KR20050002938A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
KR20050002938A
KR20050002938A KR1020030042285A KR20030042285A KR20050002938A KR 20050002938 A KR20050002938 A KR 20050002938A KR 1020030042285 A KR1020030042285 A KR 1020030042285A KR 20030042285 A KR20030042285 A KR 20030042285A KR 20050002938 A KR20050002938 A KR 20050002938A
Authority
KR
South Korea
Prior art keywords
insulating film
trench
isolation region
device isolation
etching
Prior art date
Application number
KR1020030042285A
Other languages
Korean (ko)
Other versions
KR100533886B1 (en
Inventor
박근수
Original Assignee
동부아남반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 동부아남반도체 주식회사 filed Critical 동부아남반도체 주식회사
Priority to KR10-2003-0042285A priority Critical patent/KR100533886B1/en
Publication of KR20050002938A publication Critical patent/KR20050002938A/en
Application granted granted Critical
Publication of KR100533886B1 publication Critical patent/KR100533886B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to reduce an aspect ratio and a dimple phenomenon in an NSG(Non-doped Silicate Glass) deposition process by etching an isolation region, depositing an insulating layer thereon to fill up a trench, and performing a blanket etch process. CONSTITUTION: A trench is formed on an upper surface of a silicon wafer. A first insulating layer is deposited on the trench. The first insulating layer(23) is etched. A second insulating layer(24) is deposited on an upper surface of the first insulating layer. The second insulating layer is planarized by performing a planarization process. A blanket etch process is performed to etch the first insulating layer.

Description

반도체소자 제조방법{Method for manufacturing semiconductor device}Method for manufacturing semiconductor device

본 발명은 딤플(dimple) 현상을 억제하기 위한 방법에 관한 것으로, 보다 자세하게는 반도체 공정기술이 발전함에 따라 소자분리영역(Shallow Trench Isolation) 공정의 종횡비가 갈수록 커지고 있고 소자분리영역 증착 시 균일성 향상을 위해 여러 번 증착되는 공정 흐름으로 인하여 막질과 막질 사이의 경계 면이후속 공정에 의해 막질의 심이 생겨 이러한 심의 결합이 약해져 딤플 현상이 발생하는데 이러한 현상에 의해 소자에 대한 악영향과 수율 하락을 초래하는 바, 본 발명은 이에 대한 개선에 관한 것으로서, 소자분리영역 식각 후 절연막을 증착하여 트렌치를 채우고 브랭킷 식각을 실시하여 소자분리영역 내부에 상당량의 화학기상증착(Chemical Vapor Deposition)의 절연막을 남기게 되면 종횡비가 상당히 줄어들어 NSG(Non-doped Silicate Glass, 이하 NSG) 증착시, NSG의 적층 구조가 상당히 완화되어 딤플 현상이 줄어들게 하는 방법에 관한 것이다.The present invention relates to a method for suppressing a dimple phenomenon, and more particularly, as the semiconductor processing technology is developed, the aspect ratio of the shallow trench isolation process is increasing and the uniformity is improved when the device isolation region is deposited. Due to the process flow that is deposited several times, the interface between the film quality and the film quality creates a seam of the film by a subsequent process, and the coupling of these seams is weakened, resulting in a dimple phenomenon. The present invention relates to the improvement of the present invention. When the device isolation region is etched, an insulating film is deposited to fill the trenches, and a blanket etching is performed to leave a considerable amount of chemical vapor deposition (IEC) film inside the device isolation region. The aspect ratio is significantly reduced, so when NSG (Non-doped Silicate Glass) is deposited, It relates to a method in which the laminated structure is considerably alleviated to reduce the dimple phenomenon.

소자분리영역은 특히 MOSFET 소자에서 반도체 표면에서의 전자 이동을 제어하는데 주로 사용된다. 소자분리영역 구조는 리세스형 산화물 절연(recessed oxide isolation)에 비해 종횡비가 감소하며, 상부 표면이 편평하게 되는데, 이 표면상에는 도전체가 용이하게 형성될 수 있다. 또한, 초점이 맞추어진 화상을 유지하기 위한 별도의 부가적인 피사계 심도(depth of field)가 필요로 하는 일없이 보다 양호한 해상도를 얻을 수 있으므로, 리소그래픽 노출(lithographic exposures)에 있어 상당히 유리하다.Device isolation regions are mainly used to control electron movement on the semiconductor surface, especially in MOSFET devices. The device isolation region structure has a reduced aspect ratio compared to recessed oxide isolation, and the top surface is flat, and a conductor can be easily formed on the surface. In addition, better resolution can be obtained without the need for a separate additional depth of field to maintain the focused image, which is quite advantageous for lithographic exposures.

그러나, 소자분리영역 구조를 생성하기 위해 현재 사용되고 있는 공정은 매우 복잡하고 많은 비용이 소모된다. 전형적인 공정 순서로서는, 레지스트 패터닝(resist patterning), 테이퍼(taper) 또는 비테이퍼 형의 리세스를 기판에 형성하기 위한 반응성 이온 에칭(reactive ion etch), 트렌치의 측벽 및 바닥면에 채널 차단부(channel stop)의 주입, 레지스트의 스트리핑(stripping), 트렌치 측벽 산화물을 형성하기 위한 트렌치 내의 기판 산화, 화학적 증착법(chemical vapordeposition, 이하 CVD)에 의한 산화물 충전(fill), 블랙-아웃 레지스트 패터닝(black-out resist patterning), 평탄화를 위한 건식 식각 및 트렌치 측벽상 산화물에 대한 화학기계적 연마(Chemical Mechanical Polishing, 이하 CMP) 및 어닐링(annealing)이 포함된다. 상기 및 이와 유사한 공지의 공정도 인접한 소자 영역에 고 스트레스 영역을 생성하는 경향이 있는데, 이것은 결국 반도체 기판의 결정 격자에 있어 자연 발생적인 전위 루프(dislocation loops)의 형성에 의해 해소된다. 소자분리영역 구조를 가지는 집적 회로 장치 영역 내에 생기는 소자로부터의 전하 누설(charge leakage)은 이러한 전위 루프와 연관이 있다.However, the processes currently used to create device isolation region structures are very complex and expensive. Typical process sequences include resist patterning, reactive ion etch to form tapered or non-tapered recesses in the substrate, channel trenches in the sidewalls and bottom of the trench. injection of stops, stripping of resist, oxidation of substrates in trenches to form trench sidewall oxides, oxide fill by chemical vapor deposition (CVD), black-out resist patterning (black-out) resist patterning, dry etching for planarization and chemical mechanical polishing (CMP) and annealing of oxides on the trench sidewalls. This and similar known processes also tend to create high stress regions in adjacent device regions, which are eventually eliminated by the formation of naturally occurring dislocation loops in the crystal lattice of the semiconductor substrate. Charge leakage from devices occurring within integrated circuit device regions having device isolation region structures is associated with such potential loops.

또한, 소자분리영역 구조와 관련하여,CVD 산화물로써 좁은 트렌치(narrow trench)를 충전하는 공정에 문제가 있다. 이 충전 공정은 다소 공형적으로(conformally) 진행되므로 (예를 들면, 트렌치 측면의 침착은 트렌치 바닥의 침착보다 다소 천천히 진행되나 일반적으로 그 차이는 트렌치의 종횡비보다는 작음) 좁은 트렌치의 하부 영역이 채워지기 전에 상부 영역이 채워짐으로써 공극(void)이 형성될 수도 있다.In addition, with regard to the device isolation region structure, there is a problem in the process of filling a narrow trench with CVD oxide. This filling process proceeds somewhat conformally (e.g., deposition on the trench side proceeds more slowly than deposition on the bottom of the trench, but the difference is generally less than the aspect ratio of the trench). The void may be formed by filling the upper region before it takes over.

또한, 트렌치 종횡비가 작은 소자분리영역 구조에서도, 일반적으로 공형 침착에 의해 트렌치의 상부에 표면 공극 혹은 딤플이 형성되므로, 화학적 또는 CMP와 같은 공정에 의한 복잡한 평탄화가 필요할 수도 있으며, 또한 딤플에 오염 물질이 들어 갈 수도 있다.In addition, even in a device isolation region structure having a small trench aspect ratio, since surface voids or dimples are generally formed on the trenches by the conformal deposition, complex planarization by chemical or CMP processes may be required, and contaminants may also be present in the dimples. This might go in.

현재, 트렌치 충전과 관련된 문제점을 완화시키고 스트레스를 감소시키는 유일한 기법은 광범위한 공간을 필요로 하는 트렌치 데이퍼링 공정과 트렌치 바닥면의 라운딩(rounding) 공정을 포함하고 있다. 그러나, 이러한 기법들은 단독으로 혹은 조합하여 사용되더라도, 고집적도를 유지하면서, 전술한 스트레스 감소 및 트렌치 충전 문제에 대한 해결책을 제시하지 못했다.Currently, the only techniques for mitigating problems and reducing stress associated with trench filling include trenching, which requires extensive space, and rounding of trench bottoms. However, these techniques, when used alone or in combination, do not provide a solution to the aforementioned stress reduction and trench filling problems while maintaining high integration.

일반적으로, NSG를 이용한 소자분리영역 증착 시에는 도 1a의 SEM(Scan Electron Microscopy)에서 도시된 바와 같은 증착 프로파일 구조를 갖고 있다.In general, the device isolation region deposition using NSG has a deposition profile structure as shown in the SEM (Scan Electron Microscopy) of Figure 1a.

도 1b는 종래의 소자분리영역 증착 공정 후에 CMP 공정 후의 단면을 나타내는 단면도로 NSG 적층 구조(10)가 상당히 조밀하게 증착되어 있는 것을 보여주고 있다.FIG. 1B is a cross-sectional view showing a cross section after the CMP process after the conventional device isolation region deposition process, showing that the NSG stacked structure 10 is considerably densely deposited.

소자분리영역 CMP후 이 적층구조의 끝부분의 심이 상당히 결합이 약하게 되어 있으며, 후속 게이트 식각(gate etch)시 세정 등의 영향으로 인하여 이 심이 제거되어 딤플 현상을 초래한다.After the device isolation region CMP, the seam at the end of the stacked structure is considerably weakened, and this seam is removed due to the effect of cleaning or the like during subsequent gate etching, resulting in a dimple phenomenon.

도 1c는 후속 이온주입 공정을 진행한 후 게이트 식각 및 세정까지 진행한 후의 단면도로서, 상기의 설명에 의해서 생성된 딤플(11)을 보여주고 있다.FIG. 1C is a cross-sectional view illustrating a dimple 11 generated by the above description after the gate implantation and cleaning are performed after the subsequent ion implantation process.

후속 실리카이드(silicide) 형성 시에 Ti 또는 Co 스퍼터(sputter) 증착 시 딤플에 채워져서 게이트 라인(gate line)사이의 쇼트(short)를 유발하기도 하며 딤플 그 자체로도 소자에 악영향을 미칠 수 있다.In the subsequent silicide formation, the dimple may be filled in the dimple during Ti or Co sputter deposition, causing short between the gate lines, and the dimple itself may adversely affect the device. .

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 소자분리영역 식각 후 절연막을 증착하여 트렌치를 채우고 브랭킷식각(blanket etch)을 실시하여 소자분리영역 내부에 상당량의 APCVD의 절연막을 남기게 되면 종횡비가 상당히 줄어들어 NSG 증착시, NSG의 적층 구조가 상당히 완화되어 딤플 현상이 줄어들게 되도록 하는 방법을 제공함에 본 발명의 목적이 있다.Accordingly, the present invention is to solve the problems of the prior art as described above, by depositing an insulating film after etching the device isolation region to fill the trench and blanket etching (etch blanket) a considerable amount of the insulating film of APCVD inside the device isolation region It is an object of the present invention to provide a method in which the aspect ratio is considerably reduced so that the lamination structure of the NSG is considerably alleviated to reduce the dimple phenomenon.

도 1a 내지 도 1c는 종래 기술에 의한 소자분리영역 증착 방법.1A to 1C are device isolation region deposition methods according to the prior art.

도 2는 본 발명에 의한 소자분리영역 증착 방법.2 is a device isolation region deposition method according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10 : NSG 적층 구조 11 : 딤플10: NSG laminated structure 11: dimple

20 : 오버행 21 : 캡의 중심부20: overhang 21: center of the cap

22 : 제 2절연막 25 : NSG 측벽22: second insulating film 25: NSG sidewall

본 발명의 상기 목적은 소자분리영역 식각 후 절연막을 증착하여 트렌치를 채우고 브랭킷 식각을 실시하여 소자분리영역 내부에 상당량의 화학기상증착의 절연막을 남기게 되면 종횡비가 상당히 줄어들어 NSG 증착시, NSG의 적층 구조가 상당히 완화되어 딤플 현상이 줄어들게 하는 공정으로 이루어진 딤플 현상을 억제하기 위한 방법에 의해 달성된다.The object of the present invention is to deposit an insulating film after etching the device isolation region to fill the trench and leave a significant amount of chemical vapor deposition insulating film inside the device isolation region to reduce the aspect ratio considerably reduced NSG deposition, NSG deposition This is achieved by a method for suppressing dimples, which consists of a process in which the structure is significantly relaxed to reduce the dimples.

본 발명은 소자분리영역 식각 공정 이후 소자분리영역 증착 공정 시에 절연체 증착을 진행 후에 브랭킷 식각을 실시한다. 이러한 브랭킷 식각은 포토레지스트 패턴(photoresist pattern)이 없는 식각으로 측벽 형성시의 프로파일과 마찬가지로 소자분리영역의 내부에 화학기상증착 막질이 존재한다.The present invention performs a blanket etching after the insulator deposition during the device isolation region deposition process after the device isolation region etching process. The blanket etching is an etching without a photoresist pattern, and the chemical vapor deposition film is present inside the device isolation region similar to the profile at the sidewall formation.

이러한 증착 및 식각 공정을 진행하면 소자분리영역 내부에 상당한 두께의 산화 막질이 존재하여 후속 소자분리영역 증착 공정을 진행하면 종횡비가 상당히 줄어들어 NSG의 적층 구조가 상당히 완화된다.When the deposition and etching process proceeds, there is a considerable thickness of oxide film inside the isolation region. Subsequent deposition of the isolation region significantly reduces the aspect ratio, thereby significantly alleviating the stacked structure of the NSG.

이러한 구조를 갖게 되면 후속 공정인 이온주입(implant)과 게이트 식각 세정(gate etch clean)시에 심의 부분이 존재하지 않게 되며, 이러한 이유로 딤플이 발생되지 않게 되며 이로 인해 딤플에 잔류물 막질이 없게 되는 것과 같은 후속공정의 부수적인 악영향도 제거 할 수 있게 된다.With this structure, the seam is not present during the subsequent implantation and gate etch clean, and thus dimples are not generated, resulting in no residue film on the dimples. As a result, the side effects of subsequent processes such as these can be eliminated.

이하 도면을 참조하여 본 발명에 대하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a는 소자분리영역 식각 후에 제1 절연막을 형성하는 소자분리영역 증착 공정을 진행한 후의 단면도로, 오버행(overhang)(20) 구조가 되어 캡 증착(gap fill)이 잘되지 않음을 보여 주고 있다. 이러한 이유는 상기에서 설명한 바와 같이 트렌치의 종횡비가 커질수록 더욱 심하게 발생하는 현상이다.FIG. 2A is a cross-sectional view after the device isolation region deposition process of forming the first insulating layer after the device isolation region is etched. FIG. 2A shows an overhang 20 structure, so that a cap fill is poor. . The reason for this is a phenomenon that occurs more severely as the aspect ratio of the trench increases as described above.

도 2b는 소자분리영역 증착 진행 후 패턴이 없는 브랭킷 에치를 진행하는 단면을 나타낸 것으로서, 트렌치의 위상(topology)은 중심부(21)가 가장 자리보다 더 낮은 것을 알 수 있는데 이것은 캡 증착 공정에서의 위상이 브랭킷 식각으로 인하여 그대로 유지 되면서 식각되어 이러한 형상을 하게 되는 것이다.FIG. 2B illustrates a cross-section of a patternless blanket etch after deposition of the device isolation region, in which the topology of the trench is lower than that of the edge 21 in the cap deposition process. The phase is etched while being maintained as it is due to the blanket etching to form this shape.

도 2c는 브랭킷 에치 공정 이후에 제2 절연막(22)을 증착하여 소자분리영역을 완전히 채우는 공정을 보여주는 단면도이다.2C is a cross-sectional view illustrating a process of depositing the second insulating layer 22 after the blanket etch process to completely fill the device isolation region.

도 2d는 본 발명에 의한 소자분리영역 영역의 절연막 증착 공정이 완료된 후의 단면도로, 트렌치의 하단부(23)는 화학기상증착에 의해 형성된 제1 절연막이고, 상단부(24)(24)는 브랭킷 식각 공정 이후에 재증착된 제2 절연막이다. 상기 하단부(23)의 제1 절연막과 상단부(24)의 제2 절연막을 비교하면 하단부(23)의 제1 절연막은 상단부(24)의 제2 절연막보다 종횡비가 더 커서 딤플 현상이 일어나기 쉬운 반면, 상단부(24)의 제1 절연막은 종횡비가 작아 절연체가 적층되어질 때 위상의 변화가 적어지므로 딤플 현상을 방지할 수 있다.FIG. 2D is a cross-sectional view after the insulating film deposition process in the device isolation region area according to the present invention is completed. The lower end portion 23 of the trench is a first insulating layer formed by chemical vapor deposition, and the upper end portions 24 and 24 are blanket etched. It is a 2nd insulating film redeposited after a process. Comparing the first insulating film of the lower end 23 and the second insulating film of the upper end 24, the first insulating film of the lower end 23 has a larger aspect ratio than the second insulating film of the upper end 24, so that a dimple phenomenon tends to occur. Since the aspect ratio of the first insulating film of the upper end portion 24 is small, the phase change is small when the insulators are stacked, thereby preventing the dimple phenomenon.

또한, 도 3a에서 보는 바와 같이 소자분리영역 트렌치 식각 후, 절연막을 증착하고 식각하여 NSG 측벽(25)을 형성하고, 도 3b에서 보는 바와 같이 상기 NSG 측벽(25)이 형성된 소자분리영역에 절연막(26)을 증착하는 공정을 진행하고 이후의 공정은 상기와 같이 진행하면 다른 실시예가 될 수 있다.In addition, after etching the device isolation region trench as shown in FIG. 3A, an insulating film is deposited and etched to form an NSG sidewall 25, and as shown in FIG. 3B, an insulating film is formed in the device isolation region where the NSG sidewall 25 is formed. 26) proceeds to the process of depositing and the subsequent process may be another embodiment as described above.

따라서, 본 발명의 반도체소자 제조방법은 소자분리영역 식각 후 절연막을 증착하여 트렌치를 채우고 브랭킷 에치를 실시하여 소자분리영역 내부에 상당량의 화학기상증착의 절연막을 남기게 되면 종횡비가 상당히 줄어들어 NSG 증착시, NSG의 적층 구조가 상당히 완화되어 딤플 현상이 줄어드는 효과가 있다.Therefore, the semiconductor device fabrication method of the present invention deposits an insulating film after etching the device isolation region, fills the trench, and performs a blanket etch to leave a significant amount of chemical vapor deposition insulating film inside the device isolation region, the aspect ratio is significantly reduced when NSG deposition As a result, the stacked structure of NSG is considerably alleviated, thereby reducing the dimple phenomenon.

Claims (5)

딤플 현상을 억제하기 위한 방법에 있어서,In the method for suppressing the dimple phenomenon, 실리콘 웨이퍼에 트렌치를 형성하는 단계;Forming a trench in the silicon wafer; 상기 트렌치에 제1 절연막을 증착하는 단계;Depositing a first insulating film in the trench; 상기 제1 절연막을 식각하는 단계;Etching the first insulating film; 상기 식각된 제1 절연막 위에 제2 절연막을 증착하는 단계; 및Depositing a second insulating film on the etched first insulating film; And 상기 제2 절연막을 평탄화하는 단계Planarizing the second insulating film 로 이루어짐을 특징으로 하는 반도체소자 제조방법.Method of manufacturing a semiconductor device, characterized in that consisting of. 제1항에 있어서,The method of claim 1, 상기 제1 절연막을 식각하는 단계는 블랭킷 식각을 이용하는 방법을 특징으로 하는 반도체소자 제조방법.The etching of the first insulating film is a method of manufacturing a semiconductor device, characterized in that using a blanket etching method. 딤플 현상을 억제하기 위한 방법에 있어서,In the method for suppressing the dimple phenomenon, 실리콘 웨이퍼에 트렌치를 형성하는 단계;Forming a trench in the silicon wafer; 상기 트렌치에 제1 절연막을 증착하는 단계;Depositing a first insulating film in the trench; 상기 제1 절연막을 식각하여 측벽을 형성하는 단계;Etching the first insulating film to form sidewalls; 상기 측벽이 형성된 소자분리영역에 제2 절연막을 증착하는 단계; 및Depositing a second insulating film on the device isolation region where the sidewalls are formed; And 상기 제2 절연막을 평탄화하는 단계Planarizing the second insulating film 로 이루어짐을 특징으로 하는 반도체소자 제조방법.Method of manufacturing a semiconductor device, characterized in that consisting of. 제1항 또는 제3항에 있어서,The method according to claim 1 or 3, 상기 제1 절연막 또는 제2 절연막은 산화물, 질화물 및 내열성 유기절연물 중에 어느 하나로 이루어짐을 특징으로 하는 반도체소자 제조방법.The first insulating film or the second insulating film is a semiconductor device manufacturing method, characterized in that made of any one of oxide, nitride and heat resistant organic insulating material. 제1항 또는 제3항에 있어서,The method according to claim 1 or 3, 상기 제1 절연막은 화학기상증착법으로 증착됨을 특징으로 하는 반도체소자 제조방법.The first insulating film is a semiconductor device manufacturing method, characterized in that deposited by chemical vapor deposition.
KR10-2003-0042285A 2003-06-27 2003-06-27 Method for manufacturing semiconductor device KR100533886B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-2003-0042285A KR100533886B1 (en) 2003-06-27 2003-06-27 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2003-0042285A KR100533886B1 (en) 2003-06-27 2003-06-27 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
KR20050002938A true KR20050002938A (en) 2005-01-10
KR100533886B1 KR100533886B1 (en) 2005-12-06

Family

ID=37218190

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2003-0042285A KR100533886B1 (en) 2003-06-27 2003-06-27 Method for manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR100533886B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100971207B1 (en) * 2007-08-30 2010-07-20 주식회사 동부하이텍 microlens, method of fabricating microlens thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100971207B1 (en) * 2007-08-30 2010-07-20 주식회사 동부하이텍 microlens, method of fabricating microlens thereof

Also Published As

Publication number Publication date
KR100533886B1 (en) 2005-12-06

Similar Documents

Publication Publication Date Title
KR100825014B1 (en) Method for fabricating isolation in semiconductor device
US20120264268A1 (en) Methods of forming electrical isolation regions between gate electrodes
US7566924B2 (en) Semiconductor device with gate spacer of positive slope and fabrication method thereof
KR20020055938A (en) Method of forming a isolation layer deposition in a semiconductor device
KR100533886B1 (en) Method for manufacturing semiconductor device
KR100465601B1 (en) A method for forming a semiconductor device
US7858488B2 (en) Method of forming a device isolation film of a semiconductor device
KR20050002317A (en) Method of manufacturing a semiconductor device
KR100540340B1 (en) Method For Manufacturing Semiconductor Devices
KR100732297B1 (en) Method for Forming Landing Plug Contact Hole of Semiconductor Device
CN116487419B (en) Semiconductor structure and preparation method thereof
KR20120090544A (en) Semiconductor device and method for manufacturing the same
KR100791707B1 (en) Method for polishing inter-metal dielectric layer of the semiconductor device
KR100444310B1 (en) Method for manufacturing isolation layer of semiconductor device preventing thinning at trench top corner using double o3-teos layer
KR20100079753A (en) Method of manufacturing a semiconductor device
KR20100079797A (en) Semiconductor device with buried gate and method for fabricating the same
KR20100074668A (en) Manufacturing method for isolation structure of semiconductor device
KR20070008114A (en) Method for forming the isolation layer of semiconductor device
KR20070021511A (en) Method for forming isolation layer of semiconductor device
US20070148877A1 (en) Semiconductor device and method for fabricating the same
KR20050014221A (en) A method for manufacturing a field oxide of a semiconductor device
KR100226735B1 (en) Method of forming a device isolation film of semiconductor device
KR20050003061A (en) Fabricating method for trench isoaltion layer using bottom anti reflection coating
KR100760829B1 (en) Dual trench isolation method and fabrication method of flash memory device using active area etching method
KR100822605B1 (en) Method of forming a isolation in flash memory device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20111020

Year of fee payment: 7

FPAY Annual fee payment

Payment date: 20121026

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee