KR20050002515A - Method for forming metal line contact of semiconductor device - Google Patents

Method for forming metal line contact of semiconductor device Download PDF

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Publication number
KR20050002515A
KR20050002515A KR1020030043895A KR20030043895A KR20050002515A KR 20050002515 A KR20050002515 A KR 20050002515A KR 1020030043895 A KR1020030043895 A KR 1020030043895A KR 20030043895 A KR20030043895 A KR 20030043895A KR 20050002515 A KR20050002515 A KR 20050002515A
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South Korea
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forming
ray
semiconductor device
photoresist
pattern
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KR1020030043895A
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Korean (ko)
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정중택
조성윤
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주식회사 하이닉스반도체
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Priority to KR1020030043895A priority Critical patent/KR20050002515A/en
Publication of KR20050002515A publication Critical patent/KR20050002515A/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

PURPOSE: A method of forming a metal line contact hole of a semiconductor device is provided to obtain an excellent image and uniform CD(Critical Dimension) from a photoresist pattern by using multispot beams of an X-ray nano-lithography. CONSTITUTION: A lower layer(21), an oxide layer(23) and a photoresist layer are sequentially formed on a semiconductor substrate. A photoresist pattern is formed by patterning selectively the photoresist layer using multispot beams of an X-ray nano-lithography associated with a concavity type lens. A metal line contact hole is formed by patterning selectively the oxide layer using the photoresist pattern as an etching mask.

Description

반도체소자의 금속배선콘택 형성방법{Method for forming metal line contact of semiconductor device}Method for forming metal line contact of semiconductor device

본 발명은 반도체소자의 금속배선콘택 형성방법에 관한 것으로서, 보다 상세하게는 오목형 렌즈를 가진 X-레이 나노리소그라피의 다중점 빔(multispot beam)을 이용하여 보다 양호한 이미지 형성과 CD 균일도를 향상시킬 수 있는 반도체소자의 금속배선콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metallization contact forming method of a semiconductor device, and more particularly, to improve image formation and CD uniformity by using a multispot beam of X-ray nanolithography having a concave lens. The present invention relates to a method for forming a metal wiring contact of a semiconductor device.

반도체 디바이스가 고집적화될수록 패턴 해상도의 감소는 피할 수 없는 현실이다. 이를 해결하기 위해 PR 두께를 감소하는 방법으로 패터닝을 포토에서 실시하고 있으나 PR 두께가 감소하면 식각 선택비 부족으로 식각완료되기 전에 PR이 없어져 패턴 상부 손실, 줄무늬(striation), CD 불안정 등을 유발시켜 디바이스에 악영향을 끼친다.As semiconductor devices become more integrated, a decrease in pattern resolution is inevitable. In order to solve this problem, patterning is performed in the photo as a method of reducing the PR thickness. However, when the PR thickness is reduced, the PR disappears before the etching is completed due to the lack of etching selectivity, leading to pattern top loss, striation, and CD instability. This will adversely affect the device.

또한, 비트라인콘택 마스크진행시에 홀내부 직경이 너무 작아, 예를들어 130nm 정도, 마스크 마진부족으로 홀내부 직경을 크게 만든후 열을 가하여 PR 플로우로 홀 타겟을 맞추었다.In addition, the hole inside diameter was too small at the time of the bit line contact mask, for example, about 130 nm, the hole inside diameter was made large due to lack of mask margin, and heat was applied to fit the hole target with the PR flow.

그러나, 이러한 기술은 열 전달이 고르게 되지 않아 CD 균일도도 불량하고, 패턴해상도도 좋지 않아서 웨이퍼 가장자리쪽의 패턴은 개구가 되지 않는 현상을 유발하기도 한다.However, such a technique causes poor CD uniformity due to uneven heat transfer and poor pattern resolution, resulting in a pattern at the edge of the wafer not opening.

보다 CD 균일도를 양호하게 만들기 위해 PR 두께를 감소시켜 해상도를 높히려고 하나 식각선택비 부족으로 상부 노치(top notch) 염려가 있어서 PR 두께 감소도 어려운 실정이다.In order to improve the CD uniformity, the PR thickness is reduced to increase the resolution, but there is a concern of the top notch due to the lack of etching selectivity.

감광막에 대한 식각 마진이 충분하면서 패턴 해상도 및 CD 균일도가 양호한 기술이 필요한 실정이다.There is a need for a technique in which the etching margin for the photoresist film is sufficient and the pattern resolution and CD uniformity are good.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 오목형 렌즈를 가진 X-레이 나노리소그라피의 다중점 빔(multispot beam )을 이용하여 보다 양호한 이미지 형성과 CD 균일도를 향상시킬 수 있는 반도체 소자의 금속배선콘택 형성방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above problems of the prior art, by using a multi-spot beam of X-ray nanolithography having a concave lens can improve image formation and CD uniformity better. It is an object of the present invention to provide a method for forming a metal interconnection contact of a semiconductor device.

도 1은 본 발명에 따른 금속배선 콘택 형성방법에 있어서, 포커싱 X-레이 마스크를 실시하는 것을 보여 주는 사시도,1 is a perspective view showing the implementation of a focusing X-ray mask in the metallization contact forming method according to the present invention;

도 2a 및 도 2b는 본 발명에 따른 반도체소자의 금속배선콘택 형성방법을 설명하기 위한 공정단면도.2A and 2B are cross-sectional views illustrating a method of forming a metallization contact of a semiconductor device according to the present invention.

[도면부호의설명][Description of Drawing Reference]

21 : 하부층 23 : 산화막21: lower layer 23: oxide film

25 : 감광막 25a : 감광막패턴25 photosensitive film 25a photosensitive film pattern

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속배선콘택 형성방법은, 반도체기판상의 하부층상에 산화막을 형성한후 상기 산화막상에 감광막을 도포하는 단계;Method for forming a metal wiring contact of a semiconductor device according to the present invention for achieving the above object comprises the step of forming an oxide film on the lower layer on the semiconductor substrate and then applying a photosensitive film on the oxide film;

광소스 및 빔라인을 이용한 렌즈를 가진 X-레이 나노리소그라피 다중점 빔을 이용하여 상기 감광막을 조사한후 현상 및 패터닝공정을 거쳐 감광막 패턴을 형성하는 단계; 및Irradiating the photoresist using an X-ray nanolithography multi-point beam having a lens using a light source and a beamline to form a photoresist pattern through development and patterning; And

상기 감광막패턴을 마스크로 상기 산화막을 패터닝하여 금속배선콘택을 형성 하는 단계를 포함하여 구성되는 것을 특징으로한다.And forming a metal wiring contact by patterning the oxide film using the photoresist pattern as a mask.

(실시예)(Example)

이하, 본 발명에 따른 반도체 소자의 금속배선콘택 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method for forming a metal wiring contact of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명에 따른 금속배선 콘택 형성방법에 있어서, 포커싱 X-레이 마스크를 이용하여 실시하는 공정을 도시한 개략도이다.1 is a schematic diagram showing a process performed using a focusing X-ray mask in the metallization contact forming method according to the present invention.

도 2a 및 도 2b는 본 발명에 따른 반도체소자의 금속배선콘택 형성방법을 설명하기 위한 공정단면도이다.2A and 2B are cross-sectional views illustrating a method of forming a metallization contact of a semiconductor device according to the present invention.

본 발명에 따른 금속배선콘택 형성방법은, 도 2a에 도시된 바와같이, 먼저 하부층(21)상에 산화막(23)을 증착한후 상기 산화막(23)상에 감광막(25)을 도포한다.In the method for forming a metallization contact according to the present invention, as shown in FIG. 2A, an oxide film 23 is first deposited on the lower layer 21, and then a photosensitive film 25 is coated on the oxide film 23.

그다음, 도 2b에 도시된 바와같이, 새롭게 디자인된 광소스 및 빔라인을 이용한 오목렌즈를 가진 X-레이 나노리소그라피이 다중점 빔을 이용하여 상기 감광막(25)을 조사한후 현상 및 패터닝공정을 거쳐 감광막패턴(25a)을 형성한다. 이때, 새롭게 디자인된 광소스 및 빔라인을 이용하는데, 높은 에너지 포톤빔 (photon beam)으로 이미지 형태기능(formability)를 증가시킨다. 여기서, 광소스는 오로라 (aurora) 3 (1.0 GeV)를 이용한다. 또한, 임계 파장은 0.65∼ 0.70nm로 한다.Next, as shown in FIG. 2B, the X-ray nanolithography having a concave lens using a newly designed light source and a beamline is irradiated to the photosensitive film 25 using a multi-point beam, followed by a development and patterning process. Form 25a. In this case, a newly designed light source and a beamline are used to increase image formability with a high energy photon beam. Here, the light source uses aurora 3 (1.0 GeV). The critical wavelength is 0.65 to 0.70 nm.

그리고, 마스크 멤브레인은 2μm, 다이아몬드를 이용하고 메디안 파장은 0.50∼0.55 nm를 이용한다.The mask membrane is 2 탆, diamond is used, and the median wavelength is 0.50 to 0.55 nm.

또한, 렌즈는 오목렌즈(concave lenses)를 이용하는데, 마스크(31)의 멤브 레인위에 정상 패턴(regular pattern)으로 배열되어 있고, 흡수층으로 구성되어 있다. 여기서, 오목렌즈로 웨이퍼(21)위에 X-레이를 포커스하는데 X-레이에 대한 흡수 물질의 굴절률(index of refraction)이 단일(unity)보다 작은 것이 특징이어서 패턴 해상도를 높이게 된다.In addition, the lens uses concave lenses, which are arranged in a regular pattern on the membrane lane of the mask 31, and are composed of an absorbing layer. Here, the X-rays are focused on the wafer 21 with the concave lens, and the index of refraction of the absorbing material with respect to the X-rays is smaller than unity, thereby increasing the pattern resolution.

도면에는 도시하지 않았지만, 상기와 같은 방법으로 BLC 콘택을 진행하면 감광막 플로우없이 해상도를 높일 수 있고, CD 균일도도 증가시킬 수 있다.Although not shown in the figure, if the BLC contact is made in the same manner as described above, the resolution can be increased without the photoresist flow and the CD uniformity can be increased.

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 금속배선 콘택 형성방법에 의하면, 기존에 반도체소자의 비트라인콘택 마스크 형성시에 리소그라피의 한계로 홀내의 직경을 크게 만든후 열을 가하여 PR 플로우를 시키므로써 홀 직경을 감소시켜으나 이로 인해 CD 불량, 웨이퍼 가장자리의 개구되지 않는 문제등을해결하고자 오목형 렌즈를 가진 X-레이 나노리소그라피의 다중점 빔(multispot beam)을 이용하여 보다 양호한 이미지 형성과 CD 균일도를 향상시킬 수 있다.As described above, according to the method for forming a metallization contact of a semiconductor device according to the present invention, when forming a bit line contact mask of a semiconductor device, a PR flow is applied by applying heat after making a large diameter in a hole to the limit of lithography. This reduces the diameter of the hole, but this results in better image formation by using multi-spot beams of X-ray nanolithography with concave lenses to solve CD defects and wafer openings. CD uniformity can be improved.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (6)

반도체기판상의 하부층상에 산화막을 형성한후 상기 산화막상에 감광막을 도포하는 단계;Forming an oxide film on the lower layer on the semiconductor substrate and then applying a photosensitive film on the oxide film; 광소스 및 빔라인을 이용한 렌즈를 가진 X-레이 나노리소그라피 다중점 빔을 이용하여 상기 감광막을 조사한후 현상 및 패터닝공정을 거쳐 감광막 패턴을 형성하는 단계; 및Irradiating the photoresist using an X-ray nanolithography multi-point beam having a lens using a light source and a beamline to form a photoresist pattern through development and patterning; And 상기 감광막패턴을 마스크로 상기 산화막을 패터닝하여 금속배선콘택을 형성 하는 단계를 포함하여 구성되는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.And forming a metal wiring contact by patterning the oxide film using the photoresist pattern as a mask. 제1항에 있어서, 상기 광소스는 오로라 (aurora) 3 (1.0 GeV)를 이용하고, 임계 파장은 0.65∼ 0.70nm로 하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein the light source uses Aurora 3 (1.0 GeV) and has a critical wavelength of 0.65 to 0.70 nm. 제1항에 있어서, 상기 X-레이 나노리소그라피 다중점 빔대신에 이온빔, E-빔을 사용하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein an ion beam or an E-beam is used instead of the X-ray nanolithography multi-point beam. 제1항에 있어서, 상기 렌즈는 오목렌즈를 사용하며, 마스크멤브레인위에 정상패턴이 배열되어 있고, 흡수층으로 구성되어 있는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein the lens uses a concave lens, and a normal pattern is arranged on the mask membrane, and the absorbing layer is formed. 제4항에 있어서, 상기 X-레이에 대한 흡수층물질의 굴절률은 단일보다 작은 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 4, wherein a refractive index of the absorber layer material with respect to the X-ray is less than a single unit. 제1항에 있어서, 광소스 및 빔라인을 이용한 렌즈를 가진 X-레이 나노리소그라피 다중점 빔을 이용한 패터닝공정은 1000 nm 이하의 패턴 형성시에 적용하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein the patterning process using an X-ray nanolithography multi-point beam having a lens using an optical source and a beamline is applied when forming a pattern of 1000 nm or less. .
KR1020030043895A 2003-06-30 2003-06-30 Method for forming metal line contact of semiconductor device KR20050002515A (en)

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