KR20050002490A - Method for forming fine pattern of semiconductor device - Google Patents

Method for forming fine pattern of semiconductor device Download PDF

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KR20050002490A
KR20050002490A KR1020030043869A KR20030043869A KR20050002490A KR 20050002490 A KR20050002490 A KR 20050002490A KR 1020030043869 A KR1020030043869 A KR 1020030043869A KR 20030043869 A KR20030043869 A KR 20030043869A KR 20050002490 A KR20050002490 A KR 20050002490A
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etching
semiconductor device
forming
photoresist pattern
flare
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KR1020030043869A
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Korean (ko)
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조성윤
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주식회사 하이닉스반도체
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Publication of KR20050002490A publication Critical patent/KR20050002490A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A method of forming a fine pattern of a semiconductor device is provided to improve device properties by using two-step etching under predetermined gas conditions. CONSTITUTION: A flare layer(33), an oxide layer(35) and a photoresist pattern(37) are sequentially formed on a lower layer(31). A first etching process is performed on the oxide layer by using the photoresist pattern as an etching mask under a CF4/CHF3 gas atmosphere. A second etching process is performed on the flare layer by using an outer phase pulse modulation under a CH3NH2/N2 gas atmosphere. The first and second etching processes are performed in a bit of NLD(Neutral Loop Discharge) type etching equipment.

Description

반도체소자의 미세패턴 형성방법{Method for forming fine pattern of semiconductor device}Method for forming fine pattern of semiconductor device

본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로서, 보다 상세하게는 NLD(neutral loop discharge) 플라즈마에 CH3NH2/N2가스로 외부위상 펄스 모듈레이션을 이용하여 미세 트렌치 방지와 하드마스크 감소 방지 및 RIE 레그(lag), 정상적인 테이퍼진 프로파일을 형성하여 디바이스 특성을 향상시킬 수 있는 반도체소자의 미세패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly, to prevent fine trenches and hard masks by using external phase pulse modulation with CH 3 NH 2 / N 2 gas in a NLD plasma. And a method of forming a fine pattern of a semiconductor device capable of improving device characteristics by forming a RIE lag and a normal tapered profile.

반도체소자의 구리 다마신 집적화 공정에서 절연물질로서는 저유전물질을 이용해야 한다. 위와 같은 저유전물질을 사용해야 하는 이유는 디바이스의 기술이 축소될지라도 높은 스피드 동작과 작은 파워소모로 높은 실효성을 성취하기 위해서다.In the copper damascene integration process of the semiconductor device, a low dielectric material should be used as the insulating material. The reason for using such low dielectric materials is to achieve high effectiveness with high speed operation and small power consumption even if the technology of the device is reduced.

저유전상수의 대표적인 물질로서는 플레어(flare) (k=2.8) 가 있는데, 이 물질은 기존에 RIE에 H2/N2또는 NH3플라즈마를 사용했었다.Representative material of low dielectric constant is flare (k = 2.8), which has previously used H 2 / N 2 or NH 3 plasma for RIE.

그러나, 상기와 같이 식각시에 바윙 프로파일 경향(bowing profile tendency), 미세 트렌치화, 하드마스크 감소, RIE 레그(reactive ion etching lag) 등 이상과 같은 문제점들이 발생하여 정상적인 테이퍼 프로파일 형성에 어려움이 있다.However, as described above, problems such as bowing profile tendency, fine trenching, hard mask reduction, reactive ion etching lag, and the like may be difficult to form a normal taper profile during etching.

한편, 기존의 RIE에 H2/N2또는 NH3대체가스로 CH4/N2를 이용한 경우에 수직한 식각은 가능하지만 CHx라디칼의 과다발생으로 웨이퍼의 상부표면에도 발생하여 문제점을 유발시키게 된다.On the other hand, in the case of using CH 4 / N 2 as an alternative gas to H 2 / N 2 or NH 3 in the existing RIE, vertical etching is possible, but excessive generation of CH x radicals also occurs on the upper surface of the wafer, causing problems. do.

이와 같은 문제점을 해결하기 위한 보다 진보된 기술이 필요한 시점이다.It is time for more advanced technology to solve this problem.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, NLD(neutral loop discharge) 플라즈마에 CH3NH2/N2가스로 외부위상 펄스 모듈레이션을 이용하여 미세 트렌치 방지와 하드마스크 감소 방지 및 RIE 레그(lag),정상적인 테이퍼진 프로파일을 형성하여 디바이스 특성을 향상시킬 수 있는 반도체소자의 미세패턴 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, by using an external phase pulse modulation with CH 3 NH 2 / N 2 gas in NLD (neutral loop discharge) plasma to prevent fine trench and prevent hard mask reduction And a method for forming a fine pattern of a semiconductor device capable of improving device characteristics by forming a RIE lag and a normal tapered profile.

도 1은 본 발명에 따른 반도체소자의 미세패턴 형성방법을 설명하기 위한 NLD(neutral loop discharge) 플라즈마 식각시스템의 개략도,1 is a schematic diagram of a NLD plasma etching system for explaining a method of forming a fine pattern of a semiconductor device according to the present invention;

도 2a 내지 도 2c는 본 발명에 따른 반도체소자의 미세패턴 형성방법을 설명하기 위한 공정단면도.2A to 2C are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the present invention.

[도면부호의설명][Description of Drawing Reference]

31 : 하부층 33 : 플레어막31: lower layer 33: flare film

35 : 산화막 37 : 감광막패턴35 oxide film 37 photosensitive film pattern

상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 미세패턴 형성방법 은,Method for forming a fine pattern of a semiconductor device according to the present invention for achieving the above object,

하부층상에 플레어막과 산화막을 순차적으로 적층하는 단계;Sequentially stacking a flare film and an oxide film on the lower layer;

상기 산화막상에 감광막패턴을 형성하는 단계;Forming a photoresist pattern on the oxide film;

상기 감광막패턴을 배리어로 CF4/CHF3가스를 이용한 제1식각공정에 의해 상기 산화막을 식각하는 단계; 및Etching the oxide film by a first etching process using CF 4 / CHF 3 gas as the barrier using the photoresist pattern; And

상기 감광막패턴과 산화막을 배리어로 CH3NH2/N2가스로 외부위상펄스 모듈레이션을 이용한 제2식각공정에 의해 상기 플레어막을 식각하는 단계를 포함하여 구성되는 것을 특징으로한다.And etching the flare film by a second etching process using an external phase pulse modulation with CH 3 NH 2 / N 2 gas using the photoresist pattern and the oxide film as a barrier.

(실시예)(Example)

이하, 본 발명에 따른 반도체소자의 미세패턴 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a fine pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명에 따른 반도체소자의 미세패턴 형성방법을 설명하기 위한 NLD(neutral loop discharge) 플라즈마 식각시스템의 개략도이다.1 is a schematic diagram of a NLD plasma etching system for explaining a method for forming a micropattern of a semiconductor device according to the present invention.

도 2a 내지 도 2c는 본 발명에 따른 반도체소자의 미세패턴 형성방법을 설명하기 위한 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the present invention.

본 발명에 따른 반도체소자의 미세패턴 형성방법은, 도 1에 도시된 바와같이, 유기 저유전상수의 플레어(flare) 물질을 절연물질로서 사용하고, 식각장비로 NLD(magnetic neutral loop discharge) 타입에 CH3NH2/N2가스로 외부위상 펄스모듈레이션을 이용한다. 여기서, 미설명부호 1는 식각챔버, 3은 하부전극, 5는 상부전극, 7은 가스입구, 9는 유도코일, 11은 마그네틱 코일, 13은 QMS, 21은 웨이퍼이다.In the method of forming a micropattern of a semiconductor device according to the present invention, as shown in FIG. 1, a flare material of an organic low dielectric constant is used as an insulating material, and CH is formed in an NLD type as an etching equipment. 3 Use external phase pulse modulation with NH 2 / N 2 gas. Here, reference numeral 1 denotes an etch chamber, 3 lower electrode, 5 upper electrode, 7 gas inlet, 9 induction coil, 11 magnetic coil, 13 QMS, and 21 wafer.

또한, 식각시에 소스 주파수는 10∼20 MHz를 사용하고 바이어스 주파수는 1∼10MHz를 사용한다.In the etching process, the source frequency is 10 to 20 MHz and the bias frequency is 1 to 10 MHz.

도 1에 도시된 마그네틱 NLD 플라즈마 식각시스템을 이용한 반도체소자의 미세패턴 형성방법에 대해 설명하면, 먼저 도 2a에 도시된 바와같이, 하부층(31)상에 플레어막(33)을 증착하고 이어 상기 플레어막(33)상에 산화막(35)을 증착한다.A method of forming a micropattern of a semiconductor device using the magnetic NLD plasma etching system illustrated in FIG. 1 will be described. First, as shown in FIG. 2A, a flare film 33 is deposited on the lower layer 31, and then the flare is formed. An oxide film 35 is deposited on the film 33.

그다음, 상기 산화막(35)상에 레지스트막(37)을 도포한후 이를 포토리소그라피 공정기술에 의한 노광 및 현상공정을 거친후 선택적으로 제거하여 감광막패턴(37)을 형성한다.Then, after the resist film 37 is applied on the oxide film 35, the photoresist film pattern 37 is formed by selectively removing the resist film 37 after the exposure and development processes using the photolithography process technology.

이어서, 도 2b에 도시된 바와같이, 상기 감광막패턴(37)을 배리어로 제1식각공정을 진행하여 상기 산화막(35)을 식각한다. 이때, 상기 식각조건으로는 기존의 CF4/CHF3등의 가스를 이용한다.Subsequently, as illustrated in FIG. 2B, the oxide layer 35 is etched by performing a first etching process using the photoresist pattern 37 as a barrier. In this case, as the etching condition, a conventional gas such as CF 4 / CHF 3 is used.

그다음, 상기 감광막패턴(37) 및 산화막(35)을 배리어로 제2식각공정을 진행하여 상기 저유전상수의 플레어막(33)을 식각한다. 이때, 제2식각공정시의 조건으로 CH3NH2/N2가스로 외부위상 펄스 모듈레이션을 이용하는데, 외부위상펄스 모듈레이션을 부분적으로 적용해도 무방하다.Next, a second etching process is performed using the photoresist pattern 37 and the oxide film 35 as a barrier to etch the flare film 33 having the low dielectric constant. At this time, the external phase pulse modulation is used with CH 3 NH 2 / N 2 gas as a condition during the second etching process, but the external phase pulse modulation may be partially applied.

외부위상펄스 모듈레이션을 적용하면 이온 충돌(ion bombardment)와 직진성이 증가하는데 이로 인해 정상적인 테이퍼 프로파일 형성에 도움을 줄 수 있고 내부 프로파일 바닥부분까지 이온의 영향력이 잘 전달되고 더불어 RIE-레그로 인한 식각프로파일 저하(degradation)를 방지하는 NLD 플라즈마에서 식각하기 때문에 더욱더 효과적이다.The application of external phase pulse modulation increases ion bombardment and straightness, which can help to form a normal taper profile, transfer ions to the bottom of the inner profile well, and etch profiles due to RIE legs. It is even more effective because it is etched in NLD plasma which prevents degradation.

또한, 저 파워에서도 이온 충돌이 뛰어나기 때문에 장비의 파워 소모를 줄일 수 있다.In addition, the ion collision is excellent even at low power, thereby reducing the power consumption of the equipment.

외부 위상펄스 모듈레이션 원리는 소스파워가 동작시에 바이어스파워는 오프되고 소스파워가 오프시에 바이어스파워는 온되는 원리이다.The external phase pulse modulation principle is that when the source power is in operation, the bias power is off, and when the source power is off, the bias power is on.

이러한 원리로 식각을 하면 이온충돌이 높고 직진성도 뛰어나 수직한 프로파일을 만들 수 있다.Etching on this principle produces a vertical profile with high ion collisions and excellent straightness.

또한, CH3NH2/N2가스는 기존에 사용한 N2/H2, NH3가스에 비해 홀내부에 적합한 폴리머 증착으로 수직적 식각프로파일을 형성할 수 있는 장점이 있다.In addition, the CH 3 NH 2 / N 2 gas has the advantage of forming a vertical etching profile by the suitable polymer deposition inside the hole compared to the conventional N 2 / H 2 , NH 3 gas.

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 미세패턴 형성방법에 의하면, NLD(neutral loop discharge) 플라즈마에 CH3NH2/N2가스로 외부위상 펄스 모듈레이션을 이용하여 미세 트렌치 방지와 하드마스크 감소 방지 및 RIE 레그(lag), 정상적인 테이퍼진 프로파일을 형성하여 디바이스 특성을 향상시킬 수있는 것이다.As described above, according to the method for forming a micropattern of a semiconductor device according to the present invention, a fine trench prevention and a hard mask are performed by using external phase pulse modulation with CH 3 NH 2 / N 2 gas in a NLD plasma. It is possible to improve the device characteristics by preventing reduction and forming RIE lag, normal tapered profile.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (4)

하부층상에 플레어막과 산화막을 순차적으로 적층하는 단계;Sequentially stacking a flare film and an oxide film on the lower layer; 상기 산화막상에 감광막패턴을 형성하는 단계;Forming a photoresist pattern on the oxide film; 상기 감광막패턴을 배리어로 CF4/CHF3가스를 이용한 제1식각공정에 의해 상기 산화막을 식각하는 단계; 및Etching the oxide film by a first etching process using CF 4 / CHF 3 gas as the barrier using the photoresist pattern; And 상기 감광막패턴과 산화막을 배리어로 CH3NH2/N2가스로 외부위상펄스 모듈레이션을 이용한 제2식각공정에 의해 상기 플레어막을 식각하는 단계를 포함하여 구성되는 것을 특징으로하는 반도체소자의 미세패턴 형성방법.Etching the flare film by a second etching process using an external phase pulse modulation with CH 3 NH 2 / N 2 gas using the photoresist pattern and the oxide film as a barrier. Way. 제1항에 있어서, 상기 제1 및 제2 식각공정은 NLD(neutral loop discharge) 타입의 식각장비내에서 진행하는 것을 특징으로하는 반도체소자의 미세패턴 형성방법.The method of claim 1, wherein the first and second etching processes are performed in an etching apparatus of a NLD (neutral loop discharge) type. 제1항에 있어서, 상기 외부 위상 펄스 주기는 수 μs ∼ 수십 μs인 것을 특징으로하는 반도체소자의 미세패턴 형성방법.The method of claim 1, wherein the external phase pulse period is several μs to several tens of μs. 제1항에 있어서, 상기 식각공정시에 소스 주파수는 10∼20MHz를 사용하고, 바이어스 주파수는 1∼10MHz를 사용하는 것을 특징으로하는 반도체소자의 미세패턴형성방법.The method of claim 1, wherein a source frequency is 10-20 MHz and a bias frequency is 1-10 MHz during the etching process.
KR1020030043869A 2003-06-30 2003-06-30 Method for forming fine pattern of semiconductor device KR20050002490A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114411149A (en) * 2022-01-14 2022-04-29 重庆赛帕斯汽车零部件股份有限公司 Chemical etching line device for producing metal horn mesh enclosure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114411149A (en) * 2022-01-14 2022-04-29 重庆赛帕斯汽车零部件股份有限公司 Chemical etching line device for producing metal horn mesh enclosure
CN114411149B (en) * 2022-01-14 2023-09-22 重庆赛帕斯汽车零部件股份有限公司 Chemical etching line device for producing metal loudspeaker net cover

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