KR20050002319A - Mehtod of forming device's isolation layer in semiconductor device - Google Patents
Mehtod of forming device's isolation layer in semiconductor device Download PDFInfo
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- KR20050002319A KR20050002319A KR1020030043690A KR20030043690A KR20050002319A KR 20050002319 A KR20050002319 A KR 20050002319A KR 1020030043690 A KR1020030043690 A KR 1020030043690A KR 20030043690 A KR20030043690 A KR 20030043690A KR 20050002319 A KR20050002319 A KR 20050002319A
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- 238000002955 isolation Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 더욱 상세하게는 플래시메모리소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly to a method of forming a device isolation film of a flash memory device.
일반적으로 반도체소자의 소자분리막 형성방법을 도 1에 도시하고 있다.In general, a method of forming a device isolation film of a semiconductor device is shown in FIG. 1.
도 1을 참조하면, 반도체기판(10) 상에 터널산화막(12), 제1 폴리실리콘막(14) 및 패드용 질화막(미도시)을 순차적으로 형성하고, 상기 결과물의 소정영역에 포토레지스트 패턴을 형성한 후 이를 식각마스크로 식각공정을 수행하여 소자분리영역을 정의하는 트렌치(trench; T)를 형성한다.Referring to FIG. 1, a tunnel oxide film 12, a first polysilicon film 14, and a pad nitride film (not shown) are sequentially formed on a semiconductor substrate 10, and a photoresist pattern is formed on a predetermined region of the resultant. After the formation of the trenches, an etching process is performed using an etching mask to form trenches T, which define device isolation regions.
이때 형성되는 트렌치는 특정한 기울기(slope)를 갖게 되는 데, 이는 상기 수행되는 식각공정에 대한 패드용 질화막의 특성으로 인해 기울기를 가지는 질화막이 형성되고, 이 기울기를 갖는 패드용 질화막 및 상기 포토레지스트 패턴을 식각마스크로 하부의 막질 즉, 제1 폴리실리콘막(14), 터널산화막(12) 및 반도체기판(10)을 식각하여 트렌치를 형성하기 때문이다.At this time, the trench is formed to have a specific slope, which is due to the characteristics of the nitride film for the pad to the etching process is performed, a nitride film having a slope is formed, the nitride film for the pad having the slope and the photoresist pattern This is because a trench is formed by etching the lower film quality, that is, the first polysilicon film 14, the tunnel oxide film 12, and the semiconductor substrate 10, using an etch mask.
이와 같이 형성된 상기 트렌치 내부에 갭필(gap fill)특성이 우수한 산화막이 채워지도록 증착한 후 상기 패드용 질화막이 노출될 때까지 평탄화공정을 수행하여 소자분리막을 형성한 후 패드용 질화막을 제거한다. 이때 형성되는 소자분리막은 기울기가 크다.After depositing an oxide film having a good gap fill property to fill the trench formed as described above, a planarization process is performed until the pad nitride film is exposed to form a device isolation film, and then the pad nitride film is removed. At this time, the device isolation film formed has a large slope.
그리고 상기 형성된 소자분리막의 전면에 제2 폴리실리콘막을 증착한 후 식각공정을 수행하여 플로팅게이트전극의 형성을 완료한다.The second polysilicon film is deposited on the entire surface of the formed device isolation film, and then an etching process is performed to complete formation of the floating gate electrode.
그러나 상기 제2 폴리실리콘막의 식각공정시 기울기가 큰 소자분리막의 측벽 즉, 도 1의 A 지점에는 폴리실리콘막이 잔존하게 되어 인접한 플로팅 게이트전극들은 접촉하게 된다. 이로 인해 EFH(effective Field Height)의 형성을 방해하는 소자분리막이 되는 문제점이 있다.However, during the etching process of the second polysilicon layer, the polysilicon layer remains on the sidewall of the device isolation layer, that is, the point A of FIG. 1, so that adjacent floating gate electrodes are in contact with each other. As a result, there is a problem in that the device isolation film is prevented from forming the effective field height (EFH).
상술한 문제점을 해결하기 위한 본 발명의 목적은 기울기가 큰 소자분리막의 형성을 방지할 수 있도록 하여 EFH(effective Field Height)를 만족하는 반도체소자의 소자분리막 형성방법을 제공함에 있다.An object of the present invention for solving the above problems is to provide a method for forming a device isolation film of a semiconductor device that satisfies the effective field height (EFH) by preventing the formation of a device insulator film having a large inclination.
도 1은 종래 기술에 따라 형성된 반도체소자의 소자분리막 형성방법을 설명하기 위해 도시한 단면도이고,1 is a cross-sectional view illustrating a method of forming a device isolation film of a semiconductor device formed according to the prior art;
도 2 내지 도 4는 본 발명의 바람직한 일실시예에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 단면도들이다.2 to 4 are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 반도체기판 12: 웰영역10: semiconductor substrate 12: well region
14; 문턱전압 조절용 이온이 주입된 영역14; Threshold voltage implanted area
16: 터널산화막 18: 제1 폴리실리콘막16: tunnel oxide film 18: first polysilicon film
20: 제1 질화막 22: 제1 산화막20: first nitride film 22: first oxide film
24: 제2 질화막 26: 제2 산화막24: second nitride film 26: second oxide film
28: 제3 질화막 30; 소자분리막28: third nitride film 30; Device Separator
32: 제2 폴리실리콘막32: second polysilicon film
상술한 목적을 달성하기 위한 본 발명의 사상은 반도체기판 상에 터널산화막, 플로팅게이트전극용 제1 폴리실리콘막을 순차적으로 형성하는 단계; 상기 제1 폴리실리콘막 상에 질화막과 산화막이 적어도 1회 반복 적층되고 최상부가 질화막으로 이루어진 패드층을 형성하는 단계; 상기 결과물 상에 포토레지스트 패턴을 형성한 후, 상기 패드층, 제1 폴리실리콘막, 터널산화막을 순차적으로 식각하여 소자분리영역을 정의하는 버티컬한 트렌치를 형성하는 단계; 상기 버티컬한 트렌치에 산화막을 매립하여 소자분리막을 형성하는 단계; 및 상기 패드층을 제거하는 단계를 포함한다.The idea of the present invention for achieving the above object is a step of sequentially forming a tunnel oxide film, a first polysilicon film for the floating gate electrode on the semiconductor substrate; Forming a pad layer on which the nitride film and the oxide film are repeatedly stacked at least once on the first polysilicon film and having an uppermost portion formed of a nitride film; Forming a vertical trench defining a device isolation region by sequentially etching the pad layer, the first polysilicon layer, and the tunnel oxide layer after forming a photoresist pattern on the resultant; Embedding an oxide film in the vertical trench to form a device isolation film; And removing the pad layer.
상기 패드층을 이루는 질화막은 반응기체로서 NH3와 SiH2Cl2가스를 이용하여 1~ 3torr 정도의 압력 및 650~ 800℃ 정도의 온도에서 LP- CVD법으로 형성하는 것이 바람직하다.The nitride layer constituting the pad layer is preferably formed by LP-CVD at a pressure of about 1 to 3 tor and a temperature of about 650 to 800 ° C. using NH 3 and SiH 2 Cl 2 gas as the reactor.
상기 패드층을 이루는 산화막은 600~ 700℃ 정도의 온도, 1~ 3torr 정도의 압력 및 810~ 850℃ 정도의 온도에서 LP- CVD법으로, SiH2Cl2(DichloroSilane; DCS)를 소스로 한 HTO(high temperature oxide)막 또는 N2O가스를 소스로 한 HTO막 중 어느 하나로 형성하는 것이 바람직하다.The oxide layer constituting the pad layer is LP-CVD at a temperature of about 600 to 700 ° C., a pressure of about 1 to 3 tor, and a temperature of about 810 to 850 ° C., and HTO using SiH 2 Cl 2 (DichloroSilane; DCS) as a source. It is preferable to form either a high temperature oxide film or an HTO film which has a N 2 O gas as a source.
상기 패드층의 제거는 BOE(Buffer oxide Etchant)와 H3PO4용액을 소스로 이용한 산화막/질화막 딥아웃(dip out)을 통해 수행하는 것이 바람직하다.The pad layer may be removed through an oxide / nitride dip out using BOE (Buffer oxide Etchant) and H 3 PO 4 solution as a source.
상기 패드층은 1200~ 1400Å 정도의 두께로 형성하는 것이 바람직하다.The pad layer is preferably formed to a thickness of about 1200 ~ 1400Å.
이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 따라서, 도면에서의 막의 두께 등은 보다 명확한 설명을 강조하기 위해서 과장되어진 것이며, 도면상에서 동일한 부호로 표시된 요소는 동일한 요소를 의미한다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제3의 막이 개재되어질 수도 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the thickness of the film and the like in the drawings are exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings mean the same elements. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.
도 2 내지 도 4는 본 발명의 바람직한 일실시예에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 단면도들이다.2 to 4 are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
도 2를 참조하면, 반도체기판(10)의 소정영역에 사진식각공정을 이용하여 웰을 형성하기 위한 웰형성 이온주입공정과 문턱전압 조절용 이온주입공정을 각각 수행하여, 웰영역(12) 및 문턱전압 조절용 이온이 주입된 영역(14)을 각각 형성한다. 상기 반도체기판(10)은 P형 트랜지스터가 형성되는 PMOS영역과 N형 트랜지스터가 형성되는 NMOS영역으로 구분 정의된다. 상기 PMOS영역의 웰영역을 형성하기 위한 이온주입 도펀트는 비소(As)나 인(P)을 이용하고, NMOS영역의 웰영역을 형성하기 위한 이온주입 도펀트는 보론(B)을 이용한다. 이때, 상기 영역들을 형성하기 위해 수행하는 이온주입공정은 10~ 25 KeV 정도의 에너지대역에서 1E11~ 1E12ion/㎠ 정도의 도즈로 수행할 수 있다.Referring to FIG. 2, the well region 12 and the threshold are respectively formed by performing a well forming ion implantation process for forming a well in a predetermined region of the semiconductor substrate 10 and an ion implantation process for adjusting the threshold voltage. Each of the regions 14 implanted with voltage control ions is formed. The semiconductor substrate 10 is divided into a PMOS region in which a P-type transistor is formed and an NMOS region in which an N-type transistor is formed. The ion implantation dopant for forming the well region of the PMOS region is made of arsenic (As) or phosphorus (P), and the boron (B) is used for the ion implantation dopant for forming the well region of the NMOS region. In this case, the ion implantation process performed to form the regions may be performed at a dose of about 1E11 to 1E12ion / cm 2 in an energy band of about 10 to 25 KeV.
이어서, 상기 결과물 전면 상부에 터널산화막(16) 및 플로팅게이트전극용 제1 폴리실리콘막(18)을 순차적으로 형성한다.Subsequently, the tunnel oxide layer 16 and the first polysilicon layer 18 for the floating gate electrode are sequentially formed on the entire surface of the resultant.
상기 터널산화막(16)은 750~ 800℃ 정도의 온도에서 습식산화를 진행한 후, 900~ 910℃ 정도의 온도와 N2의 기체분위기에서 20~ 30분 동안 열처리하여 70~ 80Å 정도의 두께로 형성할 수 있다.The tunnel oxide film 16 was subjected to wet oxidation at a temperature of about 750 to 800 ° C., and then heat-treated at a temperature of about 900 to 910 ° C. and a gas atmosphere of N 2 for 20 to 30 minutes to a thickness of about 70 to 80 ° C. Can be formed.
상기 플로팅 게이트전극용 제1 폴리실리콘막(18)은 SiH4또는 SiH6와 같은 Si 소스 가스와 PH3가스를 이용한 저압화학기상증착(pressure chemical vapordeposition: LP- CVD)법을 통해 580~ 620℃ 정도의 온도 및 0.1~ 3torr 정도의 압력에서 250~ 500Å 정도의 두께로, 도프드 폴리실리콘막을 형성하고, 이 도프드 폴리실리콘막의 P농도를 1.5E20~ 3.0E20 atoms/cc 정도의 도핑레벨로 형성할 수 있다.The first polysilicon film 18 for the floating gate electrode is 580 to 620 ° C through a pressure chemical vapor deposition (LP-CVD) method using a Si source gas such as SiH 4 or SiH 6 and a PH 3 gas. A doped polysilicon film is formed at a thickness of about 250 to 500 Pa at a temperature of about 0.1 to 3 torr and a P concentration of the doped polysilicon film is formed at a doping level of about 1.5E20 to 3.0E20 atoms / cc. can do.
이어서, 상기 결과물 상에 제1 질화막(20), 제1 산화막(22), 제2 질화막(24), 제2 산화막(26) 및 제3 질화막(28)을 순차적으로 형성한다.Subsequently, the first nitride film 20, the first oxide film 22, the second nitride film 24, the second oxide film 26, and the third nitride film 28 are sequentially formed on the resultant product.
상기 제1 질화막(20), 제2 질화막(24) 및 제3 질화막(28)은 반응기체로서 NH3와 SiH2Cl2가스를 이용하여 1~ 3torr 정도의 압력 및 650~ 800℃ 정도의 온도에서 LP- CVD법으로 형성할 수 있다. 이때 상기 제1 질화막(20) 및 제3 질화막(26)은 250~ 350Å 정도의 두께로 형성할 수 있고, 제2 질화막(24)은 150~ 250Å 정도의 두께로 형성할 수 있다.The first nitride film 20, the second nitride film 24, and the third nitride film 28 are each a pressure of about 1 to 3 torr and a temperature of about 650 to 800 ° C. using NH 3 and SiH 2 Cl 2 gas as a reactor. Can be formed by LP-CVD. In this case, the first nitride film 20 and the third nitride film 26 may be formed to a thickness of about 250 to 350 kPa, and the second nitride film 24 may be formed to a thickness of about 150 to 250 kPa.
제1 산화막(22) 및 제2 산화막(26)은 600~ 700℃ 정도의 온도, 1~ 3torr 정도의 압력 및 810~ 850℃ 정도의 온도에서 LP- CVD법으로, SiH2Cl2(DichloroSilane; DCS)를 소스로 한 HTO(high temperature oxide)막 또는 N2O가스를 소스로 한 HTO막 중 어느 하나로 형성할 수 있다. 이때 제1 산화막(22)은 150~ 250Å 정도의 두께로 형성하고, 제2 산화막(26)은 250~ 350Å 정도의 두께로 형성할 수 있다.The first oxide film 22 and the second oxide film 26 are LP-CVD at a temperature of about 600 to 700 ° C., a pressure of about 1 to 3 tor, and a temperature of about 810 to 850 ° C., by SiH 2 Cl 2 (DichloroSilane; It is possible to form either a high temperature oxide (HTO) film using DCS) or an HTO film using N 2 O gas as a source. At this time, the first oxide film 22 may be formed to a thickness of about 150 to 250 kPa, and the second oxide film 26 may be formed to a thickness of about 250 to 350 kPa.
따라서 상기 5층의 패드층은 1200~ 1400Å정도의 두께로 형성할 수 있다.Therefore, the pad layer of the five layers can be formed to a thickness of about 1200 ~ 1400Å.
도 3를 참조하면, 상기 결과물의 소정영역에 포토레지스트 패턴(미도시)을 형성한 후 이를 식각마스크로 식각공정을 수행하여 소자분리영역을 정의하는 트렌치(T)를 형성한다. 즉, 상기 포토레지스트 패턴(미도시)을 식각마스크로 하부의 제3 질화막, 제2 산화막, 제2 질화막, 제1 산화막, 제1 질화막, 플로팅 게이트전극용 폴리실리콘막 및 터널산화막을 순차적으로 식각하여 트렌치(T)를 형성한다.Referring to FIG. 3, after forming a photoresist pattern (not shown) in a predetermined region of the resultant, an etching process is performed using an etching mask to form a trench T defining an isolation region. That is, the photoresist pattern (not shown) is sequentially etched with the third nitride film, the second oxide film, the second nitride film, the first oxide film, the first nitride film, the polysilicon film for the floating gate electrode, and the tunnel oxide film under the etching mask. To form the trench T.
종래와 같이 포토레지스트 패턴을 식각마스크로 하부의 질화막을 식각하면, 상기 식각공정에 대한 질화막의 특성으로 인해 질화막은 기울기를 가지게 되고, 이 기울기를 가진 질화막 및 상기 포토레지스트 패턴을 식각마스크로 하부의 막질을 식각하여 트렌치를 형성하면 상기 형성된 트렌치는 상기 질화막의 기울기가 그대로 전달되어, 트렌치는 기울기를 가지게 된다. 따라서 본 발명에서 제시한 5층으로 이루어진 패드막 즉, 제3 질화막(20), 제2 산화막(26), 제2 질화막(24), 제1 산화막(22) 및 제1 질화막(20)을 순차적으로 식각하면, 질화막만을 식각하여 형성된 기울기보다 질화막과 산화막을 번갈아가며 식각한 후 형성된 기울기는 작다. 다시 말해, 질화막 사이에 형성된 산화막의 식각공정시 산화막의 막질특성상 산화막은 버티컬한 프로파일을 가지게 되는 데, 이러한 특성을 이용하여 질화막과 산화막의 식각을 번갈아 수행하면, 상기 패드막의 프로파일은 종래의 질화막만의 프로파일보다 작은 기울기 즉, 거의 버티컬한 프로파일을 갖는다. 이와 같이 형성된 작은 기울기를 가진 패드막으로 하부의 폴리실리콘막, 터널산화막을 순차적으로 식각하여 트렌치(T)의 형성을 완료한다. 이이서, 상기 형성된 포토레지스트 패턴을 제거하는 스트립공정을 수행한다.When etching the lower nitride film using the photoresist pattern as an etching mask as in the related art, the nitride film has an inclination due to the characteristics of the nitride film for the etching process, and the nitride film having the inclination and the photoresist pattern as an etching mask When the film is etched to form a trench, the formed trench is transmitted as it is, and the trench has a slope. Therefore, the pad film composed of the five layers of the present invention, that is, the third nitride film 20, the second oxide film 26, the second nitride film 24, the first oxide film 22 and the first nitride film 20 are sequentially formed. In the etching process, the inclination formed after etching the nitride film and the oxide film alternately is smaller than the inclination formed by etching only the nitride film. In other words, during the etching process of the oxide film formed between the nitride films, the oxide film has a vertical profile due to the film quality of the oxide film. When the etching of the nitride film and the oxide film is alternately performed using these properties, the profile of the pad film is a conventional nitride film only. It has a slope smaller than its profile, ie an almost vertical profile. The formation of the trench T is completed by sequentially etching the lower polysilicon film and the tunnel oxide film with a pad film having a small slope formed as described above. Next, a strip process for removing the formed photoresist pattern is performed.
상기 트렌치(T) 내부에 갭필(gap fill)특성이 우수한 HDP(HighDensity plasma)산화막이 채워지도록 증착한 후 제2 산화막(26)의 소정부분이 노출(제3 질화막(28)은 제거되고)될 때까지 화학적 기계적 연마(chemical mechanical polishing: CMP)공정 등의 평탄화공정을 수행하여 소자분리막(30)을 형성한다.After deposition to fill a high density plasma (HDP) oxide film having excellent gap fill characteristics in the trench T, a predetermined portion of the second oxide layer 26 is exposed (the third nitride layer 28 is removed). The device isolation layer 30 is formed by performing a planarization process such as a chemical mechanical polishing (CMP) process.
도 4를 참조하면, 상기 남겨진 제2 산화막(26), 제2 질화막(24), 제1 산화막(22)및 제1 질화막(20)을 식각공정을 통해 제거한다. 이때 수행하는 식각공정은 BOE(Buffer oxide Etchant)와 H3PO4용액을 소스로 이용한 산화막/질화막 딥아웃(dip out)을 통해 수행할 수 있다. 따라서 상기 형성된 제2 산화막(26), 제2 질화막(24), 제1 산화막(22) 및 제1 질화막(20)을 제거하기 위해 상기 산화막/질화막 딥아웃공정을 반복하여 수행한다. 이때 상기 제2 산화막(26), 제2 질화막(24), 제1 산화막(22) 및 제1 질화막(20)의 제거시 상기 소자분리막의 HDP산화막의 식각을 방지하기 위해서는 상기 제1 및 제2 산화막(22, 26)과 HDP 산화막의 식각비가 2.5배 이상이 되도록 한다. 따라서 상기 패드막의 제거공정으로 인해 EFH(effective Field Height)의 형성을 방해하는 것을 방지할 수 있다.Referring to FIG. 4, the remaining second oxide layer 26, the second nitride layer 24, the first oxide layer 22, and the first nitride layer 20 are removed through an etching process. The etching process may be performed through oxide / nitride dip out using BOE (Buffer oxide Etchant) and H 3 PO 4 solution as a source. Therefore, in order to remove the formed second oxide layer 26, the second nitride layer 24, the first oxide layer 22, and the first nitride layer 20, the oxide / nitride layer dipout process is repeatedly performed. In this case, when the second oxide layer 26, the second nitride layer 24, the first oxide layer 22, and the first nitride layer 20 are removed, the first and second layers may be etched to prevent etching of the HDP oxide layer of the device isolation layer. The etching ratio of the oxide films 22 and 26 and the HDP oxide film is 2.5 times or more. Therefore, it is possible to prevent the formation of the effective field height (EFH) due to the removal process of the pad film.
이어서 상기 결과물 전면에 플로팅게이트전극용 제2 폴리실리콘막(32)을 형성하고 그 상부의 소정영역에 포토레지스트 패턴(미도시)을 형성한 후 이를 식각마스크로 제2 폴리실리콘막(32)에 식각공정을 수행하여 플로팅게이트전극의 형성을 완료한다. 상기 버티컬한 프로파일을 갖는 패드막으로 인해 상기 제2 폴리실리콘막(32) 식각공정시 소자분리막의 측벽에 제2 폴리실리콘막이 잔존할 가능성이 낮아지게 된다.Subsequently, a second polysilicon layer 32 for floating gate electrodes is formed on the entire surface of the resultant, and a photoresist pattern (not shown) is formed in a predetermined region thereon, and then the second polysilicon layer 32 is formed as an etching mask. The etching process is performed to complete the formation of the floating gate electrode. Due to the pad film having the vertical profile, the possibility of the second polysilicon film remaining on the sidewall of the device isolation layer during the etching process of the second polysilicon film 32 is reduced.
상기 결과물상에 유전체막, 콘트롤게이트전극 및 금속실리사이드막등을 형성하여 플래시메모리소자의 형성을 완료한다.A dielectric film, a control gate electrode and a metal silicide film are formed on the resultant to complete the formation of the flash memory device.
본 발명에 의하면, 5층 패드막의 형성을 통해 버티컬한 식각마스크를 형성한 후 이를 통해 트렌치를 형성함으로써, 기울기가 큰 소자분리막의 형성을 방지할 수 있도록 하여 EFH(effective Field Height)를 만족한다.According to the present invention, a vertical etching mask is formed through the formation of a 5-layer pad film, and then a trench is formed therethrough, thereby preventing the formation of a device insulator film having a large inclination, thereby satisfying the effective field height (EFH).
이상에서 살펴본 바와 같이 본 발명에 의하면, 5층 패드막의 형성을 통해 버티컬한 식각마스크를 형성한 후 이를 통해 트렌치를 형성함으로써, 기울기가 큰 소자분리막의 형성을 방지할 수 있도록 하여 EFH(effective Field Height)를 만족하는 효과가 있다.As described above, according to the present invention, a vertical etching mask is formed through the formation of a 5-layer pad film, and then a trench is formed therethrough, thereby preventing the formation of a device insulator film having a large slope, thereby preventing effective field height. ) Is effective.
본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.
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