KR20050000447A - liquid crystal display devices - Google Patents

Abstract

PURPOSE: An LCD(Liquid Crystal Display) is provided to form a seal pattern and a black matrix such that the seal pattern is not superposed on the black matrix without increasing the width of an upper case or the width of a bezel, to thereby improve substrate utilization efficiency and reduce the volume of the LCD. CONSTITUTION: An LCD(101) includes a lower substrate(110) having an active region(A2) and a non-display region(NA2), a metal layer(147) formed in the non-display region of the lower substrate, and an upper substrate(150) on which red, green and blue color filters(154) are formed. The LCD further includes a black matrix(152a,152b) formed on the upper substrate, a seal pattern(172) surrounding the black matrix, an upper case(182) covering the edge of the upper substrate, and a lower case(184) located on the back side of the lower substrate. The black matrix surrounds the active region.

Description

Liquid crystal display devices

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a metal layer for preventing light leakage in a non-display area.

Recently, with the rapid development of the information society, the need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption has emerged. Among these, liquid crystal display devices have a resolution. It is excellent in color display and image quality, and is actively applied to notebooks and desktop monitors.

In general, a liquid crystal display device includes two substrates on which electrodes are formed, such that the surfaces on which the two electrodes are formed face each other, inject liquid crystal between the two substrates, and then apply an electric voltage to electrodes on the two substrates. By moving the liquid crystal molecules by means of the device to express the image by the transmittance of light that varies accordingly.

The structure of a general liquid crystal display is briefly shown in FIG. 1.

As shown, the liquid crystal display device 1 includes a lower array substrate 10 and an upper color filter substrate 50, the array substrate 10 having a larger area than the color filter substrate 50. . A black matrix 52 and a seal pattern 72 are formed on the black matrix 52 at the edge between the two substrates 10 and 50, and liquid crystal is injected between the two substrates 10 and 50 although not shown. It is. The active area A1 located inside the black matrix 52 of the edge is a portion where a screen is displayed, and a plurality of gate lines 12 and data lines 21 intersect to define pixels (not shown). A thin film transistor (not shown) is formed at a portion where the gate wiring 11 and the data wiring 21 cross each other. Next, pad portions GPA and DPA and gates connected to the gate lines 12 and the data lines 21 to form gates and data pads 36 and 40 on the left and upper outer edges of the array substrate 10, respectively. And link portions GRA and DRA connected to the data pads 36 and 40, the gate lines 12, and the data lines 21, and the pad portions GPA and DPA are external circuits. And a data driving circuit. Areas other than the active area A1, that is, the pad parts GPA and DPA and the link parts GRA and DRA, form the non-display area NA1. Although not shown, a backlight unit is provided below the array substrate 10 of the liquid crystal display device 1, and a lower case is provided below the backlight unit, and is connected to the lower case to provide a color filter substrate 50. The upper case is partially overlapped with the edge black matrix 52.

2 is a cross-sectional view of a portion of the active area and the non-display area of FIG. 1 taken along line A-A.

As shown in FIG. 2, the liquid crystal display device 1 includes an active area A1 where a screen is displayed and a gate and data pad 36 connected to a driving circuit for applying a signal to the active area A1. Gate and data pad portion (GPA, not shown), the link portion for connecting the pad 36 (not shown) and the gate and data lines 11 (not shown) of the active region A1. It is divided into a non-display area NA1 including a black matrix 52b area BA1 covering a GRA (not shown).

In the active region A1, the lower array substrate 10 has a gate electrode 13 made of a conductive material such as a metal on the transparent substrate 11, and a silicon nitride (SiN _x ) or a silicon oxide (SiN) formed thereon. The gate insulating film 16 made of SiO ₂ covers the gate electrode 13. An active layer 18 made of amorphous silicon is formed on the gate insulating layer 16 on the gate electrode 13, and ohmic contact layers 20a and 20b made of amorphous silicon doped with impurities are formed thereon. .

Source and drain electrodes 22 and 24 made of a conductive material such as a metal are formed on the ohmic contact layers 20a and 20b, and the source and drain electrodes 22 and 24 are formed together with the gate electrode 13. The transistor T is formed.

In the drawing, although the cut surface appears to be disconnected due to different cutoffs, the gate electrode 13 is connected to the gate wiring 12, and the source electrode 22 is connected to the data wiring (not shown).

Subsequently, a passivation layer 30 made of silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) is formed on the source and drain electrodes 22 and 24, and the passivation layer 30 exposes the drain electrode 24. It has a contact hole 32.

A pixel electrode 34 made of a transparent conductive material is formed in a pixel region (a region defined by the intersection of the gate wiring and the data wiring) on the passivation layer 30, and the pixel electrode 34 is a contact hole 32. It is connected to the drain electrode 24 through.

In the non-display area NA1 of the array substrate 10, a gate pad 36 and a data pad (not shown) connected to the gate line 12 and the data line (not shown) are formed.

Meanwhile, the color filter substrate 50 spaced apart from the array substrate 10 at a predetermined interval is disposed on the array substrate 10. The color filter substrate 50 has a black matrix 52a formed at a position corresponding to the thin film transistor T on the inner surface of the transparent substrate 51. Also, in the non-display area NA1, the gate line link unit GRA and the data line link unit (not shown) connected to the gate and the data pad 36 (not shown) may be covered and disposed at the edge of the active area A1. The black matrix 52b is formed. A color filter 54 is formed under the black matrix 52a in the active area A1. The color filter 54 is sequentially repeated with red, green, and blue, and one color is one pixel. Corresponds to the area. A common electrode (not shown) made of an overcoat layer 56 and a transparent conductive material is formed under the color filter 54.

The liquid crystal is injected between the two substrates 10 and 50 to form the liquid crystal layer 70.

Here, the gate insulating layer 16 and the protective layer 30 on the array substrate 10 extend to the non-display area NA1, and the array substrate 10 and the color filter substrate 50 in the non-display area NA1. A gap is formed between the liquid crystal injection gaps and a seal pattern 72 is formed to prevent leakage of the injected liquid crystals. The seal pattern 72 is formed by dispensing or screening a thermosetting resin in a predetermined pattern on the array substrate 10 and then facing the array substrate 10. The color filter substrate 50 is disposed and pressure cured to bond the two substrates 10 and 50 together.

Next, a backlight unit 80 that generates light is formed under the array substrate 10, and covers a part of an edge of the upper color filter substrate 50, and covers the upper and lower portions of the array substrate 10 to cover the lower backlight unit 80. Cases 82 and 84 are provided to form the exterior of the liquid crystal display device 1.

Cases 82 and 84 that form the exterior of the liquid crystal display device 1, in particular, the upper case 82 have a predetermined width WOT1, and are formed in a black matrix 52b formed at an edge of the upper case and the active area A1. ) Has a series of relations in the role of light leakage prevention. Hereinafter, the upper case 82 and the black matrix 52b and the seal pattern 72 formed below will be described.

Light emitted from the backlight unit 80 formed under the array substrate 10 of the liquid crystal display 1 includes the gate pad link unit and the data pad link unit GRA, including the active area A1 where the screen is driven. Also pass through the liquid crystal display device 1 to the upper side. Therefore, in order to prevent light leakage in the non-display area NA1 of the liquid crystal display device 1, the black matrix 52b is formed at a portion corresponding to the edge of the active area A1 of the color filter substrate 50. In particular, in the case of the liquid crystal display 1 used as a notebook computer, the width of the edge of the substrate, that is, the non-display area NA1 is shortened in the active area A1 where a screen is displayed by applying a narrow bezel. Is formed. As a result, a seal pattern 72 for bonding to the array substrate 10 is formed under the black matrix 52b at the edge of the active region A1 of the color filter substrate 50.

At this time, the sealant (sealant) which is a material for forming the seal pattern 72 will be described in more detail. The seal pattern 72 forms a gap for injecting the liquid crystal, prevents leakage of the injected liquid crystal, and provides moisture into the liquid crystal cell. And it serves to prevent intrusion of external air. Typically, epoxy resin is used and glass fiber or spacer is incorporated to control the cell gap. The required properties of these sealants should be reliable, low cure shrinkage, dimensional stability, high purity and non-pollution. And it is divided into thermosetting hardened by heat and ultraviolet curable resin hardened by ultraviolet. The sealant is also generally white in color.

The sealant forming the seal pattern 72 described above is correlated with the black matrix 52b. In the liquid crystal display device 1, a seal pattern 72 is formed to bond the array substrate 10 and the color filter substrate 50 together. For this reason, the seal pattern 72 is formed at the edge of the active area A1 and the active area A1 and is formed under the black matrix 52b area BA1 surrounding the active area A1. When some of the black matrix 52b, for example, the resin black matrix is used, the bonding pattern between the resin black matrix 52b and the substrate 50 is poor, so that the seal pattern A popping phenomenon of 72 occurs.

Referring to FIG. 3 (the same as FIG. 2 and only a part thereof is modified, the same code is used, only the code of the changed part is changed, and the description of the same part is omitted). Referring to FIG. When the black matrix 52b width BA1 formed at the edge, that is, the link portion GRA (not shown), is reduced, the upper case 82 and the black matrix 52b do not overlap with each other of the upper case 82. Light leakage occurs in an area between one end of the black matrix 52b. In order to prevent this, the width of the upper case 82 WOT1 or the width of the bezel must be increased, which is a problem in manufacturing a compact liquid crystal display device 1, and also the utilization efficiency of the substrate. Will be reduced.

The present invention has been made to solve the above-described conventional problems, the object of the present invention is to prevent the defect such as seal burst by forming the seal pattern and the black matrix so as not to overlap without increasing the width of the upper case or bezel. In addition, the substrate utilization efficiency is increased and a compact liquid crystal display device is provided.

1 is a plan view of a conventional general liquid crystal display device.

2 is a cross-sectional view taken along the line A-A of FIG.

3 is a cross-sectional view of a liquid crystal display device having a reduced black matrix width and an increased upper case width in a conventional non-display area.

4A and 4B are cross-sectional views of the liquid crystal display according to the exemplary embodiment of the present invention taken along the lines A-A and B-B of FIG. 1.

5A and 5B are cross-sectional views of the liquid crystal display according to the exemplary embodiment of the present invention taken along lines C-C and D-D of FIG. 1.

6 is a plan view of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

7a to 7c are sectional views of the manufacturing process according to E-E of FIG.

8a to 8c are sectional views of the manufacturing process according to F-F of FIG. 6;

9a to 9c are sectional views of the manufacturing process according to G-G of FIG.

<Description of Symbols for Major Parts of Drawings>

101 liquid crystal display device 110 array substrate

111, 151: transparent substrate 112: gate wiring

113: gate electrode 116: gate insulating film

118: active layer 120a, 120b: ohmic contact layer

122: source electrode 124: drain electrode

130: protective layer 132: drain contact hole

134: pixel electrode 136: gate pad

138: gate pad contact hole 147: second metal layer

150: color filter substrate 152a, 152b: black matrix

154: color filter layer 156: overcoat layer

170: liquid crystal layer 172: seal pattern

180: backlight unit 182, 184: upper and lower cases

A2: active area BA2: non-display area black matrix width

GPA: Gate Pad Section GRA: Gate Wiring Link Section

NA2: non-display area T: thin film transistor

WOT2: Upper Case Width WS: Seal Pattern Width

In order to achieve the above object, a liquid crystal display according to the present invention has an active region, a non-display region of a pad portion and a link portion, and a plurality of gate lines and data lines intersect to define pixels, and the thin film transistor includes A lower substrate formed; A metal layer formed in the non-display area of the lower substrate; An upper substrate on which red, green, and blue color filters are formed; A black matrix formed on an inner surface of the upper substrate and formed on an edge of an active region; A seal pattern formed outside the black matrix; An upper case formed covering an edge of the upper substrate; It includes a lower case formed on the lower substrate.

In this case, the metal layer is formed of a first metal layer formed in the data wiring link portion of the non-display area and a second metal layer formed in the gate wiring link portion, and the first metal layer formed in the data wiring link portion is a metal forming a gate wiring. The second metal layer is formed of a material, and the second metal layer formed on the gate wiring link part is formed of a metal material constituting the data wiring.

In addition, the first metal layer or the second metal layer is formed to overlap the upper case and the black matrix.

The black matrix is formed of a resin.

In addition, a backlight unit is further included between the lower substrate and the lower case.

A method of manufacturing an array substrate of a liquid crystal display according to the present invention includes the steps of defining a pad portion and a link portion, which are an active region and a non-display region, composed of pixels on a transparent substrate; Forming a first metal layer on the substrate on which the active region and the non-display region are defined, the gate wiring including the gate electrode and the data wiring link portion spaced apart from the active region by a predetermined distance; Forming a gate insulating film over the gate wiring and the first metal layer; Depositing amorphous silicon for each pixel on the gate insulating film to form an active layer; Forming an ohmic contact layer by doping impurities on the active layer; Forming a source and a drain electrode on the ohmic contact layer, and simultaneously forming a second metal layer on the data line and the gate wiring link portion at a predetermined distance from the active region on the gate insulating layer; Forming a protective layer over the data line and the second metal layer; Forming a contact hole in the protective layer, the contact hole exposing one end of the drain electrode, the gate wiring, and the data wiring; And depositing a transparent conductive material on the passivation layer to form a pixel electrode in contact with the drain electrode and a gate pad and a data pad in contact with one end of each line.

In this case, the first metal layer is formed of the same metal material as the gate wiring, and the second metal layer is formed of the same metal material as the data wiring.

Hereinafter, the structure of the liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

Since the top view of the liquid crystal display according to the embodiment of the present invention is the same as the conventional one, a conventional drawing (Fig. 1) is used, and Figs. Fig. 4B and Fig. 5B are cross-sectional views cut along the BB and DD (cutting the pad and link main surfaces in the non-display area).

As illustrated, the liquid crystal display device 101 according to the exemplary embodiment of the present invention is formed so that the color filter substrate 150, which is the upper substrate, is opposite to each other and corresponds to the array substrate 110, which is the lower substrate. The backlight unit 180 is provided under the 110, overlaps a part of the edge of the color filter substrate 150, and has an upper case 182 formed thereon, and is connected to the upper case 182. A lower case 184 is formed to surround 180.

In addition, the liquid crystal display 101 includes an area where the pads 136 and 140 connected to the driving circuits are positioned to apply a signal to the active area A2 and the active area A2 where the screen is displayed. A non-display area including a black matrix 152b area BM2 that covers the link parts GRA and DRA for connecting the gates 136 and 140 and the gates and data lines 112 and 121 of the active area A2 to each other. NA2).

The gate electrode 113 is formed on the transparent substrate 111 in the lower array substrate 110 in the active region A2, and the gate insulating layer 116 covers the gate electrode 113 thereon. An active layer 118 made of amorphous silicon and ohmic contact layers 120a and 120b made of amorphous silicon doped with impurities are sequentially formed on the gate insulating layer 116 on the gate electrode 113. In addition, source and drain electrodes 122 and 124 are formed on the ohmic contact layers 120a and 120b, and the source and drain electrodes 122 and 124 form the thin film transistor T together with the gate electrode 113. Doing. In this case, the gate electrode 113 is connected to the gate wiring 112, the source electrode 122 is connected to the data wiring 121, and the gate wiring 113 and the data wiring 121 are orthogonal to each other. Define.

Subsequently, a passivation layer 130 is formed on the source and drain electrodes 122 and 124, and the passivation layer 130 has a contact hole 132 exposing the drain electrode 122.

A pixel electrode 134 made of a transparent conductive material is formed in the pixel area above the passivation layer 130, and the pixel electrode 134 is connected to the drain electrode 124 through the contact hole 132.

The color filter substrate 150, which is an upper substrate spaced apart from the array substrate 110 at a predetermined interval, is disposed on the array substrate 110. In the color filter substrate 150, a black matrix 152a is formed on an inner surface of the transparent substrate 151 (the surface opposite to the array substrate) and is formed in a region corresponding to the thin film transistor T. The black matrix 152b covers the gate and data lines 112 and 121 of the NA2 and the link parts GRA and DRA connected to the gate and data pads 136 and 140 and corresponds to the edge area of the active area A2. ) Is formed. The color filter 154 is formed under the black matrix 152a in the active area A2. The color filter 154 is sequentially repeated with red, green, and blue, and one color is one pixel. Corresponds to the area. A common electrode (not shown) made of an overcoat layer 156 and a transparent conductive material is formed under the color filter 154.

The liquid crystal is injected between the two substrates 110 and 150 to form the liquid crystal layer 170.

Here, the gate insulating layer 116 and the protective layer 130 on the array substrate 110 extend to the non-display area NA2, and the array substrate 110 and the color filter substrate 150 in the non-display area NA2. A gap between the liquid crystal injection is formed therebetween, and a seal pattern 172 is formed to prevent leakage of the injected liquid crystal. In this case, the seal pattern 172 does not overlap with the black matrix 152b formed at the edge of the upper active region A2 and is formed outside the black matrix 152b. In addition, one end of the upper case 182 is located between one end of the seal pattern 172 and one end of the edge black matrix 152b. At this time, the liquid crystal panel (the form in which the array substrate and the color filter substrate are bonded by the seal pattern), in particular, the width WOT2 of the upper case 182 formed to cover a part of the edge of the color filter substrate 150 so that the liquid crystal panel does not move. Since it serves as a fixing, it is formed to cover and fix a part of the edge of the color filter substrate 150 to the minimum, including pads (GPA, DPA) of the array substrate 110. Therefore, the upper gate overlaps with the seal pattern 172 formed on the edge of the liquid crystal panel or is formed inside the inner end of the seal pattern 172.

Briefly describing the black matrix 152b formed at the edge of the active area A2, the width BA2 of the black matrix 152b is at least a seal pattern compared to the width BA1 of the conventional black matrix 52b of FIG. 2. It is formed by reducing the width (WS) of. That is, since a large number of seal burst defects occur due to the black matrix (52b of FIG. 2) existing at the position where the seal pattern (72 of FIG. 2) is formed, it is one of the objects of the present invention to solve the problem of the black matrix 152b. It is formed by reducing the width BA2.

4A and 4B, a gate formed on the gate line 112 on the entire surface of the gate link portion GRA connected to the gate line 112 of the active area A2 and the gate pad 136 of the non-display area NA2. A second metal layer 147 formed of the same material as the source and drain electrodes 122 and 124 is formed on the insulating layer 116. The second metal layer 147 blocks a part of the light emitted from the backlight unit 180 in place of the black matrix 152b of the active region A2 of the upper color filter substrate 150. . In the gate link portion GRA of FIG. 4A, light from the lower backlight is blocked by the gate wiring 112, but in plan view, only an insulating film and a protective layer exist between the gate wiring 112 and the wiring. The light from the bottom passes through the top. Therefore, the second metal layer 147 is formed on the gate line 112 with the gate insulating layer 116 interposed therebetween to block a part of light emitted from the bottom. At this time, in the gate pad link portion GRA in which the second metal layer 147 is not formed, light from the lower portion is blocked by the upper black matrix 152b formed partially overlapping with the second metal layer 147. .

Next, referring to FIGS. 5A and 5B, the gate electrode and the lower portion of the data line 121 of the data link unit DRA connected to the data line 121 of the active area A2 and the data line 121 of the non-display area NA2 may be used. The first metal layer 145 is formed of the same material. A gate insulating layer 116 is formed between the first metal layer 145 and the data line 121. Like the second metal layer, the first metal layer 145 blocks light emitted from the lower backlight unit 180 in place of a part of the black matrix 152b.

Accordingly, the leakage of light from the link portions GRA and DRA between the inner end of the seal pattern 172 and the outer end of the black matrix 152b of the edge of the active area A2 is performed on the array substrate 110. The metal layers 145 and 147 were formed to prevent the upper case 182 without extending the width WOT2.

In addition, since the seal pattern 172 and the black matrix 152b do not overlap each other, the seal burst phenomenon due to the black matrix 152b peeling is prevented.

Next, the manufacturing method of the array substrate of the liquid crystal display device which concerns on this invention is demonstrated with reference to drawings.

6 is a plan view of an array substrate according to an embodiment of the present invention.

As illustrated, the array substrate 110 is formed of an active area A2 on which a screen is displayed, pad parts GPA and DPA and link parts GRA and DRA, which are non-display areas. The gate line 112 extending in the horizontal direction and the data line 121 extending in the vertical direction intersect to define the pixel region P, and the thin film transistor T as a switching element is formed at the intersection. First and second blocking light may be applied to the gate link unit GRA connecting the gate line 112 and the gate pad 136 and the data link unit DRA connecting the data line 121 and the data pad 140. 2 metal layers 145 and 147 are formed. The first and second metal layers 145 and 147 may be formed on different layers although not shown in the drawing.

7A through 7F are cross-sectional views taken along the line E-E of the switching element in the pixel in the active region, and FIGS. 8A through 8F and 9A through 9F are cross-sectional views taken along the lines F-F and G-G, respectively.

As shown in FIGS. 7A, 8A, and 9A, a gate electrode 113 may be formed by depositing one selected from a metal material such as aluminum (Al), aluminum alloy (AlNd), or copper on a transparent substrate 111. The gate wiring 112 is formed. At this time, molybdenum (Mo) may be further deposited to form the gate electrode 113 and the gate wiring 112 in a double layer. At the same time, the first metal layer 145 is formed on the entire surface of the data link unit DRA in the data link unit DRA. In this case, the first metal layer 145 is not connected to the gate line and is formed to be sufficiently spaced apart so as not to cause signal interference with each other. Subsequently, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the gate electrode 113, the gate wiring 112, and the first metal layer 145 formed on the data ring portion DRA. The gate insulating film 116 is formed.

Next, as shown in FIGS. 7B, 8B, and 9B, amorphous silicon is deposited and patterned on the gate insulating layer 116, and subsequently doped by ion implantation to form an ohmic contact layer on the amorphous silicon layer 118. To form 120a and 120b. Subsequently, a metal material such as chromium is deposited to form the source and drain electrodes 122 and 124 and the data line 121 on the ohmic contact layers 120a and 120b, and the gate line (in the gate link portion GRA). 111, a second metal layer 147 is formed. In this case, the second metal layer 147 is formed to be sufficiently spaced apart from the data line (not shown) positioned at the outermost portion of the active area in contact with the gate link part GRA so as to prevent signal interference. In the gate wiring link part GRA, the second metal layer 147 and the extended gate wiring 112 are electrically insulated because a gate insulating film 116 is formed therebetween.

Next, as illustrated in FIGS. 7C, 8C, and 9C, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is deposited on the entire surface of the substrate on which the source and drain electrodes 122 and 124 are formed. The protective layer 130 is formed and patterned to form a drain contact hole 132, a gate pad contact hole 138, and a data pad contact hole 142, respectively. Thereafter, one of the transparent conductive materials, indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the entire surface of the substrate 111 to contact the drain electrode 124 for each pixel. And a gate pad 136 and a data pad 140.

In the liquid crystal display using the array substrate formed as described above, light is not emitted to the upper color filter substrate because a metal layer is formed in the gate link portion and the data link portion to block the light emitted from the backlight unit. At this time, the light emitted to a portion spaced apart by a predetermined interval to avoid signal interference between the gate wiring and the data wiring of the active region is covered by the black matrix formed on the edge of the active region below the color filter substrate.

The liquid crystal display according to the present invention has the effect of blocking unnecessary light from the lower backlight unit without increasing the upper case width by forming a metal layer on the non-display area of the lower array substrate so as to overlap the upper case and the black matrix, respectively. .

In addition, in the seal pattern overlapping with the black matrix, the black matrix width of the active region is reduced to form the outer side of the black matrix, thereby preventing the seal burst phenomenon due to black mattress contact failure.

Claims (10)

A lower substrate having an active region, a non-display region of the pad portion, and a link portion, wherein a plurality of gate lines and data lines cross each other to define a pixel, wherein the pixel includes a lower substrate; A metal layer formed in the non-display area of the lower substrate; An upper substrate on which red, green, and blue color filters are formed; A black matrix formed on an inner surface of the upper substrate and formed on an edge of an active region; A seal pattern formed outside the black matrix; An upper case formed covering an edge of the upper substrate; A lower case formed under the lower substrate Liquid crystal display comprising a. The method of claim 1, And the metal layer comprises a first metal layer formed on the data line link portion of the non-display area and a second metal layer formed on the gate line link portion. The method of claim 2, And a first metal layer formed on the data line link part is formed of a metal material constituting a gate line. The method of claim 2, And a second metal layer formed on the gate wiring link part is formed of a metal material constituting a data wiring. The method according to any one of claims 3 to 4, The first metal layer or the second metal layer overlaps with the upper case and the black matrix. The method of claim 1, The black matrix is formed of a resin. The method of claim 1, And a backlight unit between the lower substrate and the lower case. Defining a pad portion and a link portion, which are an active region and a non-display region, of pixels on a transparent substrate; Forming a first metal layer on the substrate on which the active region and the non-display region are defined, the gate wiring including the gate electrode and the data wiring link portion spaced apart from the active region by a predetermined distance; Forming a gate insulating film over the gate wiring and the first metal layer; Depositing amorphous silicon for each pixel on the gate insulating film to form an active layer; Forming an ohmic contact layer by doping impurities on the active layer; Forming a source and a drain electrode on the ohmic contact layer, and simultaneously forming a second metal layer on the data line and the gate wiring link portion at a predetermined distance from the active region on the gate insulating layer; Forming a protective layer over the data line and the second metal layer; Forming a contact hole in the protective layer, the contact hole exposing one end of the drain electrode, the gate line, and the data line; Depositing a transparent conductive material on the passivation layer to form a pixel electrode in contact with the drain electrode and a gate pad and a data pad in contact with one end of each wire; Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 8, The first metal layer is formed of the same metal material as the gate wiring. The method of claim 8, And wherein the second metal layer is formed of the same metal material as that of the data line.