KR200435514Y1 - Multiplexed circuit emulation ATM interface module - Google Patents

Abstract

The present invention is an ATM circuit emulation device for connecting a military tactical circuit electronic switch to an ATM network, and the trunk of a military tactic circuit switch with a special transmission rate is 2: 2 at a standardized E1 transmission rate (2.048 Mbps). The present invention relates to an ATM circuit emulation matching device which provides not only channelization but channelized circuit emulation function by using the link efficiency and the existing AAL1 SAR commercial chipset.

That is, the plurality of line interface units 100 matching the circuit switch and the plurality of transmission frame converters 200 which converts the trunk transmission frame of 1.024 Mbps from the circuit switch to the E1 standard transmission frame of 2.048 Mbps. A commercial chipset 300 consisting of a commercial chipset for disassembly and assembly into ATM cells, ATM layer processing unit 400, ATM network, which is in charge of various ATM layer functions such as ATM traffic processing and OEM processing. The AMT physical layer processing unit 500, which is responsible for matching and ATM physical layer processing functions, and the processor unit 600 for controlling all the above configurations.

ATM switch, interface unit, transmission frame conversion unit, commercial chipset unit, layer processing unit

Description

Multiplexed circuit emulation ATM interface module

1 is a block diagram of a conventional ATM line matching device.

2 is a block diagram of an ATM circuit emulation matching device showing an embodiment of the present invention.

3, 4 and 5 are timing diagrams between a line interface unit and a transmission frame conversion unit or between a transmission frame conversion unit and a commercially available set section showing a preferred embodiment of the present invention.

FIG. 6 is a diagram illustrating an embodiment of a transmission frame processing unit in the transmission frame conversion unit of FIG. 2. FIG.

FIG. 7 is a diagram illustrating an embodiment of a reception frame processing unit in the transmission frame conversion unit of FIG. 2. FIG.

8 is a timing diagram illustrating an exemplary embodiment of FIG. 6.

9 is a timing diagram illustrating an exemplary embodiment of FIG. 7.

              Explanation of the main symbols used in the main part of the drawing

100: line interchange unit 200: transmission frame conversion unit

211 and 231: comparators 212 and 232: register section

213, 233, 241, 261: FIFO section 221, 251: clock synthesizing section

222 and 252: timing generator 223: FS generator

224, 242, 262: MUX section 253: M_FS generating section

300: commercial chipset unit 400: ATM layer processing unit

500: ATM physical layer processing unit 600: processor unit

The present invention relates to a circuit multiplexing ATM matching device, and more particularly, multiplexed ATM circuit emulation for matching a military tactical rotary electronic exchanger (hereinafter, abbreviated as "line exchanger") to ATM network. Circuit emulation device uses the link efficiency and the standard commercial chipset (AAL1 SAR) as it is by changing the frame of a circuit switch having a special transmission rate to the AT switch in a 2: 1 interframe change to a standardized E1 data rate (2.048 Mbps). The present invention relates to a multiplexed ATM circuit emulation matching device having a channelized circuit emulation function as well as a physical layer matching function capable of directly accessing an ATM network.

In general, when attempting to match a military tactics circuit switch to an ATM network, the military tactics circuit switch uses a non-standardized transmission rate and frame structure according to the group's specificity, so that a separate channel emulation function is implemented. Existing commercial chipsets are required to be implemented, which requires considerable cost and development ability for ASICs.

Therefore, the conventional circuit-switching matching device has developed only a non-channelization function of matching a trunk of a 1.024 MHz group circuit switch physically to a commercial chipset of a commercial T1 / E1 radar.

That is, as shown in Fig. 1, the line interface unit 10, which is a part that is matched with the circuit switch, the commercial chipset unit 20 for disassembling and assembling into AMT cells, the traffic processing and the main function of the AT layers. AMT layer processing unit 30 that handles advanced network operation, management, and maintenance (AM) functions, AMT physical layer 40 that performs a matching function and a traffic buffer function with the switch fabric unit, and appropriately control them. It is composed of a processor unit 50 for.

Here, as shown in FIG. 3, since 1.024 Mbps of line data is transmitted to the commercial chip set unit 20 -PM73122 / PM73123: PMC-SIERRA-, the commercial chip set unit designed with a frame structure of the existing E1 or T1 bit rate ( In 20), each channel cannot be processed, and the entire link is processed by ATM cells in a single unchannelized form of 1.024 Mbps.

Therefore, even though the link efficiency is reduced by half by matching 1.024Mbps link to commercial chipset chips supporting 2.048Mbps, the related companies are not providing proper solutions.

Accordingly, the present invention is designed to solve the above-mentioned conventional technical problems, and through a 2: 1 mutual frame conversion of a trunk of a circuit switch having a special transmission rate to an AT switch with a standardized E1 transmission rate (2.048 Mbps). It can provide not only channel efficiency but also channelization circuit emulation function by using the existing commercial chipset as it is, and it can be directly matched to ATM network by forming a module form to satisfy ATM standard UNI 3.1 / 4.0 function. An object of the present invention is to provide an ATM line emulation matching device.

The present invention for achieving the above object, the transmission frame between the line interface unit and the commercial chipset unit in order to solve the conventional problems that could not provide functions such as link efficiency degradation and channelized line emulation of commercialized chipset With the conversion unit, the trunk data of the 1.024Mbps circuit switch input to the ATM connection device is converted into a ratio of 2: 1 2.048Mbps E1 frame and matched to the commercial chipset unit.

In addition, by converting one E frame into two 1.024 Mbps group line frames from a commercial chipset and matching them, it is possible not only to increase link efficiency of the commercial chipset but also to provide various functions such as channelization line emulation provided by the commercial chipset. This is a technical task.

Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention according to the spirit as follows.

As shown in FIG. 2, a plurality of transmission frames for performing a 2: 1 conversion between a plurality of line interface units 100 matching a circuit switch and a 1.024 Mbps trunk transmission frame of the circuit switch to an E1 standard transmission frame of 2.048 Mbps. Transformation unit 200, commercial chipset 300 consisting of a commercial chipset for disassembly and assembly into the ATM cell, ATM layer processing unit 400 responsible for various ATM layer functions such as ATM traffic processing and OAM processing ), The AMT physical layer processing unit 500 responsible for matching with the AMT network and the AMT physical layer processing function, and the processor unit 600 for controlling all the above configurations.

Herein, a format showing data of a serial link input and output to the transmission frame converter 200 is shown in FIG. 4, and a timing diagram is shown in FIG. 5.

The transmission frame converter 200 is input from the line interface unit 100 as shown in FIG. 6 to transmit 1: 2 frame and rate conversion from the transmission frame converter 200 to the commercial chipset 300. As a block diagram showing the function of the transmission frame processing unit, it can be seen that the configuration is largely composed of a link 0 matching unit, a link 1 matching unit and a common unit.

That is, the common unit selects a clock of any good quality from two input 1.024 MHz clocks, and performs a clock synthesis unit 221 for clock synthesis at twice the 2,048 MHz clock, and controls to generate various control signals in the transmission frame processing unit. The timing generator 222 and the FS generator 223 which stores the E1 frame alignment data and is controlled by the control timing generator 222 to generate the frame alignment data of E1, and the link 0 and the frame alignment data. And a MUX unit 224 that provides a time multiprocessing function with a link 1 and a time multiprocessing function with link 1 and frame alignment data.

The link0 matcher and the link1 matcher store the framing sync signal 15-bit " 000011100100100 " of the circuit switch, and have comparators 211 and 231 having a function of comparing the shift register data in parallel, and a 15-bit capacity. And serial data input from each link according to the timing signals generated by the shift register units 212 and 232 and the control timing generator 222, which sequentially input serial data according to the input club and output them in parallel. Are stored in order, and are respectively composed of FIFO units 213 and 233 which are output in accordance with the control signal of the control timing generating unit 222.

In addition, as shown in FIG. 7, the frame conversion unit 200 outputs the data from the commercial chipset unit 300 and transmits the block to the line interface unit 100 through a 1: 2 frame and a rate conversion. This figure also comprises a link 0 matching section, a link 1 matching section and a common section.

The common unit includes a clock synthesizing unit 251 for synthesizing a line matching reference clock of 1.024 MHz through an input E1 clock of 2.048 MHz, a timing control unit 252 for controlling timing of the entire receiving frame converter, and a timing control unit 252. M_FS generation unit 253 which generates 15 bits of circuit-switched frame alignment data under the control of the "

The link0 matching unit and the link1 matching unit respectively input the E1 frame alignment data under the control of the timing control unit 252, and control the respective FIFO units under the control of the timing control unit 252. And MUX units 242 and 262 for time multiplexing the serial data output from the 241 and 261 and the frame alignment data signal output from the M_FS generating unit 253, respectively.

Here, the operation of the transmission frame conversion unit in the transmission frame conversion unit 200 is performed by serial data (S6-2) (S6-7) of link 0 and link 1 input from the line interface unit 100 as shown in the timing diagram shown in FIG. Is input to the respective shift registers 212 in accordance with the clocks S6-1 and S6-7, and the pattern and the 15-bit frame alignment data signal " 000011100100100 " of the circuit-switch stored in the comparator 211 for each clock. When a match is made and a match is made, a signal S2-3 or S6-8 is generated to inform the control timing generator 222 of the pattern match.

When the (S6-3) or (S6-8) signal is generated, the control timing generator 222 generates (S6-4) or (S6-9), which is a FIFO write signal, to the FIFO unit 213 to generate the FIFO unit. Serial data (S6-5) and (S6-10) are stored in (213) and (233), respectively.

In addition, the clock synthesizing unit 221 selects a high-quality 1.024 MHz (S6-20) from the 1.02 MHz signals from the two line interfaces, and sends it to the reference clock of the control timing generation unit 222 and simultaneously synthesizes twice. The 2.048 MHz clock S6-11 is also sent to the control timing generator 222 and the commercial chipset 300 to be used as the E1 reference clock.

As a result, as shown in the timing diagram of FIG. 8, the control timing generator 222 matches the reference 2.048 MHz clock S6-11 when both of the pattern matching signals S6-3 and S6-8 occur. Simultaneously with the generation of the E1 frame alignment data signal S6-12, the signal S6-13 is sent to the FS generating unit 223 to generate the M_FS signal 15-bit " Si00110011100100 " (S6-14) of the E1 frame alignment data signal. Let's do it.

In this case, the Si bit is used as a bit for distinguishing the first frame "O" from the second frame "1" among the E1 frame alignment data bytes.

The control timing generator 222 alternately generates the FIFO read signals S6-15 and S6-17 to the FIFO units 213 and 233, and is stored in the FIFO units 213 and 233. Read each serial data.

In the MUX unit 224, the serial data S6-16 and S6-18 and the frame alignment data S6-14 output from the FIFO units 213 and 233 are each subjected to time multiplexing (S6-19). Create and send the E1 frame data of the time, and the data multi-processed (S6-19) is sent to the commercial chipset 300 as TX DATA

In addition, the operation of the reception frame processing unit in the transmission frame conversion unit 200 is performed by the commercially available chipset unit 300 (S7-1) and E1 frame serial data (S7-) as shown in the timing diagram of FIG. 9. 2) When receiving the E1 frame sync signal S7-3, the timing controller 252 checks the first bit of the E1 frame alignment data signal 0 when the E1 frame alignment data signal S7-3 occurs. Is generated, the M_FS generation unit 253 generates a signal (S7-8) to generate the frame alignment data signals 15 bits (S7-9) and (S7-13), respectively.

The timing controller 252 generates the FIFO write signals of (S7-4) and (S7-6) and stores serial data of (S7-5) (S7-7) in the FIFO units 241 and 261, respectively. A FIFO read signal (S7-10) (S7-14) is generated in the FIFO section 241 (261) to output serial data (S7-11) and (S7-15) from the FIFO.

Each MUX unit 242, 262 performs time multiplexing on the circuit-switched frame alignment data signals S7-9, S7-11, and 7-15, respectively, and the final signals S7-13 and (S7-17) is output.

As described in detail above, the circuit multiplexing ATM matching device of the present invention has a transmission frame conversion unit between a line interface unit and a commercial chipset unit, and transmits trunk data of a 1.024Mbps circuit switch to a 2.01Mbps as an ATM connection device. By converting the ratio of E1 frame type, it is possible to utilize 100% of E1 link of commercial chipset and to provide various functions such as channelized circuit emulation provided by existing commercial chipset. The circuit electronic switch can be efficiently matched to ATM network, and the expectation is very large.

Claims (4)

An AMT line emulation matching device comprising: A plurality of line interface units 100 that match the group circuit switch; A plurality of transmission frame converters for converting a trunk transmission frame of 1.024 Mbps of the group circuit switch into an E1 standard transmission frame of 2.048 Mbps; A commercial chipset unit 300 comprising a commercial chipset for disassembling and assembling into an AT cell; An AT layer processing unit 400 that is responsible for various AT layer functions such as AT traffic processing and OEM processing; An AMT physical layer processing unit 500 which is responsible for matching with AMT network and ATM physical layer processing function; Multiplexed circuit emulation ATM matching device characterized in that it comprises a processor 600 for controlling all of the configuration. The method of claim 1; The transmission frame converter 200 includes a transmission frame processor for performing a 1: 2 frame and a rate conversion on a frame input from the line interface unit 100; Multiplexed circuit emulation ATM matching device comprising a receiving frame converter for performing a 1: 2 frame and a rate conversion for the frame output to the commercial chipset 300. The method of claim 2; The transmission frame processor selects a clock of any good quality from two input clocks of 1.024 MHz, generates a clock synthesizer 221 for clock synthesis using a double clock of 2,048 MHz, and generates various control signals in the transmission frame processor. The control timing generation unit 222 and the FS generation unit 223 which stores the E1 frame alignment data and generates frame alignment data of E1 under the control of the control timing generation unit 222. The MUX unit 224, which provides the time multiprocessing function with data and the time multiprocessing function with link 1 and frame alignment data, stores the framing sync signal 15-bit " 000011100100100 " Comparator 211 (231) having the function of comparing with a 15-bit capacity, and serially input the serial data according to the input club in order to output in parallel Stores serial data input from each link in order according to the timing signals generated by the shift registers 212 and 232 and the control timing generator 222, and the control signal of the control timing generator 222. Multiplexed line emulation AMT matching device, characterized in that each consisting of FIFO unit (213) (233) for outputting according to. The method of claim 2; The receiving frame converter may include a clock synthesizer 251 for synthesizing a line matching reference clock of 1.024 MHz through an E1 clock of 2.048 MHz input, a timing controller 252 for controlling timing of the entire received frame converter, and a timing controller ( The M_FS generation unit 253 which generates 15 bits of circuit-switch frame alignment data under the control of the control unit 252, the FIFO units 241 and 261 that are input under the control of the timing control unit 252, and the control of the timing control unit 252. And MUX units 242 and 262 for time multiplexing the serial data output from the respective FIFO units 241 and 261 and the frame alignment data signals output from the M_FS generation unit 253, respectively. A multiplexed circuit emulation ATM matching device.

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