KR20040106198A - Memory device capable of reducing package pin number and information process system including the same - Google Patents

Abstract

PURPOSE: A memory device capable of reducing the number of package pins and an information processing system including the same are provided to reduce the number of the multi-chip package or the system in package by changing the packet data transmitted in response to the activation of the chip selection signal. CONSTITUTION: A memory device capable of reducing the number of package pins includes a plurality of packet pins, a synchronization memory(1300) and a packet controller(1200). The synchronization memory and the packet controller operate with synchronizing to each clock signal. The packet controller receives each of the packet data through the packet pins with synchronizing to the clock signal when the packet enable signal is activated and converts the inputted packet data into the address and the control signals. And, the synchronization memory receives the address and the control signals with synchronizing to the clock signal.

Description

MEMORY DEVICE CAPABLE OF REDUCING PACKAGE PIN NUMBER AND INFORMATION PROCESS SYSTEM INCLUDING THE SAME}

The present invention relates to a data processing system, and more particularly to a data processing system using a packet method.

Mobile applications such as personal digital assistants, third-generation mobile phones, digital still cameras, etc., require miniaturization and diversification. This demand has long been addressed by the miniaturization of semiconductor processes. However, the effect of miniaturization is difficult to be obtained due to the development period and the increase in the cost of the process technology. Therefore, in order to obtain the effect of miniaturization, MCP (Multi-Chip Package) technology is employed in mobile applications. MCP is a multi-chip product that has several different memory chips (for example, NOR flash, NAND flash, SRAM, UtRAM, etc.) in one package, and is almost the same as the memory commonly used by using advanced package technology. Can be prepared at a level. When using MCP, the internal mounting area can be reduced by more than 50% and the wiring can be simplified, compared to the case of using a single unit of portable devices, which can greatly reduce cost and productivity. Furthermore, in order to achieve the effect of miniaturization, SIP (System In Package) technology is employed in mobile applications. SIP refers to a product in which not only a memory product but also a non-memory product is mounted in one package, and a plurality of required chips are stacked (stacked) and connected in three dimensions. Stacking can not only reduce the mounting area, but also shorten the development period, reduce the cost, and speed up the operation.

However, in the case of SIP products as well as MCP products, there are many pins because they contain a large number of chips, which is a obstacle in configuring the system. In addition, the memory device also has many pins (address pins, data pins, control pins, etc.), which is a barrier to constructing a memory system employed in mobile applications.

The present invention provides a memory device capable of reducing the number of external pins and an information processing system including the same.

1 is a block diagram showing an information processing system according to a first embodiment of the present invention;

2 is a block diagram showing the packet controller of FIG. 1 in accordance with a preferred embodiment of the present invention;

3 is a timing diagram showing output signals of the control logic shown in FIG. 2;

4A-4E are circuit diagrams showing the series-parallel registers of FIG. 3 in accordance with a preferred embodiment of the present invention;

5 shows a packet data configuration according to the first embodiment of the present invention;

6 is a block diagram showing the synchronous memory of FIG. 1 in accordance with a preferred embodiment of the present invention;

7 is a timing diagram for explaining the operation of the packet controller and the synchronous memory according to the present invention;

8 is a block diagram showing an information processing system according to a second embodiment of the present invention;

9 is a block diagram showing the packet controller of FIG. 8 in accordance with a preferred embodiment of the present invention;

10 and 11 show packet data configurations according to a second embodiment of the present invention;

12 is a timing diagram for explaining an auto refresh operation according to the second embodiment of the present invention; And

13 is a block diagram showing an information processing system according to a third embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: information processing system 110: memory controller

120: packet controller 130: synchronous memory

121: control logic 122-126: register

According to a feature of the present invention for achieving the above object, a memory device comprises a plurality of packet pins; And a synchronous memory and a packet controller, each of which operates in synchronization with a clock signal. When a packet enable signal is activated, the packet controller receives packet data through the packet pins in synchronization with the clock signal, and converts the input packet data into address and control signals; The synchronous memory receives the address and control signals in synchronization with the clock signal. The synchronous memory performs a burst operation in synchronization with the clock signal, and the synchronous memory and the packet controller are mounted in one package. The package is either a multi-chip package or a system in package.

In this embodiment, any one of the packet pins is used to accept packet data related to the command. The packet data is a serial combination of the control signals. Alternatively, the packet data is a serial combination of data bits for defining the command. The packet enable signal is a chip select signal.

According to another feature of the invention, the memory device comprises a first pin for receiving a chip select signal; Second pins receiving clock signals; Third pins each receiving packet data; A memory operating in synchronization with the clock signals; And a packet controller operating in synchronization with the clock signals. When the chip select signal is activated, the packet controller receives packet data through the packet pins in synchronization with the clock signal, and converts the input packet data into address and control signals; The synchronous memory receives the address and control signals in synchronization with the clock signal.

In this embodiment, one of the third pins is used to receive packet data for defining a command, and the other is used to receive packet data indicating an address.

In this embodiment, each of the third pins is used to receive packet data mixed with data bits and address signals for defining a command.

In this embodiment, the memory device comprises: fourth pins for inputting and outputting data signals; A fifth pin receiving a clock enable signal; A sixth pin receiving a data strobe signal; And a seventh pin receiving a data masking signal, wherein the data strobe signal, the data mask signal, the data signals, and the clock enable signal are directly transmitted to the synchronous memory.

In this embodiment, any one of the third pins is used to accept packet data related to the command. The packet data related to the command is a serial combination of the control signals or a serial combination of data bits for defining the command. The synchronous memory is a double data rate synchronous DRAM (DDR SDRAM).

According to still another aspect of the present invention, an information processing system includes: a synchronous memory device operative to be synchronized with a clock signal; A memory controller generating the clock signal and outputting packet data; And a packet controller which operates in synchronization with the clock signal and converts the packet data into address and control signals so as to conform to the communication protocol of the synchronous memory device. The packet controller is mounted in one package.

According to still another aspect of the present invention, an information processing system includes a memory controller for generating a clock signal and a chip select signal and outputting a plurality of data packets; Control logic that operates in response to activation of a chip select signal and generates a plurality of pulse signals synchronized with the clock signal; A plurality of registers respectively corresponding to the data packets, each register sequentially latching data bits of the corresponding data packet in response to the pulse signals and simultaneously outputting the latched data bits; A signal generator for generating control signals in response to data bits output from any one of the registers; And a synchronous memory device which operates in synchronization with the clock signal and receives control signals output from the signal generator as commands and data bits output from the remaining registers as addresses.

The information processing system or memory system according to the present invention includes a memory and is configured such that address and control signals (especially control signals for indicating a command) to be applied to the memory are transmitted in the form of a packet. By sending address and control signals in the form of packets, it is possible to reduce the pin count of a package containing memory. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing an information processing system (or memory system) according to a first embodiment of the present invention. Referring to FIG. 1, an information processing system 100 according to the present invention includes a memory controller 110, a packet controller 120 as an interface device, and a synchronous memory. 130). In the first embodiment of the present invention, the synchronous memory 130 is a double data rate synchronous DRAM (hereinafter referred to as "DDR-SDRAM"), and the synchronous memory 130 is connected thereto. Not limited to those who have acquired common knowledge in this field. In the information processing system (or memory system) 100 according to the present invention, the packet controller 120 and the synchronous memory 130 are configured to constitute a multi-chip package (MCP) or a system-in-package (SIP). Mounted on the package. Furthermore, it will be apparent to those who have acquired the general knowledge in this field that the packet controller 120 and the synchronous memory 130 can be configured as a System On a Chip (SOC). The packet controller 120 and the synchronous memory 130 operate in synchronization with the clock signals CK and / CK output from the memory controller 110. In particular, the synchronous memory 130 operates as the clock signals CK, / CK) to perform a burst operation. The memory controller 110 outputs address and command signals to be provided to the synchronous memory 130 in the form of a packet, and the packet controller 120 is adapted to the communication protocol of the synchronous memory 130. Converts packet data provided from 110 into address and control (or command) signals. More specifically, it is as follows.

The memory controller 110 converts address and command signals into a packet form. For example, the address and command signals are applied in parallel to the synchronous memory 130, while the memory controller 110 converts the address and command signals in series and converts the converted data into " packet data " Or data packet). Packet data (PACKET0 [m: 0] -PACKETn [m: 0]) is delivered to packet controller 120 for a predetermined cycle of clock signal CK (two cycles in this embodiment). For example, each packet data is 4-bit data, which is transmitted from the memory controller 110 to the packet controller 120 by one bit every half cycle of the clock signal CK. The packet controller 120 operates in synchronization with the clock signals CK and / CK from the memory controller 110 and is a packet input in response to the control signals / CS and CKE from the memory controller 110. Convert data to suit the communication protocol of synchronous memory 130. The packet controller 120 starts to accept packet data from the memory controller 110 when the control signal / CS is activated. That is, activation of the control signal / CS as the chip select signal is used as a packet enable signal indicating that packet data is transmitted.

The packet controller 120 converts m-bit serial data having mixed address and command signals into m-bit parallel data. While the address and command signals are sent in packet form, the data is sent as-is without modification. That is, when writing data to the synchronous memory 130, the packet controller 120 bypasses the data DQ [15: 0] from the memory controller 110 to the synchronous memory 130. When reading data from the synchronous memory 130, the packet controller 120 bypasses the data DQ [15: 0] from the synchronous memory 130 to the memory controller 110. As a result, data to be written to / read from / from the synchronous memory 130 is transferred directly between the memory controller 110 and the synchronous memory 130. The synchronous memory 130 operates in synchronization with the clock signals CK and / CK, and performs a read / write operation in response to address and control (or command) signals output from the packet controller 120.

As described above, the packet controller 120 and the synchronous memory 130 are mounted in one package, and the synchronous memory 130, that is, DDR-SDRAM, inputs addresses, commands, and data in a conventional manner. Receive. In other words, the DDR-SDRAM 130 has the same pin configuration. If the packet controller 120 is not used, the SIP or MCP including the synchronous memory 130 must provide all the pins needed for the synchronous memory 130. On the other hand, when transmitting the address and command signals required for the synchronous memory 130 in the form of packets from the memory controller 110 to the packet controller 120, the SIP or MCP including the synchronous memory 130 is a synchronous memory It requires fewer pins than are needed for 130.

In a preferred embodiment of the present invention, the packet controller 120 and the DDR-SDRAM 130 are formed on one substrate, and because of the low pin count and low power consumption, L ² RAM (Low pin and Low power RAM). Thus, the L ² RAM according to the present invention is suitable for adoption in mobile applications.

FIG. 2 is a block diagram showing the packet controller 120 of FIG. 1 in accordance with a preferred embodiment of the present invention, and FIG. 3 is a timing diagram showing the output signals of the control logic 121 shown in FIG. The embodiment of the packet controller 120 has been implemented assuming that the packet data number n is 5 and each packet data is 4-bit data. However, it will be apparent to those skilled in the art that the number of packet data and the number of bits of the packet data may be variously changed depending on the memory system (or information processing system) to which the packet data is applied.

Referring to FIG. 2, a packet controller 120 according to a preferred embodiment of the present invention includes control logic 121 and five serial-to-parallel registers 122, 123, 124, 125, 126). The control logic 121 receives the clock signals CK and / CK and the control signals / CS and CKE provided from the memory controller 110 and controls the input / output operation of the registers 122-126. To generate pulse signals (PCLK1-PCLK4, PCLKD). For example, as shown in FIG. 3, the control logic 121 is a pulse signal synchronized to the rising edges of the clock signal CK at T1-T4 time points in response to the activation of the chip select signal / CS. (PCLK1-PCLK4) occur sequentially. In addition, the control logic 121 generates the pulse signal PCLKD synchronized with the pulse signal PCLK4 within the period in which the pulse signal PCLK4 is generated. In other words, after the chip select signal / CS is activated, the packet data is effectively input to the packet controller 120, and therefore the chip select signal / CS is used as a signal indicating the start of transmission of the packet data.

Referring back to FIG. 2, each of the registers 122-126 operates in response to the pulse signals PCLK1-PCLK4, PCLKD from the control logic 121, and corresponds to the corresponding packet data PACKET0 [3: 0]. -PACKET4 [3: 0]) is input respectively. Packet data (PACKET0 [3: 0] -PACKET4 [3: 0]) is 4-bit serial data, which is converted into parallel data through corresponding registers. The converted data bits are simultaneously delivered to the synchronous memory 130 as addresses ADDR [13: 0], BA [1: 0] and control signals (/ RAS, / CAS, / WE, DM). The synchronous memory 130 performs a burst operation in response to address and control signals output from the packet controller 120 in parallel at the same time.

4A-4E are circuit diagrams showing the series-parallel registers 122-126 of FIG. 3 in accordance with a preferred embodiment of the present invention.

Referring first to FIG. 4A, the series-parallel register 122 includes a plurality of switches SW1-SW8, a plurality of latches LAT1-LAT8, a plurality of MOS transistors M1-M8, and inverters ( INV7, INV13, INV20, and INV24), and are connected as shown in the figure. Each switch consists of a transfer gate and an inverter, and each latch consists of two inverters. The latches LAT1-LAT8 are initialized high or low via corresponding MOS transistors, respectively, when the control signal VCCH is activated low. The control signal VCCH is a power-on reset signal, which is generated by a well-known power-on detection circuit (not shown).

Assume that 4-bit packet data (PACKET0 [3: 0]) consists of "/ RAS, / CAS, / WE, DM". However, it is obvious to those who have learned the general knowledge in this field that 4-bit packet data (PACKET0 [3: 0]) is not limited to "/ RAS, / CAS, / WE, DM". For example, the 4-bit packet data (PACKET0 [3: 0]) may be composed of "/ RAS, / CAS, / WE, CS" (CS means an internal chip select signal). According to the above assumption, first, when the pulse signal PCLK1 is activated high, the packet data PACKET0 [0] of "/ RAS" is latched to the latch LAT1 through the switch SW1. When the pulse signal PCLK2 is activated high, the packet data PACKET0 [1], which is " / CAS " is latched to the latch LAT3 via the switch SW3. When the pulse signal PCLK3 is activated high, the packet data PACKET0 [2] which is " / WE " is latched to the latch LAT5 via the switch SW5. When the pulse signal PCLK4 is activated high, the packet data PACKET0 [3] which is "DM" is latched to the latch LAT7 via the switch SW7. As shown in FIG. 3, when the pulse signal PCLKD is activated within the period T3-T4 where the pulse signal PCLK4 is activated, the contents of the latches LAT1, LAT3, LAT5, and LAT7 correspond to each other. The switches SW2, SW4, SW6, and SW8 are transferred to the latches LAT2, LAT4, LAT6, and LAT8, respectively. As a result, the register 122 receives 4-bit serial packet data PACKET0 [3: 0] in synchronization with the pulse signals PCLK1-PCLK4, and control signals (/) in synchronization with the pulse signal PCLKD. RAS, / CAS, / WE, DM) at the same time (or in parallel).

The registers 123-126 shown in FIGS. 4B-4E are substantially the same as those shown in FIG. 4A except that the initialization values of the latches are different, and a description thereof is therefore omitted.

5 is a diagram illustrating a packet data configuration according to a preferred embodiment of the present invention. In this embodiment, the packet data is 4-bit serial data. First, in the T1 interval, the first data bits (/ RAS, BA0, BA1, A0, A1) of each packet data are respectively latched in the registers 122-126 when the pulse signal PCLK1 is activated. In the T2 interval, the second data bits (/ CAS, A2, A3, A4, A5) of each packet data are latched in the registers 122-126 respectively when the pulse signal PCLK2 is activated. In the T3 period, the third data bits (/ WE, A6, A7, A8, A9) of each packet data are latched in the registers 122-126 respectively when the pulse signal PCLK3 is activated. In the T4 interval, the fourth data bits DM, A10, A11, A12, A13 of each packet data are latched in the registers 122-126, respectively, when the pulse signal PCLK4 is activated.

6 is a block diagram illustrating the synchronous memory 130 of FIG. 1 in accordance with a preferred embodiment of the present invention. Although the synchronous memory 130 according to the present invention is constructed using DDR-SDRAM, it is apparent to those who have acquired common knowledge in the art that the synchronous memory 130 of the present invention is not limited thereto. The synchronous memory 130 according to the present invention operates in synchronization with the clock signals CK and / CK provided from the memory controller 110. In other words, the read / write operation of the synchronous memory 130 is performed in synchronization with the clock signals CK and / CK. As shown in FIG. 6, clock signals CK and / CK from the memory controller 110 include a timing register 201, an address register 202, a data strobe generation circuit 213, a data output buffer circuit ( 214, and data input register circuit 216.

Although the address and command signals are provided to the packet controller 120 in the form of packets at the memory controller 110, the synchronous memory 130 provides the address and command signals provided by the packet controller 120 in a conventional SDRAM communication protocol. It works normally depending on the field. That is, basically, the synchronous memory 130 operates identically to the well-known DDR-SDRAM in this field, and a description thereof will therefore be omitted. In particular, the synchronous memory 130 according to the present invention performs a burst operation (or an operation of increasing a column address internally) in synchronization with the clock signals CK and / CK, as described above. The internal operating frequency, which is a reference for burst operation of the DDR-SDRAM, is the same as the frequency of the clock signal CK provided from the memory controller 110.

7 is a timing diagram illustrating the operation of the packet controller 120 and the synchronous memory 130 according to the present invention. As is well known, an active command is given to the SDRAM with a row address to read data, and after a predetermined time a read command is given to the SDRAM with a column address. In this embodiment, the operation of the packet controller 120 using the read operation will be described. However, in the case of a write operation, the operation of the packet controller 120 is performed in the same manner as that of the read operation, and a description thereof will be omitted here.

To read data from synchronous memory 130, first, memory controller 110 includes an active command and a row address along with clock signals CK and / CK and control signals CKE and / CS. Outputs the bit serial packet data (PACKET0 [3: 0], PACKET1 [3: 0], PACKET2 [3: 0], PACKET3 [3: 0], PACKET4 [3: 0]) to the packet controller 120. . The control logic 121 of the packet controller 120 controls the pulse signals PCLK1-PCLK4 and PCLKD in response to the control signals / CS and CKE and the clock signals CK and / CK from the memory controller 110. ) Occurs sequentially. The registers 122-126 of the packet controller 120 correspond to the corresponding packet data PACKET0 [3: 0], PACKET1 [3: 0], PACKET2 [3: 0] in response to the pulse signals PCLK1-PCLK4. , PACKET3 [3: 0], PACKET4 [3: 0]) sequentially latches four data bits. The data bits so latched are output simultaneously when the pulse signal PCLKD is activated. That is, the data bits converted in parallel are transferred to the synchronous memory 130 as addresses ADDR [12: 0], BA [1: 0] and control signals (/ RAS, / CAS, / WE, DM). do. Each of the registers 122-126 accepts data bits input at the high edge and the low edge of the clock signal CK of the 1st / 2nd cycle, respectively, and the input data bits are simultaneously input to the synchronous memory 130. Delivered. Synchronous memory 130 receives active command and row address signals in a third cycle.

Then, the memory controller 110, together with the clock signals (CK, / CK) and control signals (CKE, / CS), the 4-bit serial packet data (PACKET0 [3 :) including a read command and a column address. 0], PACKET1 [3: 0], PACKET2 [3: 0], PACKET3 [3: 0], PACKET4 [3: 0]) are output to the packet controller 120. The control logic 121 of the packet controller 120 controls the pulse signals PCLK1-PCLK4 and PCLKD in response to the control signals / CS and CKE and the clock signals CK and / CK from the memory controller 110. ) Occurs sequentially. The registers 122-126 of the packet controller 120 correspond to the corresponding packet data PACKET0 [3: 0], PACKET1 [3: 0], PACKET2 [3: 0] in response to the pulse signals PCLK1-PCLK4. , PACKET3 [3: 0], PACKET4 [3: 0]) sequentially latches four data bits. The data bits so latched are output simultaneously when the pulse signal PCLKD is activated. That is, the data bits converted in parallel are transferred to the synchronous memory 130 as column address and control signals (/ RAS, / CAS, / WE, DM). Each of the registers 122-126 accepts data bits input at the high edge and the low edge of the clock signal CK of the third and fourth cycles, respectively, and the input data bits are simultaneously input to the synchronous memory 130. Delivered. Synchronous memory 130 accepts a read command and a column address in the fifth cycle. The data read operation will then be performed according to well known methods.

8 is a block diagram showing an information processing system (or memory system) according to a second embodiment of the present invention.

Referring to FIG. 8, an information processing system 1000 according to the present invention includes a memory controller 1100, a packet controller 1200, and a synchronous memory 1300. In the second embodiment of the present invention, the synchronous memory 1300 is a DDR-SDRAM, and it is apparent to those who have acquired common knowledge in this field that the synchronous memory 1300 is not limited thereto. In the information processing system (or memory system) 1000 according to the present invention, the packet controller 1200 and the synchronous memory 1300 are configured to constitute a multi-chip package (MCP) or a system-in-package (SIP). Mounted on the package. Furthermore, it will be apparent to those who have acquired the general knowledge in this field that the packet controller 1200 and the synchronous memory 1300 may be configured as a System On a Chip (SOC).

The packet controller 1200 and the synchronous memory 1300 operate in synchronization with the clock signals CK and / CK output from the memory controller 1100. In particular, the synchronous memory 1300 may operate in response to the clock signals CK, / CK) to perform a burst operation. The memory controller 1100 outputs packet data as addresses and command signals to be provided to the synchronous memory 1300, and the packet controller 1200 transmits the packet data provided from the memory controller 1100 to the synchronous memory 1300. Convert to address and control (or command) signals. In this embodiment, the data strobe signal DS and the data masking signal DM are transmitted from the memory controller 1100 directly to the synchronous memory 1300 without passing through the packet controller 1200. Similarly, the data DQi is also transmitted directly from the memory controller 1100 to the synchronous memory 1300 and from the synchronous memory 1300 to the memory controller 1100 without passing through the packet controller 1200.

The memory controller 1100 converts address and command signals into a packet form. For example, address and command signals are applied in parallel to synchronous memory 1300, while memory controller 1100 converts address and command signals in series, and so converted data is referred to as " packet data " It is called. Packet data (PACKET0 [m: 0] -PACKETn [m: 0]) is delivered to the packet controller 1200 for a predetermined cycle (in this embodiment, two cycles) of the clock signal CK. For example, each packet data is 4-bit data, which is transmitted from the memory controller 1100 to the packet controller 1200 by one bit every half period of the clock signal CK. The packet controller 1200 operates in synchronization with the clock signals CK and / CK from the memory controller 1100 and is a packet input in response to the control signals / CS and CKE from the memory controller 1100. Convert data to suit the communication protocol of synchronous memory 1300. The packet controller 1200 starts to accept packet data from the memory controller 1100 when the control signal / CS is activated. The packet controller 1200 inputs and converts packet data in the same manner as shown in FIG. 1.

In comparison with the packet controller 120 shown in FIG. 1, the packet controller 1200 shown in FIG. 8 is configured to include packet data (eg, PACKET0 [m: 0]) including data bits for defining an instruction. Receives and generates control signals (/ RAS, / CAS, / WE, TCS). That is, the packet data PACKET9 [m: 0] is not a serial combination of control signals (/ RAS, / CAS, / WE, / CS), but a serial combination of data bits representing each command. Generate control signals (/ RAS, / CAS, / WE, TCS), which will be described in detail below.

As described above, the packet controller 1200 and the synchronous memory 1300 are mounted in one package, and the synchronous memory 1300, that is, the DDR-SDRAM, inputs addresses, commands, and data in a conventional manner. Receive. In other words, the DDR-SDRAM 1300 has the same pin configuration. If the packet controller 1200 is not used, the SIP or MCP including the synchronous memory 1300 should provide all the pins needed for the synchronous memory 1300. On the other hand, when transmitting the address and command signals required for the synchronous memory 1300 in the form of a packet from the memory controller 1100 to the packet controller 1200, the SIP or MCP including the synchronous memory 1300 is a synchronous memory It requires fewer pins than are needed for 1300.

Like the first embodiment, the packet controller 1200 and the DDR-SDRAM 1300 are formed on one substrate and are referred to as L ² RAM because they have a low pin count and attain low power consumption. Thus, the L ² RAM according to the present invention is suitable for mobile applications.

9 is a block diagram illustrating the packet controller 1200 of FIG. 8 in accordance with a preferred embodiment of the present invention. 9, a packet controller 1200 according to a preferred embodiment of the present invention includes a control logic 1210, five serial-parallel registers 1220, 1230, 1240, 1250, 1260, and a signal generator 1270. ). Control logic 1210 and registers 1220-1260 are substantially the same as shown in FIG. 2, and a description thereof is therefore omitted.

The memory controller 1100 according to the second embodiment of the present invention transmits 4-bit command data through the packet data pins PACKET0 [3: 0]. For example, the memory controller 1100 transmits packet data "PACKET0 [3: 0]" of "1000" to the packet controller 1200 as an active command. The packet controller 1200 converts the packet data "PACKET0 [3: 0]" of 1000 transmitted serially into parallel packet data RC3-RC0, and the signal generator 1270 converts the parallel packet data RC3-RC0. ) Generates control signals (/ RAS, / CAS, / WE, TCS) as active commands. The memory controller 1100 transmits the packet data "PACKET0 [3: 0]" of "0001" to the packet controller 1200 as a read command. The packet controller 1200 converts serially transmitted packet data (PACKET0 [3: 0]) of "0001" into parallel packet data (CC3-CC0), and the signal generator 1270 converts the parallel packet data (CC3-CC0). ) Generates control signals (/ RAS, / CAS, / WE, TCS) as a read command.

Packet data pins PACKET0-PACKET4 are used to transmit row packets and column packets, and a diagram showing the configuration of each packet is shown in FIG. 10. In this embodiment, the packet data is 4-bit serial data. First, in the first interval T1 of the row packet, the first data bits RC0, BA0, BA1, RA0, RA1 of each packet data are registered in the registers 1220-1260 when the pulse signal PCLK1 is activated. Each latched within. In the second transmission period T2, the second data bits RC1, RA2, RA3, RA4, RA5 of each packet data are respectively latched in the registers 1220-1260 when the pulse signal PCLK2 is activated. . In the third transmission period T3, the third data bits RC2, RA6, RA7, RA8, RA9 of each packet data are respectively latched in the registers 1220-1260 when the pulse signal PCLK3 is activated. . In the fourth transmission period T4, the fourth data bits RC3, RA10 / AP, RA11, RA12, RA13 of each packet data are respectively stored in the registers 1220-1260 when the pulse signal PCLK4 is activated. Latched. According to the second embodiment of the present invention, unlike the first embodiment, the values RC0-RC3 latched in the register 1220 are transmitted to the signal generator 1270, and the signal generator 1270 is assigned to each command (active). Command, precharge command, auto precharge command, mode register setting command, etc.) and generate control signals (/ RAS, / CAS, / WE, TCS). The column packet is transmitted in the same manner as the row packet described above, and the description thereof will therefore be omitted.

The registers 1220-1260 shown in FIG. 9 are configured substantially the same as those shown in FIGS. 4A to 4E, and a description thereof will therefore be omitted. Similarly, the synchronous memory 1300 according to the second embodiment of the present invention is configured substantially the same as that shown in Fig. 6, and a description thereof will therefore be omitted.

FIG. 11 is a diagram for describing a row command packet and a column command packet. Referring to FIG. 11, the row packet data RC3-RC0 of "1000" indicates an active command, and the row packet data RC3-RC0 of "0100" indicates a precharge command. The row packet data RC3-RC0 of "0010" represents an auto refresh command, and the row packet data RC3-RC0 of "0110" represents a mode register setting command. Similarly, column packet data CC3-CC0 of "0001" represents a read command, and column packet data CC3-CC0 of "1001" represents a write command. Instead of a serial combination of control signals, it is possible to represent various commands by sending packet data PACKET0 as a data combination for specifying each command.

The operation of the information processing system (or memory system) according to the second embodiment of the present invention will be described in detail below on the basis of the reference drawings.

To read data from synchronous memory 1300, first, memory controller 1100 includes an active command and row address along with clock signals CK, / CK and control signals CKE, / CS. Outputs bit serial packet data (PACKET0 [3: 0], PACKET1 [3: 0], PACKET2 [3: 0], PACKET3 [3: 0], PACKET4 [3: 0]) to the packet controller 1200. . The control logic 1210 of the packet controller 1200 may output pulse signals PCLK1-PCLK4 and PCLKD in response to the control signals / CS and CKE and the clock signals CK and / CK from the memory controller 1100. ) Occurs sequentially. The registers 1220-1260 of the packet controller 1200 correspond to the packet data PACKET0 [3: 0], PACKET1 [3: 0], and PACKET2 [3: 0] in response to the pulse signals PCLK1-PCLK4. , PACKET3 [3: 0], PACKET4 [3: 0]) sequentially latches four data bits. The data bits so latched are output simultaneously when the pulse signal PCLKD is activated. At the same time, the signal generator 1270 generates control signals / RAS, / CAS, / WE, TCS in response to the data bits RC0-RC3 output from the register 1220, and the control signals ( / RAS, / CAS, / WE, TCS) are transferred to the synchronous memory 1300. In addition, the data bits translated in parallel through the registers 1230-1260 are transferred to the synchronous memory 130 as addresses ADDR [13: 0], BA [1: 0]. That is, each of the registers 1220-1260 receives data bits input at the high edge and the low edge of the clock signal CK of the 1st / 2nd cycle, respectively, so that the input data bits are simultaneously synchronized with the synchronous memory 1300. Is delivered. The synchronous memory 1300 receives active command and row address signals in a third cycle.

Then, the memory controller 1100 includes 4-bit serial packet data PACKET0 [3: containing a read command and a column address together with the clock signals CK and / CK and the control signals CKE and / CS. 0], PACKET1 [3: 0], PACKET2 [3: 0], PACKET3 [3: 0], PACKET4 [3: 0]) are output to the packet controller 1200. The control logic 1210 of the packet controller 1200 may output pulse signals PCLK1-PCLK4 and PCLKD in response to the control signals / CS and CKE and the clock signals CK and / CK from the memory controller 1100. ) Occurs sequentially. The registers 1220-1260 of the packet controller 1200 correspond to corresponding packet data (PACKET0 [3: 0], PACKET1 [3: 0], PACKET2 [3: 0] in response to the pulse signals PCLK1-PCLK4. , PACKET3 [3: 0], PACKET4 [3: 0]) sequentially latches four data bits. The data bits so latched are output simultaneously when the pulse signal PCLKD is activated. At the same time, the signal generator 1270 generates control signals / RAS, / CAS, / WE, TCS in response to the data bits RC0-RC3 output from the register 1220, and the control signals ( / RAS, / CAS, / WE, TCS) are transferred to the synchronous memory 1300. In addition, the data bits translated in parallel through the registers 1230-1260 are transferred to the synchronous memory 130 as addresses ADDR [13: 0], BA [1: 0]. That is, each of the registers 1220-1260 receives data bits input at the high edge and the low edge of the clock signal CK of the third and fourth cycles, respectively, and the input data bits are simultaneously synchronized to the synchronous memory 1300. Is delivered. The synchronous memory 1300 receives a read command and a column address in the fifth cycle. The data read operation will then be performed according to well known methods.

In the information processing system according to the embodiments of the present invention, in the case of the auto refresh operation, as shown in FIG. 12, the memory controller issues an auto refresh command to the packet controller through the packet data pin PACKET0 without transmitting an address. send. That is, no toggle of packet data pins occurs. The packet controller generates control signals in response to an auto refresh command sent over the packet data pin (PACKET0). The synchronous memory will then perform an auto refresh operation in response to control signals generated from the packet controller.

When the L ² RAM composed of the packet controller and the synchronous memory is controlled by the memory controller, as described above, the chip select signal output from the memory controller is used as a packet enable signal informing the start of transmission of packet data. However, when L ² RAMs are used in this module form, the chip select signal corresponding to each L ² RAM is used as a packet enable signal indicating the start of transmission of packet data and as a select signal for selecting the corresponding L ² RAM. Used. For example, as shown in FIG. 13, when a plurality of L ² RAMs are controlled by a memory controller, chip select signals (/ CS0- / CSn) will be allocated to each L ² RAM. Thus, the chip select signal corresponding to each L ² RAM is used as a packet enable signal informing the start of transmission of packet data and as a selection signal for selecting the corresponding L ² RAM.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, the number of pins of a multichip package or a system-in-package can be reduced by transmitting an address and a command to be input to the synchronous memory in the package in the form of a packet and converting the transmitted packet data according to the activation of the chip select signal. have.

Claims (52)

A plurality of packet pins; And Each includes a synchronous memory and a packet controller that operate in synchronization with a clock signal, When a packet enable signal is activated, the packet controller receives packet data through the packet pins in synchronization with the clock signal, and converts the input packet data into address and control signals; The synchronous memory receives the address and control signals in synchronization with the clock signal. The method of claim 1, And the synchronous memory performs a burst operation in synchronization with the clock signal. The method of claim 1, The synchronous memory and the packet controller are mounted in one package. The method of claim 3, wherein The package is any one of a multi-chip package and a system in a package. The method of claim 1, Any one of the packet pins is used to accept packet data related to a command. The method of claim 5, wherein And the packet data is a serial combination of the control signals. The method of claim 5, wherein And said packet data is a serial combination of data bits for defining said command. The method of claim 1, The synchronous memory is a double data rate synchronous DRAM (DDR SDRAM). The method of claim 1, The packet enable signal is a chip select signal. The method of claim 1, The plurality of packet pins include first to fifth packet pins, wherein the first packet pin receives packet data related to the command and each of the second to fifth packet pins receives packet data related to the address. Memory device. The method of claim 1, Data to be written to / read from / from the synchronous memory is transmitted without passing through the packet controller. The method of claim 1, The synchronous memory A memory cell array having a plurality of memory cells arranged in rows and columns; Row selection circuitry for selecting rows of said memory cell array in response to a row address from said packet controller; A column selection circuit for selecting columns of the memory cell array in response to a column address from the packet controller; And A write / read circuit for writing / reading data to / from memory cells designated by the selected rows and columns, wherein the row and column select circuits and the write / read circuit operate in synchronization with the clock signal. Memory device. The method of claim 1, And the burst operation of the packet data and the burst operation of the synchronous memory device are performed at the same operating frequency as the clock signal. The method of claim 1, The control signals include a row strobe signal (/ RAS), a column strobe signal (/ CAS), a write enable signal (/ WE), and an internal chip select signal (TCS). A first pin receiving a chip select signal; Second pins receiving clock signals; Third pins each receiving packet data; A memory operating in synchronization with the clock signals; And A packet controller operating in synchronization with the clock signals, When a chip select signal is activated, the packet controller receives packet data through the packet pins in synchronization with the clock signal, and converts the input packet data into address and control signals; The synchronous memory receives the address and control signals in synchronization with the clock signal. The method of claim 15, One of the third pins is used to receive packet data for defining a command, and the other is used to receive packet data indicating an address. The method of claim 15, Each of the third pins is used to receive packet data mixed with data bits and address signals for defining a command. The method of claim 15, Fourth pins for inputting and outputting data signals; A fifth pin receiving a clock enable signal; A sixth pin receiving a data strobe signal; And And a seventh pin receiving a data masking signal. And the data strobe signal, the data mask signal, the data signals, and the clock enable signal are transmitted directly to the synchronous memory. The method of claim 15, And the synchronous memory performs a burst operation in synchronization with the clock signals. The method of claim 15, The synchronous memory and the packet controller are mounted in one package. The method of claim 20, And the package is one of a multi-chip package and a system in package. The method of claim 15, Any one of the third pins is used to accept packet data related to an instruction. The method of claim 22, And the packet data associated with the command is a serial combination of the control signals. The method of claim 22, And the packet data associated with the command is a serial combination of data bits for defining the command. The method of claim 15, The synchronous memory is a double data rate synchronous DRAM (DDR SDRAM). The method of claim 15, The synchronous memory A memory cell array having a plurality of memory cells arranged in rows and columns; Row selection circuitry for selecting rows of said memory cell array in response to a row address from said packet controller; A column selection circuit for selecting columns of the memory cell array in response to a column address from the packet controller; And A write / read circuit for writing / reading data to / from memory cells designated by the selected rows and columns, wherein the row and column select circuits and the write / read circuit operate in synchronization with the clock signal. Memory device. The method of claim 15, And the burst operation of the packet data and the burst operation of the synchronous memory device are performed at the same operating frequency as the clock signal. The method of claim 15, The control signals include a row strobe signal (/ RAS), a column strobe signal (/ CAS), a write enable signal (/ WE), and an internal chip select signal (TCS). A synchronous memory device operating in synchronization with a clock signal; A memory controller generating the clock signal and outputting packet data; And A packet controller which operates in synchronization with the clock signal, and converts the packet data into address and control signals to conform to a communication protocol of the synchronous memory device, wherein the synchronous memory device and the packet The controller is an information processing system mounted in one package. The method of claim 29, And the packet controller is configured such that data is transmitted without change between the synchronous memory device and the memory control. The method of claim 29, And the synchronous memory device performs a burst operation in synchronization with the clock signal. The method of claim 29, The synchronous memory device A memory cell array having a plurality of memory cells arranged in rows and columns; Row selection circuitry for selecting rows of said memory cell array in response to a row address from said packet controller; A column selection circuit for selecting columns of the memory cell array in response to a column address from the packet controller; And A write / read circuit for writing / reading data to / from memory cells designated by the selected rows and columns, wherein the row and column select circuits and the write / read circuit operate in synchronization with the clock signal. Information processing system. The method of claim 29, And the package is one of a multi-chip package and a system in package. The method of claim 29, And the synchronous memory device is a double data rate synchronous DRAM (DDR SDRAM). The method of claim 29, And the burst operation of the packet data and the burst operation of the synchronous memory device are performed according to an operating frequency of the clock signal. A memory controller generating a clock signal and a chip select signal and outputting a plurality of data packets; Control logic that operates in response to activation of a chip select signal and generates a plurality of pulse signals synchronized with the clock signal; A plurality of registers respectively corresponding to the data packets, each register sequentially latching data bits of the corresponding data packet in response to the pulse signals and simultaneously outputting the latched data bits; A signal generator for generating control signals in response to data bits output from any one of the registers; And And a synchronous memory device operating in synchronization with the clock signal and receiving control signals output from the signal generator as commands and data bits output from the remaining registers as addresses. The method of claim 36, And information to be written to / read from the synchronous memory device is transferred between the synchronous memory device and the memory controller without modification. The method of claim 36, And the synchronous memory device performs a burst operation in synchronization with the clock signal. The method of claim 38, The synchronous memory device A memory cell array having a plurality of memory cells arranged in rows and columns; A row selection circuit that selects rows of the memory cell array in response to a row address of the address composed of some of the data bits output from the registers; A column select circuit for selecting columns of the memory cell array in response to a column address of the addresses; And A write / read circuit for writing / reading data to / from memory cells designated by the selected rows and columns, wherein the row and column select circuits and the write / read circuit operate in synchronization with the clock signal. Information processing system. The method of claim 39, And the synchronous memory device is a double data rate synchronous DRAM (DDR SDRAM). The method of claim 39, And the burst operation of the synchronous memory device is performed at the same operating frequency as the clock signal. The method of claim 36, Wherein any one of the data packets is a data packet related to an instruction. The method of claim 42, And the data packet associated with the command is a serial combination of the control signals. The method of claim 42, And the data packet associated with the command is a serial combination of data bits for defining the command. The method of claim 36, And the memory controller does not transmit data packets associated with an address when transmitting a data packet associated with an auto refresh command. The method of claim 36, Wherein the synchronous memory device, the plurality of registers, the signal generator, and the control logic are mounted in one package, wherein the package is one of a multi-chip package and a system in package. A memory controller generating a clock signal and a chip select signal and outputting a plurality of data packets; Control logic that operates in response to activation of a chip select signal and generates a plurality of pulse signals synchronized with the clock signal; A plurality of registers respectively corresponding to the data packets, each register sequentially latching data bits of the corresponding data packet in response to the pulse signals and simultaneously outputting the latched data bits; And And a synchronous memory device which operates in synchronization with the clock signal and receives data bits output from the registers as a command and an address, wherein a conversion operation of the data packets and a burst operation of the synchronous memory device include Information processing system performed at the same operating frequency as the signal. The method of claim 47, Wherein any one of the data packets is a data packet related to an instruction. The method of claim 47, And the data packet associated with the command is a serial combination of the control signals. The method of claim 47, And the data packet associated with the command is a serial combination of data bits for defining the command. The method of claim 47, And the memory controller does not transmit data packets associated with an address when transmitting a data packet associated with an auto refresh command. The method of claim 36, Wherein the synchronous memory device, the plurality of registers, and the control logic are mounted in one package, wherein the package is one of a multi-chip package and a system in package.