KR20040104970A - Parallel test increasing method and test system - Google Patents

Abstract

PURPOSE: A parallel test expansion method and a test system thereof are provided to increase a number of semiconductor chips to be tested while using a conventional test system. CONSTITUTION: A test system(200) for parallel test expansion includes a plurality of DUTs(Device Under Test)(210,240) and first through m-th switches(SW11,SW12). Each of the DUTs includes n channels, where n is a natural number. The switches are coupled with power channels(230) of each of the DUTs in parallel, where m is a natural number smaller than n. Each of the DUTs is capable of testing m semiconductor chips by using the first through m-th switches.

Description

Parallel test increasing method and test system

The present invention relates to test methods and test systems, and more particularly, to a parallel test extension method and test system for parallel extension of tests.

The test equipment can test several semiconductor chips at once. Typically, there are test equipment that can test 16 semiconductor chips at a time, and test equipment that can test 32 semiconductor chips at a time. Of course, there are test equipment that can test more semiconductor chips.

When testing the same number of semiconductor chips, test equipment that can test 16 semiconductor chips at a time increases test costs even more because test time is longer than test equipment that can test 32 semiconductor chips at a time.

In general, when testing a semiconductor chip, the number of parallel chips specified in the specification of the equipment (regardless of whether the test chip is large or small) means the number of semiconductor chips that the test apparatus can test at one time. In parallel, parallel tests of semiconductor chips have been performed.

1 is a diagram illustrating a general test system.

Referring to FIG. 1, the test system 100 includes two DUTs 110 and 160 and corresponding channel parts 120 and 170. The DUTs 110 and 160 are portions in which the semiconductor chip to be tested is placed. The channel units 120 and 170 have channels of test equipment connected to the test pins of the semiconductor chip placed on the DUTs 110 and 160.

As shown in FIG. 1, the channel units 120 and 170 may include driver channels 130 and 180 that may test driver pins of a semiconductor chip, input / output channels 140 and 190 that may test input / output pins of a semiconductor chip, and Power channels 150 and 195 are provided for testing the power pins of the semiconductor chip. In addition, the channel units 120 and 170 have channels for testing various signal pins of the semiconductor chip.

For example, assume that the parallel number of the test system 100 of FIG. 1 is 16, has 16 power channels, and has 32 channels allocated per DUT. If there is only one power pin of the semiconductor chip to be tested and 15 signal pins are used, the test system 100 of FIG. 1 may test only 16 semiconductor chips at a time.

That is, in the case of test equipment having a small number of parallels, when the number of semiconductor chips to be tested increases, there is a problem in that the number of test equipment is increased or the test time is lengthened.

The technical problem to be achieved by the present invention is to provide a test system that can increase the number of semiconductor chips that can be tested at a time while using the same test system.

Another object of the present invention is to provide a test method that can increase the number of semiconductor chips that can be tested at one time while using the same test system.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a general test system.

2 is a diagram illustrating a test system according to an embodiment of the present invention.

The test system according to an embodiment of the present invention for achieving the technical problem is a plurality of DUT (Device Under Test) having each of n (n is a natural number) and the first connected in parallel to the power channel of each DUT 1 to m (m is a natural number smaller than n) switches.

Each DUT may test m semiconductor chips through the first to m th switches. The m semiconductor chips to be tested are each characterized by having n / m (n / m is a natural number) test pins.

Each semiconductor chip being tested is connected to a power channel of a corresponding DUT through the switch to which one power pin of the test pin is connected, and the remaining test pin is connected to the remaining channel of the corresponding DUT.

In the case of a direct current test, the DUT connects only one of the first to mth switches and cuts off the remaining switches to perform a direct current test only on the connected semiconductor chip.

The parallel test extension method according to another embodiment of the present invention for achieving the technical problem is m (m is a natural number less than n) in the power channel of the n (n is a natural number) channels of the DUT (Device Under Test) By connecting the power pins of the chip jointly, the semiconductor chip to be tested at a time is increased by m times.

The m semiconductor chips have n / m (n / m is a natural number) test pins. The m semiconductor chips being tested are connected to a power channel of the DUT through a switch corresponding to each power pin, and the remaining test pins are connected to the remaining channels of the DUT.

In the parallel test extension method, in the case of a DC test, only one switch is connected and the other switches are blocked, so that the DC test is performed only on the semiconductor chip to which the switch is connected.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a diagram illustrating a test system according to an embodiment of the present invention.

According to the present invention, when the number of test pins of a semiconductor chip to be tested is less than the number of channels included in each DUT of the test system, the power channel of the test system is commonly connected to a plurality of semiconductor chips to be tested and one DUT is used. Test a plurality of semiconductor chips using.

Referring to FIG. 2, the test system 200 according to an embodiment of the present invention includes a plurality of device under tests (DUTs) 210 and 240 having n (n is a natural number) channels, and each DUT 210. And first through m (m is a natural number smaller than n) switches SW11 and SW12 connected in parallel to the power supply channel 230 of the 240.

The channel unit 220 may test the driver channels 231 and 233 for testing the driver of the semiconductor chip to be tested, the input / output channels 241 and 243 for testing the input / output pins of the semiconductor chip, and the power pins of the semiconductor chip. And a power channel 230 which may be. Although not shown, the channel unit 220 includes channels for testing various signal pins of the semiconductor chip.

Conventionally, although the number of test pins of a semiconductor chip to be tested is less than the number of channels of one DUT, channels corresponding to one DUT are used only to test one semiconductor chip.

However, in the test system 200 of the present invention, one DUT may test a plurality of semiconductor chips in consideration of the number of channels and the number of test pins of the semiconductor chip.

Assume that the number n of channels corresponding to one DUT of the test system 200 is 32. In addition, it is assumed that the number of test pins of the semiconductor chip to be tested is 16 including power supply pins.

Since the number of test pins of the semiconductor chip is 16, n / m = 16 and m becomes 2. That is, the test pins of two semiconductor chips may be connected to the channel of one DUT to test the same.

Since one channel unit 220 has one power channel 230, power pins of two semiconductor chips share one power channel 230 to test two semiconductor chips. The power channel is connected to the power pins of each of the two semiconductor chips using two switches SW11 and SW12.

When testing a semiconductor chip function, two semiconductor chips may be tested at a time by using channels corresponding to one DUT. That is, the driver pins and the input / output pins of the test pins of one semiconductor chip are connected to the driver channel 231 and the input / output channel 241, respectively, and the driver pins and the input / output pins of the test pins of the other semiconductor chip are respectively driver channels. 233 and an input / output channel 243.

Therefore, two semiconductor chips can be tested simultaneously.

When performing the DC test as the two semiconductor chips share the power channel 230, only one of the two switches SW11 and SW12 is connected and the other switches are blocked. The DC test is first performed only on the semiconductor chip connected to the power channel by the switch.

After the DC test is completed, the connection state of the switch can be changed to perform the DC test on the second semiconductor chip.

In FIG. 2, a case in which one DUT can test two semiconductor chips has been described as an example. However, if the number of test pins of the semiconductor chip is small, two or more semiconductor chips may be tested using one DUT.

That is, in the case of the number n of channels, if the number of test pins of the semiconductor chip is smaller than n / m, the number of semiconductor chips that can be tested at one time will be m. Of course you need m switches.

The parallel test extension method according to another embodiment of the present invention for achieving the technical problem is m (m is a natural number less than n) in the power channel of the n (n is a natural number) channels of the DUT (Device Under Test) It is a method of increasing the number of semiconductor chips tested at one time by jointly connecting the power pins of the chip.

When the number of test pins of the semiconductor chip is smaller than the number of channels of the DUT, the test pins of the plurality of semiconductor chips may be connected to the channels of one DUT to test the plurality of semiconductor chips at once.

If a DUT tests m semiconductor chips, the test system multiplies the number of semiconductor chips that can be tested at one time by m times. Since the DUT has only one power channel, the plurality of semiconductor chips must share the power channel of the DUT. The method of sharing the power channel of the DUT may use a method of connecting switches in parallel.

In case of performing the DC test, only one switch is connected and the other switches are cut off so that the DC test is performed only on the semiconductor chip to which the switch is connected. After the test, the DC test is performed by connecting the switch connected to the next semiconductor chip. .

Since the parallel test extension method corresponds to the operation of the test system of FIG. 2, a detailed description thereof will be omitted.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the test system and the parallel test extension method according to the present invention have an advantage of increasing the number of semiconductor chips that can be tested at one time while using the same test system.

Claims (8)

A plurality of device under tests (DUTs) each having n channels (n is a natural number); And A test system comprising first to mth switches (m is a natural number less than n) connected in parallel to a power channel of each DUT, Each DUT is A test system, characterized in that for testing the m semiconductor chips through the first to m-th switch. The m chip of claim 1, wherein each of the m semiconductor chips to be tested is and n / m (n / m is a natural number) test pins. The semiconductor chip of claim 2, wherein each of the semiconductor chips to be tested is And a power pin of one of the test pins is connected to the power channel of the corresponding DUT through the corresponding switch, and the remaining test pins are connected to the remaining channels of the corresponding DUT. The method of claim 1, wherein the DUT, In the case of the direct current test, only one of the first to m-th switches is connected, and the other switches are disconnected to perform a direct current test only on the connected semiconductor chip. In the parallel test expansion method of the test apparatus, Parallel to increase the number of semiconductor chips tested at one time by jointly connecting the power pins of m (m is a natural number less than n) semiconductor chips to the power channel among the n (n is natural numbers) channels of the DUT (Device Under Test) Test extension method. The method of claim 5, wherein the m semiconductor chips, and n / m (n / m is a natural number) test pins. The method of claim 5, wherein the m semiconductor chips to be tested, Wherein each power pin is connected to a power channel of the DUT through a corresponding switch, and the remaining test pins are connected to the remaining channels of the DUT. The method of claim 5, wherein In the case of the direct current test, only one switch is connected and the other switches are disconnected to perform the direct current test only on the semiconductor chip to which the switch is connected.