KR20040103515A - Apparatus and method for trimming reference voltage of a flash memory device - Google Patents

Abstract

PURPOSE: An apparatus and a method for trimming the reference voltage of a flash memory device is provided to simplify the reference voltage generation circuit by generating the reference voltage based on the information stored on the cord address memory(CAM) cell. CONSTITUTION: An apparatus for trimming the reference voltage of a flash memory device includes a cord address memory(CAM) cell unit(100), a CAM cell controller(200) and a reference voltage generation unit(300). The CAM cell unit outputs the control signal in response to the information stored on the CAM cell. The CAM cell controller controls the operation of the CAM cell unit. And, the reference voltage generation unit generates the reference voltage not affected to the external environment condition in response to the control signal.

Description

Apparatus and method for trimming reference voltage of a flash memory device

The present invention relates to an apparatus and method for trimming a reference voltage of a flash memory device, and to an apparatus and method for trimming a reference voltage of a flash memory device capable of trimming generation of an accurate reference voltage using a cam cell.

The internal voltage used during programming or programming of a typical flash memory is adjusted using a reference voltage. Since the reference voltage changes according to temperature, external power change, and process variation, the reference voltage is trimmed by using a trimming method using a fuse.

1 is a block diagram illustrating a reference voltage trimming apparatus and method according to the related art.

Referring to FIG. 1, a conventional reference voltage trimming apparatus includes a fuse cell block 10 that outputs a first control signal S1, a test bit block 20 that outputs a second control signal S2, and a first And a reference voltage generator 30 generating the reference voltage VREF_a according to the second control signals S1 and S2, a pad part 40 for applying an external reference voltage VREF_b bias, and switch control. The switch unit 50 outputs the reference voltage VREF by switching the output of the pad unit 40 or the reference voltage generator 30 according to the signal Tswitch.

Hereinafter, a trimming method using a conventional fuse will be described.

The fuse cell block 10 and the test bit block 20 generate first and second control signals S1 and S2 for adjusting the voltage level of the reference voltage VREF_a to be generated by the reference voltage generator 30. do. That is, the reference voltage generator 30 generates the reference voltage VREF_a which is not affected by external conditions by the first and second control signals S1 and S2. The reference voltages are used to generate desired voltages in the semiconductor device.

The conventional setting method for generating the first control signal S1 of the fuse cell block 10 will be briefly described as follows. As the tester performs the test, the fuse cutting is performed only once. As a result, during the initial test, there is a problem that the reference voltage VREF cannot be adjusted when it is higher or lower than a desired voltage. Since the reference voltage VREF is different from each chip, many problems occur in controlling the reference voltage generator 30 through a method of fuse cutting.

In order to solve the above problem, before the fuse is cut, the desired information is applied in advance in the test bit block to check whether the reference voltage VREF is correct. This leads to the problem of longer test times. In addition, when the reference voltage VREF_a set as described above is higher or lower than the target voltage, the pad part 40 is provided to apply an external reference voltage VREF_b to adjust the voltage. 40 and the switch unit 50 for controlling the output of the reference voltage generator 30 to solve the above problems. That is, the switch unit 50 is operated according to the switch control signal Tswitch to apply the reference voltage VREF_a, which is the output of the reference voltage generator 30, to the inside of the device, or output the pad 40 to the inside of the device. To apply. However, the size of the flash memory device may increase due to the addition of the switch unit 50 and the pad unit 40.

Therefore, the conventional trimming of the reference voltage using the fuse requires a circuit and a dummy pad that are additionally needed due to the problem of the one-off of the fuse.

Accordingly, the present invention can be easily adjusted according to the high and low bias of the reference voltage by using a code address memory (CAM) cell of the flash memory device in order to solve the above problems, and generates a reference voltage An object of the present invention is to provide a method and apparatus for trimming a reference voltage of a flash memory device, which can simplify a circuit for the purpose.

1 is a block diagram illustrating a reference voltage trimming apparatus and method according to the related art.

2 is a block diagram illustrating a method and apparatus for trimming a reference voltage of a flash memory device according to the present invention.

3A is a circuit diagram of a cam cell unit according to the present invention.

3B is a reference voltage generator circuit according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: fuse cell block 20: test bit block

30, 300: reference voltage generator 40: pad portion

50 switch unit 100 cam cell unit

200: cam cell control unit 110: cam cell array unit

120: decoder 122: switch means

124: Reader 126: Decoder

As a technical means for achieving the above object, an aspect of the present invention is a cam cell unit for outputting a control signal according to the information stored in the cam cell, a cam cell control unit for controlling the operation of the cam cell unit and the control signal Accordingly, there is provided a reference voltage trimming device for a flash memory device, comprising: a reference voltage generator configured to generate a reference voltage which is not affected by external conditions.

In addition, another aspect is a step of storing predetermined information in the cam cell in accordance with the cam cell control signal, outputting a predetermined control signal in accordance with the information stored in the cam cell and the reference voltage in accordance with the control signal It provides a reference voltage trimming method of a flash memory device comprising the step of generating.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

Referring to the flash memory device according to the present invention, an electrically programmable and eraseable flash memory cell has a basic structure of a gate, a source, and a drain in which a floating gate and a control gate are stacked. In a flash memory device, a plurality of flash memory cells are grouped into word lines and bit lines to form a memory cell array. In this case, a device in which an array of cells is connected in a string form is called a NAND flash memory device. The flash memory device includes a main cell array, a redundancy cell array, and a code storage memory cell array. The main cell array is composed of memory cells for program and erase, and the redundancy cell array is composed of flash cells for repairing defective cells of the main cell array, and the CAM cell array is a normal cell or defective. It consists of flash cells for storing cell information. In addition, in this embodiment, information for generating a reference voltage is input to the CAM cell array, and then the reference voltage generator is trimmed using the input information. At this time, by converting the information stored in the cam cell by the cam cell control unit, it is possible to modify the reference voltage to generate the target reference voltage. In addition, by controlling the reference voltage generator through the cam cell unit, a plurality of circuits required when the fuse cell block is used may be omitted. In addition, in order to obtain an accurate reference voltage for high voltage generation in a NAND flash memory device, a band gap reference voltage is generated and used as a reference voltage. However, this reference voltage is different for each chip as described in the prior art. As a result, the high voltage used by each chip varies. According to the present invention, the generation of a high voltage of each chip can be facilitated by trimming a reference voltage that differs from chip to voltage of a target level for each chip.

For convenience of description, the above-described CAM cell array and a plurality of circuit units for driving the same will be described as cam cell units.

Hereinafter, reference voltage trimming of the flash memory device of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram illustrating a method and apparatus for trimming a reference voltage of a flash memory device according to the present invention.

Referring to FIG. 2, the reference voltage trimming apparatus of a flash memory device may include a cam cell unit 100 that outputs a predetermined control signal S100 based on a data value input to a cam cell, and an external device according to the control signal S100. The reference voltage generator 300 outputs a reference voltage VREF that is not affected by the condition. The apparatus further includes a cam cell controller 200 for inputting data into the cam cell in the cam cell unit 100 and outputting a cam cell control signal CSC200 for controlling the operation of the cam cell unit 100.

The operation of the reference voltage trimming device having the above-described configuration will be described.

To generate the target reference voltage VREF, the cam cell controller 200 programs the cam cell unit 100 through the cam cell control signal CSC200. The cam cell unit 100 outputs a control signal S100 for controlling the reference voltage generator 300 through the information stored in the cam cell. The reference voltage generator 300 generates a target reference voltage VREF through the control signal S100 of the cam cell unit 100. The cam cell control signal CSC200, which is the output of the cam cell controller 200, may not only program or erase predetermined information in the cam cell in the cam cell unit 100, but also control the operation of the cam cell unit 100. have. The cam cell controller 200 may control the cam cell unit 100 by outputting a plurality of control voltages based on information input by a user.

Hereinafter, the operation of the cam cell unit 100 receiving the cam cell control signal CSC200 will be described based on the circuit diagram.

3A is a circuit diagram of a cam cell unit according to the present invention.

Referring to FIG. 3A, the cam cell unit 100 of the present invention decodes the cam cell array unit 110 in which a plurality of cam cells for storing predetermined information are arranged in a predetermined structure and the information stored in the cam cells. And a decoder unit 120 for outputting the control signal S100. The cam cell array unit 110 is programmed with predetermined information by the cam cell control signal CSC200 of the cam cell controller 200. The decoder 120 outputs a control signal S100 (trim signal) for controlling the reference voltage generator 300 according to information programmed in the cam cell array 110.

The circuit diagram shown in FIG. 3A illustrates a cam cell unit in which two cam cells are arranged, and is an exemplary view for briefly explaining a cam cell unit in which a plurality of cam cells are arranged.

The cam cell array unit 110 is connected between one input terminal and one output terminal of the cam cell array unit 110, and the first cam cell CS1 programmed and erased by an external cam cell control signal CSC200, and a cam. The second cam cell CS2 is connected between the other input terminal and the other output terminal of the cell array unit 110 and programmed and erased by the external cam cell control signal CSC200.

Decoder unit 120 includes a 2 × 4 decoder 126, wherein a first input of the decoder 126 is connected to the first cam cell CS1, and a second input of the decoder 126 is connected to the second cam cell CS2. The first to fourth output terminals of the decoder 126 are connected to the output terminal of the decoder unit 120.

Between the first and second cam cells CS1 and CS2 and the input terminal of the decoder 126, switch means 122 for controlling the transfer of status information of the cam cell, and a reader 124 for reading the status of the cam cell. ) May be connected in series. Thus, the output of the cam cell unit 100 can be controlled through the cam cell control signal CSC200 of the cam cell control unit 100 of FIG. 2. In addition, the cam cell information can be accurately read by comparing the external control voltage Vc with the cam cell information.

The cam cell unit 100 according to an embodiment of the present invention may be configured according to the first and second cam cells CS1 and CS2 programmed and erased according to the cam cell control signal CSC200 and the cam cell control signal CSC200. First and second switch means 122_a and 12_b for transmitting information stored in the first and second cam cells CS1 and CD2, respectively, and the first and second cam cells (according to an external control voltage Vc). First and second readers 124_a and 124_b for sensing information stored in CS1 and CS2, respectively, and first and second cam cells CS1 and CS2 read through the first and second readers 124_a and 124_b. The decoder 126 outputs a plurality of control signals S100 by decoding the information of the &lt; RTI ID = 0.0 &gt;

As a result, the decoder outputs a plurality of control signals S100_A to S100_D according to the state of information stored in the first and second cam cells CS1 and CS2. In this case, the output control signal S100 is maintained at a constant level unless the state of the information stored in the first and second cam cells CS1 and CS2 is changed.

For convenience of description, the control signal S100 that is an output in the cam cell unit 100 is divided into first to fourth control signals S100_A to S100_D in accordance with the output of the decoder 120 of FIG. 3A. The reference voltage generator 300 also generates a constant reference voltage VREF with little change by an external element by the first to fourth control signals S100_A to S100_D output from the decoder 120.

The reference voltage generator 300 may be configured as a circuit for generating a constant voltage that does not change according to temperature, external power change, and process variation. Hereinafter, the band gap reference circuit is illustrated and described as the reference voltage generator 300.

3B is a reference voltage generator circuit according to the present invention.

Referring to FIG. 3B, the reference voltage generator 300 includes first to seventh transistors T1 to T7 and first to fifth resistors R1 to R5. The first and second transistors T1 and T2 are connected in series to the power supply voltage Vcc and the reference voltage output terminal, and are driven by respective junctions. The third transistor T3 and the first resistor R1 are connected between the reference voltage output terminal and the first node Q1, and the third transistor T3 is driven by the reference voltage output terminal. The first to third transistors T1 to T3 are diode-connected (to which a gate terminal and a drain terminal / source terminal are connected). The fourth transistor T4 is connected between the first node Q1 and the ground voltage Vss and is driven by the first control signal S100_A of the cam cell unit 100. The second resistor R2 is connected between the first node Q1 and the second node Q2. The fifth transistor T5 is connected between the second node Q2 and the ground voltage Vss and driven by the second control signal S100_B of the cam cell unit 100. The third resistor R3 is connected between the second node Q2 and the third node Q3. The sixth transistor T6 is connected between the third node Q3 and the ground voltage Vss and is driven by the third control signal S100_C of the cam cell unit 100. The fourth resistor R4 is connected between the third node Q3 and the fourth node Q4. The seventh transistor T7 and the fifth resistor R5 are connected in parallel between the fourth node Q4 and the ground voltage Vss, and the seventh transistor T7 is connected to the fourth control signal of the cam cell unit 100. S100_D).

In the reference voltage generator 300 having the above connection relationship, the driving of the fourth to seventh transistors T4 to T7 is controlled according to the control signal S100 of the cam cell unit 100. As a result, the voltage is divided by the first to fifth resistors R1 to R5 to output a constant voltage.

The first and second transistors T1 and T2 use PMOS transistors, and the third to seventh transistors T3 to T7 use NMOS transistors. The first to fifth resistors R1 to T5 may use element resistances as well as resistors used in semiconductor devices. The first to fifth resistors R1 to R5 may have different resistance values according to the target reference voltage VREF or may have the same value.

A reference voltage generation using two trim bits according to an embodiment of the present invention will be described in detail with reference to the circuit diagram and the block diagram described above.

Information for generating a target reference voltage VREF is input to the first and second cam cells CS1 and CS2 in the cam cell unit 100 through the cam cell controller 200. The cam cell unit 100 reads information stored in the first and second cam cells CS1 and CS2 through the cam cell control signal CSC200 and the external control voltage Vc, and decodes the first and fourth controls. One control signal S100 of the signals S100_A to S100_D is output. One of the fourth to seventh transistors T4 to T7 is operated by the first to fourth control signals S100_A to S100_D to operate the voltage by the first to fifth resistors R1 to R5 connected to each transistor. Are distributed to produce the desired constant reference voltage.

When the reference voltage through the above method is not the target voltage, the cam cell controller 200 may erase the information of the cam cell and reprogram it to generate the correct reference voltage VREF. That is, since the cam cell control signal CSC200 of the cam cell control unit 200 can program / erase various types of information to the cam cell, the target reference voltage VREF can be easily generated, and the conventional external A reference voltage can be generated without a pad part receiving a reference voltage from the pad, a switch part therefor, and a test bit part, and tested.

As described above, the present invention can simplify the circuit for generating the reference voltage by generating the reference voltage based on the information stored in the cam cell.

In addition, an accurate reference voltage can be generated through the program / erase of the cam cell.

Claims (6)

A cam cell unit for outputting a control signal according to the information stored in the cam cell; A cam cell control unit for controlling the operation of the cam cell unit; And And a reference voltage generator configured to generate a reference voltage which is not influenced by external conditions according to the control signal. The method of claim 1, wherein the cam cell unit, A cam cell array unit comprising a plurality of cam cells; And And a decoder unit for decoding the information stored in the cam cell array unit to output the control signal. The method of claim 1, wherein the cam cell unit, First and second cam cells having a program or erase state; First and second switch means for transmitting information stored in each of the first and second cam cells; First and second readers configured to sense information stored in each of the first and second cam cells according to an external control voltage; And And a decoder which decodes information of the first and second cam cells read through the first and second readers and outputs a plurality of control signals. The method of claim 1, And the cam cell is a flash memory cell. Storing predetermined information in the cam cell according to the cam cell control signal; Outputting a predetermined control signal according to the information stored in the cam cell; And And generating a reference voltage according to the control signal. The method of claim 5, wherein the outputting the control signal, Sensing information stored in the cam cell by using an external control voltage; And And outputting a control signal by decoding the sensed information.