KR0172411B1 - Memory apparatus of non-volatile semiconductor - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

An electrically erasable and programmable nonvolatile semiconductor memory device for programming multiple states of data in one memory cell.

2. The technical problem to be solved by the invention

The present invention provides an electrically erasable and programmable nonvolatile semiconductor memory device having a simple circuit configuration and reduced layout despite an increase in the number of programs.

3. Summary of Solution to Invention

In an electrically erasable and programmable nonvolatile semiconductor memory device having a program voltage generator circuit for programming a plurality of states of data in a single memory cell, a voltage generated by the program voltage generator circuit in a program or erase operation mode is used. It is essential to have a control means for automatically increasing.

4. Important uses of the invention

Suitable for nonvolatile semiconductor memory devices.

Description

Nonvolatile Semiconductor Memory Devices

1 is a block diagram schematically illustrating a circuit for outputting a program voltage according to an embodiment of the present invention.

2A and 2B are detailed views showing a program voltage sensing circuit according to the prior art and the embodiment of the present invention, respectively.

3 is a diagram illustrating a program loop binary counter 106 according to an embodiment of the present invention.

4 is a detailed view of a program loop detector 107 according to an embodiment of the present invention.

5 is a view showing a waveform diagram according to another embodiment of the present invention.

6 is a diagram illustrating a program voltage value and a variation amount according to the number of programs according to an embodiment of the present invention.

7 is a diagram showing the complexity of the circuit and the size of the layout with respect to the increase in the number of programs according to the prior art and the embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electrically erasable and programmable nonvolatile semiconductor memory devices, and more particularly to electrically erasable and programmable nonvolatile semiconductor memory devices for programming multiple states of data in one memory cell.

In general, in an electrically erasable and programmable nonvolatile semiconductor memory device (hereinafter referred to as EEPROM), program voltage adjustment is very important for determining a threshold voltage of a cell, and research on such a program method has recently been conducted. In particular, in the case of a multi-bit flash EEPROM that programs and reads a plurality of data in one cell, a more accurate threshold voltage adjustment is required than a single bit flash, and the method of adjusting the program voltage is an important factor.

The conventional technology automatically increases the program voltage within a chip by a predetermined value, that is, performs a stepping program, and determines that the program has been programmed with an appropriate threshold voltage through program verification at each step. Completion is determined.

This conventional stepping program method has a high voltage level sensing circuit in which resistance elements are connected in series to implement the program voltage of each step. If there are many high voltage levels to be implemented, a decoding signal is required as many as the number of resistors, so that not only the high voltage level sensing circuit but also the decoding circuit becomes complicated and the layout area becomes large. In particular, in the case of the multi-bit flash EEPROM as described above, the above-mentioned problem becomes very serious because the program voltage level is further increased as compared with the single bit.

Accordingly, an object of the present invention is to provide a program voltage sensing circuit of an electrically erased and programmable nonvolatile semiconductor memory device having a reduced layout.

Another object of the present invention is to provide a program sensing circuit of an electrically erasable and programmable nonvolatile semiconductor memory device whose circuit configuration is simplified.

Another object of the present invention is to provide an electrically erasable and programmable nonvolatile semiconductor memory device having a simple circuit configuration and reduced layout despite an increase in the number of programs.

According to the technical idea of the present invention for achieving the above object, in the electrically erasable and programmable nonvolatile semiconductor memory device having a program voltage generation circuit for programming a plurality of states of data in one memory cell, And control means for automatically increasing the voltage generated by the program voltage generator in the program or erase operation mode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a circuit for outputting a program voltage according to an embodiment of the present invention.

In the following description, for convenience of explanation, the present invention describes a program of a NAND type flash EEPROM. It will be apparent to one of ordinary skill in the art that this has been presented to provide a more general understanding of the invention, but not limited thereto.

The NAND flash structure and operation are described in detail in Korean Application No. 93-00390 Nonvolatile Semiconductor Memory Device. Referring to FIG. 1, a program voltage generation circuit 101 for generating a program voltage Vpgm, a program voltage detection circuit 102 for sensing a program voltage connected to an output terminal thereof, and a reference program voltage generation circuit 103 for sensing. And a program generation circuit controller 105 for enabling or disabling the operation of the program voltage generator circuit 101 by the output of the high voltage program voltage sense amplifier circuit 104 and the high voltage program voltage sense amplifier circuit 104. And a program loop binary counter 106 for detecting the generated pulse and counting the number of programs, and a program loop detector 107 for decoding the output of the program loop binary counter 106. The present invention aims to improve the program voltage sensing circuit 102 connected to the output terminal of the program loop sensing circuit 107 and the output loop of the program loop binary counter 106 and connected to the output terminals of the program voltage sense amplifying circuit 104 and the program voltage generating circuit 101. In particular, the present invention aims to provide a program voltage sensing circuit 102 having a reduced layout by minimizing the number of elements in a recent NAND-type flash EEPROM for storing a plurality of multi-bit data.

2A and 2B are detailed views showing the program voltage sensing circuit 102 according to the prior art and the embodiment of the present invention, respectively. First, referring to FIG. 2A, one end is connected to the generated program voltage and resistors Ra, Rb, R32,... R1 is connected to the ground voltage terminal in series, and the resistors R32,... At one end of R1, the output signals of the program loop detector 107, TRM32,... The N-type control transistor gated by the TRM1 is connected in series to the ground power supply terminal in parallel. According to this conventional configuration, if the program voltage is 0.2V in the case of multi-bit, a total of 32 stepping programs require 34 resistors, 32 decoded signals, and 32 N-type control transistors as shown in the drawing. Therefore, the increase in layout becomes an inevitable problem. 2b has a configuration as follows to solve the problem. That is, the resistors Ra, Rb, Rc, and Ro1 are connected in series to sense the proper program voltage for each program to the program voltage, and at one end of each of the resistors Ra, Rb, Rc, and Ro1 are output signals of the program loop detector 107. Select transistors M5, M6, and M7 gated by TRM4, TRM3, and TRM2 are connected in series to the source terminal in parallel.

In addition, the select transistors M1, M2, M3, and M4 gated by the output signals of the program loop detector 107 TRM1, TRM2, TRM3, and TRM4 in parallel to the resistor Ro1 are connected in parallel, and the select transistors M1, M2, One end of M3, M4 is connected in series with the ground voltage, and the first, second, third, and fourth resistance stages 301, 302, 303, and 304 are connected to each other. The resistors constituting the respective resistance stages are the control transistors M10, M11, M12, M20, M21, M22, M30, M31, M32, M40, gated by the output signals of the program loop binary counter 106, Mout0, Mout1, and Mout2. The resistor is composed of M41 and M42, and the resistor is composed of a double value of resistance value which is distinguished from the resistor stage, respectively. The node 401 between Ra and Rb is connected to the program voltage sense amplifier circuit 104 shown in FIG. 1 to sense the high voltage level.

Before explaining the effect of the present invention, the initial program voltage is 14.66. The turn-on resistance of the select transistors M1 to 4 is small enough to be ignored, and Δ for each program. pgm about 0.2 Suppose that you increment by.

In addition, when the node 401 is connected to the program voltage sense amplifying circuit 104 and is equal to the output value of the reference voltage generating circuit 103 of FIG. Assume

A characteristic effect according to the configuration of the present invention under the assumption of the above-described assumption will be described with reference to FIG. 6 which shows a program voltage value and a change amount according to the number of programs according to an embodiment of the present invention.

First, if the program has been run once, Mouto = High, Mouto1 ~ 3 = Low, TRM1 = High, TRM2 ~ 4 = Low The pgm levels are as follows:

Thus, if Vpgm is increased by 0.17V compared to the circuit, and the program is run twice,

Therefore, Vpgm increased by 0.18V compared with one time.

If the program has been done 31 times,

If the program has been run 32 times,

Program 1 to 32 times in the same way as above pgm and Step pgm = Δ The result of calculating pgm is shown in FIG.

Therefore, in the present invention, since each of the select transistors and the control transistors are coded by binary data, and the resistance values of series-connected resistor structures 301 to 304 are determined to be doubled, the resistance values are changed corresponding to the binary coding data, and each step Δ pgm is about 0.2 The level is maintained.

Δ for the present invention pgm = 0.2 In order to program a total of three times, 17 resistors are needed, and since the decoded signals are also TRM1-4 and Mot0-2, only seven are needed. As a result, remarkable element reduction can be expected as compared with the conventional configuration.

The following describes a peripheral circuit to explain the control signals of the present invention.

3 is a detailed view showing a program loop binary counter 106 according to an embodiment of the present invention. Referring to FIG. 3, Sapgm is enabled from low to high level when entering the program mode. Is a short pulse that occurs every program after entering the program mode. The output gates Mout 0 to Mout4 described above are output by the transmission gates including the shaped and N-type transistors 302, 303, 304, 305, 306, 307, 308, and 309, and the NAND gates 311, 313, inverters 310, and 312. Since five program loop binary counters 106 of the above structure are connected in series. Depending on the toggle, the outputs of each counter, Mouto, 1, 2, 3, and 4, have binary data, with values up to 2 ⁵ . Although five counter circuits are shown for convenience of description according to the present invention, it is obvious that other things are possible.

For example, if Sappm is low, Mout 0, 1, 2, 3, and 4 are all 0, and Sapgm is enabled high. Is toggled five times, i.e. if the program has been executed five times, Mout 0 = 1, Mout 1 = 0, Mout 2 = 1, Mout 3 = 0, Mout 4 = 0, and if converted to decimal, it corresponds to 5. do.

4 is a detailed view showing a program loop detector 107 according to an embodiment of the present invention. Referring to Fig. 4, since Mout 0 to 4 are binary data, TRM1 to 4 binary data are output. TRM1 is Will toggle high 1-8 times, TRM2 9-16 times, TRM3 17-24 times, TRM4 25-32 times Is output high when toggled.

5 is a view showing a waveform diagram according to an embodiment of the present invention. Referring to FIG. 5, when Sapgm is enabled and the program is started, the program voltage level is automatically determined by Mout0 ~ 2 and TRM1 ~ 4.

7 is a diagram showing the complexity of the circuit and the size of the layout with respect to the increase in the number of programs according to the prior art and the embodiment of the present invention. Referring to FIG. 7, the program voltage sensing circuit 102 has the same step-by-step Δ if all resistors are connected in series as in the prior art. pgm = 0.2 In order to program 32 times, 34 resistors, 32 decoded signals, and 32 control gates are required. Therefore, the program voltage sensing circuit is much more complicated, the layout area is larger, and the decoding circuit is more complicated than the present invention. In addition, it can be seen that as the number of programs increases, the effect of the present invention increases when the circuit complexity and layout area are compared with those of the prior art.

Claims (5)

An electrically erasable and programmable nonvolatile semiconductor memory device having a program voltage generator circuit for programming a plurality of states of data in a single memory cell, comprising: a voltage generated by the program voltage generator circuit in a program or erase operation mode; Non-volatile semiconductor memory device characterized in that it has a control means for automatically increasing the number. The method of claim 1; And when the voltage is automatically increased, the high voltage is determined by voltage distribution of resistance elements having different resistance values, and the resistance elements are controlled by binary data. The method of claim 2; And each of the resistance values is doubled. The method of claim 1, wherein the control means is connected to the first, second, third and fourth resistors in series for sensing the appropriate program voltage at every program with the program voltage. At one end of each of the first, second, and third selection transistors gated by an external output signal, connected in series to the source terminal in parallel, and the fourth, fifth gated by the external output signal in parallel to the fourth resistor 1. , 6, 8 select transistors are connected in parallel, and the first, second, third and fourth resistor terminals are connected in series with the ground voltage at one end of the fourth, 5, 6, 8 select transistors. A nonvolatile semiconductor memory device. The method of claim 4; And the resistance stages comprise a plurality of control transistors gated by an external output signal and a resistance element distinguished by a double value of resistance.