KR20040103026A - A method for connecting ferroelectric random access memory cells and a ferroelectric random access memory having such a connecting structure - Google Patents

Abstract

PURPOSE: A connecting method of a ferroelectric memory cell and a ferroelectric memory thereby are provided to perform a reading process and a writing process on a selected cell alone without interference between cells by connecting upper electrodes and sources of FETs(Field Effect Transistors) in columns and lower electrodes and drains of the FETs in rows using bit lines and word lines. CONSTITUTION: A ferroelectric memory cell array includes a plurality of ferroelectric memory cells. Each cell(1) includes a FET. The FET includes an upper electrode(2) and a lower electrode(3) of a gate with a metal-ferroelectric-metal-insulator-silicon structure, a source(4) and a drain(5). The upper electrode is connected to a write bit line(6) in column. The lower electrode is connected to a write word line(7) in row. The source is connected to a read bit line(9) in column. The drain is connected to a read word line(8) in row.

Description

A method of connecting a ferroelectric memory cell and a ferroelectric memory by the connection method {A METHOD FOR CONNECTING FERROELECTRIC RANDOM ACCESS MEMORY CELLS AND A FERROELECTRIC RANDOM ACCESS MEMORY HAVING SUCH A CONNECTING STRUCTURE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of connecting a ferroelectric memory cell and a method of connecting a ferroelectric memory cell, and more particularly, to a method of connecting a ferroelectric memory cell and a method of connecting the ferroelectric memory cell so that read and write operations can be performed only in a desired memory cell without interference with each other. By ferroelectric memory.

In today's most commonly used one-transistor, one-capacitor DRAM, word lines read the data stored in each cell by sending the charges charged to the capacitor to the bit lines. In order to read data at a desired position, a decoded signal indicating a row and a column of one cell in a matrix arranged structure is used.

In the read operation, the word line to which the row address decoding signal is input is selected, the charge of the capacitor moves to the bit line, the bit line to which the column address decoding signal is input is selected, and the signal of the bit line is transmitted to the sense amplifier.

In the write operation, data is sent to the bit line selected by the column address decoding signal, the word line to which the row address decoding signal is input is selected, and the data is stored in the capacitor.

On the other hand, a ferroelectric memory (MFMIS 1T Type FRAM) in the form of a 1 field effect transistor (FET) having a gate of a metal-ferroelectric-metal-insulator-silicon (hereinafter referred to as MFMIS) structure Since the signal required when a cell is selected is different from that of a general DRAM, generation of a new signal and arrangement of cells are required for the operation of the memory.

1 shows an MFMIS transistor as a memory cell constituting a ferroelectric memory array. As shown in FIG. 1, in order to effectively drive a FET having a gate of an MFMIS structure as a memory cell, a signal is applied by separating an upper electrode and a lower electrode of the gate together with the source and drain terminals of the FET.

Table 1 shows the operating characteristics of the MFMIS 1T Type FRAM.

Upper electrode Bottom electrode drain sauce Read action Vread Floating + Vcc Read Out '0' write operation grounding Vwrite Floating Floating '1' write operation Vwrite grounding Floating Floating

As can be seen from Table 1, in the read operation, a read voltage (Vread) is applied to the upper electrode, a floating electrode is applied to the lower electrode, and a power supply voltage (+ Vcc) is applied to the drain. Read out data by reading.

In the case of the '0' write operation, the upper electrode is grounded and the write voltage Vwrite is applied to the lower electrode. In the '1' write operation, the write voltage is applied to the upper electrode, and the lower electrode is grounded. In the write operation, both the drain and the source are floating.

In addition, in order to prevent interference between cells during the memory operation, both the upper electrode and the lower electrode of the unselected cells are floated.

As such, when a cell is selected by a decoding signal indicating a row and a column, a read voltage, a ground voltage, a write voltage, and a floating signal should be generated at the upper electrode, and a write voltage, ground voltage, and floating signal at the lower electrode. There is a problem in that the cell cannot be driven by the conventional method because needs to be generated.

It is designed to solve the above problems of the present invention, and is selected by connecting a memory cell so that there is no interference, generating a driving signal necessary for reading and writing the memory, and outputting the driving signal in accordance with the connection structure of the memory cell. An object of the present invention is to provide a method of connecting a ferroelectric memory cell capable of driving a memory cell, and a ferroelectric memory by the connecting method.

To this end, the present invention, when the ferroelectric memory cell consisting of a field-effect transistor having an upper electrode and a lower electrode, a source and a drain of the gate of the metal-ferroelectric-metal-insulator-silicon structure in an array In the connection method,

The upper electrode is connected to a plurality of write bit lines WBL arranged in columns, the lower electrode is connected to a plurality of write word lines WWL arranged in rows, and the source is a plurality of read bit lines arranged in columns. The drain is connected to a plurality of read word lines RWL arranged in rows.

In addition, the present invention relates to a ferroelectric memory having an array of ferroelectric memory cells composed of a field effect transistor having an upper electrode and a lower electrode, a source and a drain of a gate of a metal-ferroelectric-metal-insulator-silicon structure,

The upper electrode is connected to a plurality of write bit lines WBL arranged in columns, the lower electrode is connected to a plurality of write word lines WWL arranged in rows, and the source is a plurality of read bit lines arranged in columns. The drain is connected to a plurality of read word lines RWL arranged in rows to form an array;

A write bit line driving circuit connected to the plurality of write bit lines arranged in the column, a write / read word line driving circuit connected to the plurality of write word lines and read word lines arranged in the row, and a plurality of reads arranged in the column And a sensing circuit connected to each of the bit lines, and a sensing circuit connected to each of the data transmission circuits.

1 is a symbol diagram showing the structure of an MFMIS transistor which is a memory cell constituting a ferroelectric memory array.

2 is an internal configuration diagram of a ferroelectric memory according to the present invention.

3A to 3C are graphs showing a result of performing a read / write operation on a ferroelectric memory according to the present invention.

** Explanation of Signs of Major Parts of Drawings **

1: memory cell 2: upper electrode

3: lower electrode 4: source

5: drain 6: write bit line (WBL)

7: Write word line (WWL) 8: Read word line (RWL)

9: read bit line (RBL) 10: write bit line driving circuit

11: write / read word line driver circuit 12: data transfer circuit

13: sensing circuit

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 shows a structure of a ferroelectric memory according to the present invention.

First, in the ferroelectric memory according to the present invention, as shown in FIG. 2, as shown in FIG. 2, memory cells 1 composed of MFMIS transistors are arranged, and upper electrodes 2 of each memory cell 1 are arranged. ) Is connected to a plurality of write bit lines (WBL) 6 arranged in a column, the lower electrode 3 is connected to a plurality of write word lines (WWL) 7 arranged in a row, and the source 4 is A plurality of read bit lines (RBL) 9 arranged in a column are connected, and a drain 5 is connected to a plurality of read word lines RWL 8 arranged in a row.

The ferroelectric memory according to the present invention constitutes a memory array with a connection structure of the above-described memory cells, and includes a write bit line driver circuit 10 connected to a plurality of write bit lines 6 arranged in rows, and arranged in the rows. Write / read word line driver circuits 11 connected to a plurality of write word lines 7 and read word lines 8, and data transfer circuits 12 connected to each of the plurality of read bit lines 9 arranged in the column. And a sensing circuit 13 connected to the data transmission circuit 12.

The write bit line driver circuit 10 generates a write voltage, a read voltage, a ground voltage, and a floating voltage in the write bit line 6, and the write / read word line driver circuit 11 is connected to the write word line 7. A write voltage, a ground voltage and a floating voltage are generated, and a power supply voltage (+ Vcc) and a floating voltage are generated on the read word line 8.

In the ferroelectric memory of the present invention, during a read operation, a read voltage Vread is applied to the write bit line 6 selected by the column address, and a floating voltage is applied to the write word line 7 selected by the row address. And applying a power supply voltage Vcc to the read word line 8 selected by the row address, applying a floating voltage to all unselected bit lines and word lines, and detecting a voltage or current at the selected read bit line. As a result, a read operation is performed on the selected memory cell.

As the threshold voltage shifts depending on whether '0' or '1' is written in the selected cell, if '0' is written by the applied read voltage, the transistor is still off, so that the current in the source 4 If it fails to flow and '1' is written, the transistor is turned on and current flows to the source 4. At this time, the unselected column is still off because no read voltage is applied, and the unselected row does not flow current because the drain 5 is floating even though there is a column to which the read voltage is applied to the upper electrode 2. Does not cause interference

The current flowing in the selected cell at the time of reading is transferred to the sensing circuit 13 along the selected read bit line 9 through the data transmission circuit 12 to determine whether '0' or '1' is written. Since the signal of the unselected read bit line 9 does not pass through the data transmission circuit 12, no signal is transmitted to the sensing circuit 13, and only the signal of the selected read bit line 9 is transmitted.

In a '0' write operation, a ground voltage is applied to the selected write bit line 6, a write voltage Vwrite is applied to the selected write word line 7, and a floating voltage is applied to the selected read word line 8. By applying, applying a floating voltage to the selected read bit line 9, and applying a floating voltage to all unselected bit lines and word lines, a '0' write operation is performed for the selected memory cell.

When the upper electrode 2 is grounded and a read voltage is applied to the lower electrode 3, the polarization is reversed. Since the unselected rows are floating, no change in polarization occurs, and the unselected columns do not cause polarization changes even when the read voltage is applied to the lower electrode 3 because the upper electrode 2 is floating.

A write operation of '0' may be regarded as an erase operation, and erase may be performed in units of rows to avoid interference. In this case, the entire upper electrode 2 may be grounded and a read voltage may be applied to only the selected row so that the entire row may be written as '0' at once (that is, erased). This has the advantage of reducing interference in '0' write operations.

In a '1' write operation, a write voltage Vwrite is applied to the selected write bit line 6, a ground voltage is applied to the selected write word line 7, and a floating voltage is applied to the selected read word line 8. By applying, applying a floating voltage to the selected read bit line 9 and applying a floating voltage to all unselected bit lines and word lines, a '1' write operation is performed on the selected memory cell.

A write voltage is applied to the upper electrode 2 of the selected column and the lower electrode is grounded. At this time, the unselected column does not cause any change because the upper electrode 2 is floating, and the unselected row is shown by the following equation (1) even if a write voltage is applied to the upper electrode 2. If 3) is floating, the voltage Vc is not applied enough to change the polarization of the ferroelectric, and thus the polarization does not change.

3 is a graph showing a result of performing a read / write operation on the MFMIS 1T Type FRAM according to the present invention.

3A illustrates a signal in a selected cell during a read operation. In FIG. 3A, the first graph shows the signal of the read word line 8 connected to the drain 5, and the power supply voltage (+ Vcc), and the second graph shows the write bit line connected to the upper electrode 2. The signal of (6) is shown to show the read voltage (Vread), and the third graph shows the signal of the write word line (7) connected to the lower electrode (3).

3B illustrates a signal of a selected cell when writing '0'. In FIG. 3B, the first graph shows a floating read word line, the second graph shows a grounded write bit line, and the third graph shows a write word line to which a write voltage is applied.

3C illustrates a signal of a selected cell when writing '1'. In FIG. 3C, the first graph represents a floating read word line, the second graph represents a write bit line to which a write voltage is applied, and the third graph represents a grounded write word line.

Simulation of such read / write shows that the ferroelectric memory of the present invention operates effectively.

As described above, the present invention connects the MFMIS 1T Type FRAM cell with the above-described connection method, and configures the ferroelectric memory by installing a driving circuit for generating a desired signal in the memory array having such a connection structure, thereby reading the selected cell. Can effectively perform / write operation without interference.

In addition, according to the present invention, memory cells may be integrated in an MFMIS 1T Type FRAM, thereby accelerating the commercialization of ferroelectric memory chips.

Claims (7)

A method of connecting ferroelectric memory cells when an array of ferroelectric memory cells composed of field effect transistors having an upper electrode and a lower electrode, a source and a drain of a gate of a metal-ferroelectric-metal-insulator-silicon structure, comprising: The upper electrode is connected to a plurality of write bit lines WBL arranged in columns, the lower electrode is connected to a plurality of write word lines WWL arranged in rows, and the source is a plurality of read bit lines arranged in columns. And a drain connected to a plurality of read word lines RWL arranged in rows. The method of claim 1, In the read operation, a read voltage Vread is applied to the selected write bit line, a floating voltage is applied to the selected write word line, a power supply voltage Vcc is applied to the selected read word line, and all unselected bit lines are applied. And applying a floating voltage to the word line and sensing a voltage or a current at the selected read bit line to perform a read operation on the selected memory cell. The method of claim 1, In a '0' write operation, a ground voltage is applied to the selected write bit line, a write voltage Vwrite is applied to the selected write word line, a floating voltage is applied to the selected read word line, and a flow is applied to the selected read bit line. A method for connecting a ferroelectric memory cell, characterized in that a '0' write operation is performed on a selected memory cell by applying a floating voltage and applying a floating voltage to all unselected bit lines and word lines. The method of claim 1, In a '1' write operation, a write voltage Vwrite is applied to the selected write bit line, a ground voltage is applied to the selected write word line, a floating voltage is applied to the selected read word line, and a flow is applied to the selected read bit line. A method of connecting a ferroelectric memory cell, characterized in that a '1' write operation is performed on a selected memory cell by applying a floating voltage and applying a floating voltage to all unselected bit lines and word lines. A ferroelectric memory having an array of ferroelectric memory cells consisting of field effect transistors having an upper electrode and a lower electrode, a source and a drain of a gate of a metal-ferroelectric-metal-insulator-silicon structure, The upper electrode is connected to a plurality of write bit lines WBL arranged in columns, the lower electrode is connected to a plurality of write word lines WWL arranged in rows, and the source is a plurality of read bit lines arranged in columns. The drain is connected to a plurality of read word lines RWL arranged in rows to form an array; A write bit line driver circuit connected to the plurality of write bit lines arranged in the column; A write / read word line driver circuit connected to the plurality of write word lines and read word lines arranged in the row; A data transmission circuit connected to each of the plurality of read bit lines arranged in the column; And a sensing circuit connected to the data transmission circuit. The method of claim 5, And the write bit line driver circuit generates a write voltage, a read voltage, a ground voltage, and a floating voltage. The method of claim 5, And the write / read word line driver circuit generates a write voltage, a ground voltage and a floating voltage on the write word line, and generates a power supply voltage and a floating voltage on the read word line.