KR20040101344A - Power control of a processor using hardware structures controlled by a compiler with an accumulated instruction profile - Google Patents

Abstract

The microprocessor according to the invention comprises a logic circuit. A selection device is coupled to this logic circuit, which switches the logic circuit on / off based on the stored logic value. Program instructions for setting stored logic values to control the on / off state of the logic circuit based on the expected usage of the logic circuit in accordance with the instruction sequence of the microprocessor.

Description

A microprocessor, an instruction sequence generation method and a program device implementing the same {POWER CONTROL OF A PROCESSOR USING HARDWARE STRUCTURES CONTROLLED BY A COMPILER WITH AN ACCUMULATED INSTRUCTION PROFILE}

The dynamic power control of a processor can be divided into two general categories: cycle-by-cycle control using the clock gating technique and longer terms based on software settings in power saving mode. Can be divided into control. Clock gating relies on logic circuitry to analyze whether a function is used during the current clock cycle, and if not, degating the clock as part of the logic used by that function. )do. This process consumes power in analysis logic to save power in clocked logic. In addition, since the clocked logic is active, only the dynamic component of power dissipation is removed during the cycle of clock clocking. It would also be desirable to eliminate leakage or static components as well. The power saving mode is used for long term power savings, but more overhead is required to invoke this mode to resume normal operation.

U.S. Patent No. 4,980,836 APPARATUS FOR REDUCING COMPUTER SYSTEM POWER CONSUMPTION discloses a general method of software controlled power saving mode, wherein each individual processor and I / O controller has a power down mode and is operated. The system dynamically monitors the usage of each unit dynamically, closing these units when they are not in use. The power off mode is typically implemented by controlling a regulator that generates a supply voltage, thus eliminating both active and static components of power loss. This general-mode method at the current technology level has some vulnerabilities. This method consumes some power and requires monitoring of the operating system, which cannot predict future activity. The unit may be turned on and off frequently, so the actual power savings are small.

U.S. Patent No. 5,781,062, SEMICONDUCTOR INTEGRATED CIRCUIT, is a logic that has a multi-threshold complementary metal oxide semiconductor (MTCMOS) structure that generates virtual Vdd and ground. Signal / "header-footer switch structure controlled by " U.S. Patent 5,781,062 discloses two modes of power saving control. In the first mode, during the waiting period, the header / footer switch device repeatedly conducts / non-conductions to provide leakage power to the virtual Vdd and ground to prevent loss of information in the logic. do. In the second mode, no periodic conduction interval is provided during the standby period, thereby increasing power savings by discharging the virtual Vdd line to eliminate leakage power, which is charged back to Vdd at the start of the active period. do. Turning off virtual Vdd and ground in this manner saves more power than cycle clock gating only when called for many cycles. This technique does not disclose a means of determining that some of the logic that is turned off will not be used for many cycles in the future, so that an explicitly programmed global mode is available in the prior art to control the header / footer switch. That is the only means.

Power loss in CMOS logic includes two components: active power consumed when the circuit is switched and static power or leakage power consumed each time Vdd and ground are applied to the logic. Conventional active power power control relies on clock gating to turn off the clock on a cycle-by-cycle basis when logic is not used.

In Figure 1, the MTCMOS structure used to control the leakage power of static CMOS logic 12 is shown. When the SLEEP signal is active, Vdd and ground are separated from the rest of the logic by transistors 11 and 13 so that no leakage power is consumed. Typically, the thresholds of field effect transistors (FETs) 11 and 13 in SLEEP mode are higher than the rest of the logic FETs to ensure minimum leakage power. This technique has two drawbacks: first, sizing of the FET in sleep mode is important to avoid degrading performance, and second, the logic gradually loses the stored charge when Vdd or ground is isolated. Therefore, all memory in the previously saved state is lost. When power is restored, all discharged nodes of the logic must be recharged by consuming power. Thus, SLEEP mode control must be invoked for several cycles to achieve real power savings.

Because it is difficult to predict when processor logic will be used in the future, the prior art relies on global control of the operating system to control the SLEEP mode of the MTCMOS structure. 2, a processor 22 having such a control structure is shown. The processor 22 uses the control signal SLEEP generated from the state of the sleep mode latch 24 (always powered on) to supply power by the virtual ground and the virtual Vdd controlled by the FETs 21 and 23. To be supplied. This latch 24 is set by the processor 22 via a set signal 25 and is asserted by the processor through a programmed operation when there is no work left to be done. The operating system kernel must store the state of the processor 22 needed to resume operation to some non-volatile storage (not shown) before asserting the signal 25. Some external event 26 is connected to reset of the sleep mode latch 24 to resume operation. Conceptually this is the same as the "suspend" mode with power regulator shutdown used in some computers.

Accordingly, what is needed is an apparatus and method for more effectively controlling power in a digital integrated circuit. There is also a need to control the power of the processor based on knowing the future usage of a particular hardware architecture.

The present invention relates to power control of microprocessor digital integrated circuits, and more particularly, to an apparatus and method for dynamically controlling power of a portion of a processor by inserting power control information into instructions generated by a compiler.

1 is a schematic diagram of a multi-threshold CMOS (MTCMOS) for power down logic function according to the prior art;

2 is a schematic diagram of a prior art structure having an MTCMOS structure with global sleep mode control.

3 is a schematic diagram of a processor constructed in accordance with one embodiment of the present invention, divided into portions of several independently controlled logic, each having separate MTCMOS control.

4 is a schematic diagram of a table constructed during the analysis portion of code generation of the compiler for the processor of FIG. 3 in accordance with the present invention;

5 is a block diagram / flow diagram of a system / method for a code generation portion of a compiler for generating switch control for the processor of FIG. 3 in accordance with the present invention.

6 illustrates an instruction sequence resulting from the insertion of a power map control instruction for the example of FIG. 4 in accordance with the present invention.

The microprocessor according to the invention comprises a logic circuit. The selection device is coupled to the logic circuit, which switches the logic circuit on / off based on the stored logic value. Program instructions for setting stored logic values to control the on / off state of the logic circuit based on the expected usage of the logic circuit in accordance with the instruction sequence of the microprocessor.

In another embodiment, the selection device may include a switch that provides a connection from the supply voltage to the power line of the at least one logic circuit in the on state. The selection device may include a switch that provides a connection from ground to at least one logic circuit in the on state. The microprocessor may include a register coupled to the selection device to store the stored logical value. The register is updated after a number of instruction cycles. The input table may include instruction sequences and related resources required for the logical unit, where the expected usage is determined according to the input table.

In another embodiment, the expected usage of the logical unit may include the usage of the logical device after a number of instruction cycles. The microprocessor may include an output table having a logic state corresponding to the power saving on / off state of the logic device, and the program instructions may set stored logic values to control the logic circuit in accordance with the power saving on / off state. .

Another microprocessor of the present invention includes a plurality of logic circuits divided into functional groups. The selection device is coupled to each functional group, and each selection device switches the corresponding functional group on / off based on a logic value stored in a register. The program instruction sets a logical value in the register to control the on / off state of the functional group. The compiler program generates a logical value that is set in a register based on an instruction sequence that anticipates the usage of each functional group.

The selection device may each comprise a switch providing a connection from the supply voltage to the power line of the functional group in the on state or a switch providing a connection from the ground to the power line of the functional group in the on state. The register may contain one memory location for each functional group. The register is preferably updated after a number of instruction cycles. The microprocessor may include an input table generated by the compiler program, or may include instruction sequences and related resources required for each functional group, and usage of the functional group is determined according to the input table. The usage of the functional group may include the usage of the functional group after a number of instruction cycles. The microprocessor may include an output table that includes a logic state corresponding to the power saving on / off state of the functional group.

In accordance with the present invention, a method of generating an inserted instruction sequence for controlling power to a logic circuit in a microprocessor generates an instruction sequence for controlling a functional program for the microprocessor. The instruction sequence is analyzed to determine which logic circuit is active in each instruction cycle, and a plurality of instruction cycles for each logic circuit that are deactivated after the current instruction cycle are compared with the values for each instruction cycle of the function program. . The instruction sequence is inserted to turn each logic circuit on or off depending on the comparison.

In another method, the insert instruction sequence may include programming a register with a logical value, where each logic circuit is turned on or off based on the logical value. The value of the comparison may include a number determined to provide pure power savings within the logic circuit. A program storage device readable by a machine that specifically implements a program of instructions executable by the machine may include performing the method described herein.

The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings.

The invention is explained in detail in the description of the preferred embodiment in connection with the following figures.

The present invention is a header / footer device of a microprocessor, preferably a multi-threshold complementary metal oxide semiconductor (MTCMOS), although other field effect transistor devices or other types of structures may be used. Provides control over digital integrated circuits utilizing the structure. Based on the recognition that the controlled logic will not be used in some cycles in the future, the selected header / footer device is switched off. Recognition of a request for a particular device may be extracted from a memory device, a lookout table or an instruction sequence from a compiler. Awareness of the need for this particular device is then used to turn the header / footer switch on or off. These switches may include a CMOS FET or any other switching device.

In one embodiment, the perception of the use of the device may be extracted by the compiler when instructions for the processor are generated and associated with the text of the instructions to use during its execution. In a particularly useful embodiment, a method of subdividing a logic device / circuit of a microprocessor into a plurality of power control regions that can be controlled separately, for example by its header / footer switch is used. Instructions for individually controlling power for a plurality of control regions may be generated.

One aspect of the present invention provides a microprocessor digital integrated circuit divided into a plurality of independent logic groups, for example, an MTCMOS structure that independently controls a header / footer switch, and programs the state of the switch. Each of the instructions in the instruction set architecture of the microprocessor allows control. The instruction sequence forming the program for the microprocessor may be generated by a compiler program that specifies the division of logic by the function and the minimum time that the header / footer is opened for power saving. The compiler preferably includes program logic that determines whether resources associated with any of these functions will not be used during the minimum time interval associated with that function. When groups are not used, a code generation step is provided in the program logic that inserts the instructions needed to turn off each group. Program logic is added to the compiler and execution environment to save and recover any state that will be lost by turning off the virtual Vdd and ground. Using the present invention, greater power savings are achieved than discrete clock gating and provide these savings without the negative system effect associated with invoking global sleep mode.

The elements shown in the figures may be implemented in various forms of hardware, software, or a combination thereof. Preferably, these elements are implemented in a combination of hardware and software, wired or stored on and executed on one or more suitably programmed general-purpose digital computers having a processor, memory and input / output interfaces. Referring now to the drawings, in the drawings, like reference numerals refer to the same or similar elements, and first, in FIG. 3, a schematic diagram of an example circuit 100 is shown to illustrate the invention, but the invention is not limited thereto. And other circuits, integrated circuits or semiconductor circuits.

In one embodiment of the present invention, processor 100 includes logic circuits 112, 121, 123. The functional group of logic circuits is further subdivided into specific instructions and headers and footer FETs 108, preferably groups 101 to 107 associated with MTCMOS, with individual controls (line 110) being provided for each logical group 101 to 107. (Line 110 for groups 102-106 is omitted for simplicity). Processor 100 is configured in accordance with the present invention having processor logic divided into groups of logic circuits 112 without individually controlled header / footer switches. Although part of the group 112 or the entire circuit of the group 112 includes separate header / footer control in other embodiments, this group 112 (or groups) of logic circuits is a separate MTCMOS header / group for the entire group. Does not include footer control. The seven individually controlled groups 101-107 corresponding to execution resources of a particular instruction type have individually controllable header / footer switches 108.

Some of the logic 112 without such control may actually be subdivided, while some subdivisions have power control, but the subdivisions shown in FIG. 3 are sufficient to illustrate the principles of the present invention. The invention may be applied to many other logic configurations, and the divisions of such logic circuits may be formed in accordance with standards defined by chip designers using, for example, general principles to determine operable and effective subdivisions of the circuit. .

In one embodiment, all logic associated with the current state of process 100 contained in registers 131 and 133 and other registers (not shown) in logic 112 is not powered by virtual Vdd / ground. Instead it remains "on". On the other hand, this logic may be powered by a virtual Vdd / ground controlled by a global signal as described above. However, since the state of the current processor cannot be lost, this virtual Vdd / ground cannot be separated from the actual Vdd / ground unless the processor state is stored in some nonvolatile storage. The nonvolatile storage device and the operating system support device are required for state storage and are returned to the global power saving mode as described above with reference to FIG. 2. An alternative to this overall power control is known and therefore not shown in FIG. 3.

The processor 100 may include a plurality of other devices. As shown in FIG. 3, the integer unit 121 is, for example, an addition logic 101, an integer shifter logic 102, an integer logic unit 103, an integer multiplier logic 104 and an integer. It contains integer logic such as register 131. Floating point unit 123 includes floating point logic such as, for example, floating point adder logic 105, floating point divider logic 106, floating point multiplier logic 107, and floating point register 133.

Group 112 includes a memory queue and bus interface unit 130 that receives address information and data as inputs, and the data is stored at addressed locations in cache array 132. Cache tag 134 may be applied to data stored in cache array 132 to identify information present in cache array 132. The instruction queue and dispatch logic unit 136 receives instructions (e.g., special purpose unit instructions, floating point instructions, and / or integer instructions), and processes the appropriate execution resources (e.g., special purpose register units) for processing. 150, the floating point unit 123, and the integer unit 121. The instruction fetch unit 138 fetches the next instruction to be executed from the next sequential instruction address or branch target address. Branch unit 140 is provided with any branch instructions fetched by instruction fetch unit 138 so that the next instruction to be executed next to the branch is the next sequential instruction or is fetched from the information calculated from the information specified by the branch instruction. Determines whether the instruction was taken from a branch target. The load / store unit 142 executes all load storage instructions and executes special purpose registers in the cache array 132 and the integer register 131, the floating point register 133, and the special purpose register unit 150, for example. Provide a data transfer interface between registers 152.

In accordance with the present invention, control for each logical group 101-107 is provided by a bit in special purpose unit 150 including a power map register 152. The value in register 152 is set by a special immediate instruction that loads the value from the instruction text into register 152. These instructions are inserted by the code generator of the compiler described below.

Referring to FIG. 4, during the end of the code assignment phase of compilation, the compiler constructs a table 200 with the information shown in FIG. 4. Each column of the table 200 corresponds to a group of logic (groups labeled 101-107 in FIG. 3) with individually controlled header / footer FETs 108 (see FIG. 3), and each row 201 is Corresponds to the instructions indicated by 1 to 10 in the order of execution. A check mark is placed in a cell of table 200 to indicate when the resource (eg, logical group) is being used by the current corresponding instruction. The further the distance in each column between the check marks, the longer the logic group 101-107 may be powered off. In a preferred embodiment, the compiler preferably rearranges the code to maximize the distance between the check marks in each column in accordance with the compiler's optimization instructions. Once the table 200 is populated, the method shown in FIG. 5 is executed to generate a " Load Power Map Register " instruction with appropriate immediate data values. The method of FIG. 5 is preferably used in software that requires as input a number of cycles considered to be the minimum number of cycles in which the unit is shut off before actual power savings are made.

Referring to FIG. 5, for example, the maximum number of cycles in which the unit is shut off before actual power savings are made is 5 cycles (instruction). The input table 300 is composed of the same number of rows and columns as the table 200 of FIG. 4 with each check mark in FIG. 4 indicated by a logical "1" value in the input table 300. The output table 301 has the same number of rows and columns as the input table 300, and switches 108 (see FIG. 3) for the logic corresponding to that column (zero or more of the groups 101-107). Has a value of "1" when the control signal to the furnace is set to NOT SLEEP (ie, powered on logic). At block 304, the method is initialized and begins at the first row of input table 300.

The method estimates the minimum number of cycles required for power savings (in this example, the minimum number of cycles (or instructions) is 5) to see if the unit can be powered down, and outputs if power can be cut off. The corresponding cell in the table 301 is set to "1". This is done by examining each cell in the first row of the input table 300 at block 306. The current cell value is represented by "C" and may have a value of "1" or "0". The value of the previous row in the output table is represented by "P". All 1 preceding rows in the output table 301 may be used for the first row considered by the method. The determination of instruction activity is now determined by a logical OR operation on the minimum number of rows corresponding to the minimum number of cycles (eg, 5). The result of this logical OR operation is represented by N.

At block 308, if C = 1, the program path proceeds to block 310. Otherwise, the program path proceeds to block 312. At block 310, the group or logic device corresponding to the cell with C = 1 remains on. Therefore, the corresponding position in the output table 301 is set to "1". In block 312, a logic unit or group (e.g., one of groups 101-107) is not used within five cycles (C = 0, N = 0) or is used within five cycles but power is already If blocked (C = 0, P = 0), the group or logic unit corresponding to that cell is turned off until needed. If these conditions exist, "0" is located at the corresponding position in the output table 301.

In block 314, a check is made to see if all rows have been completed. If all rows do not end, the program path proceeds to the next row in block 316 and returns to block 306. Otherwise, the program path proceeds to block 318.

At block 318, insertion of the power control instruction LOAD POWER MAP is made. The number of inserted LOAD POWER MAP (LPM) instructions represents the balance between power savings of the turn-off of some of the units (e.g., 101-107) and wasted power due to new instructions and instruction space. . In extreme cases, a new power control value can be loaded every cycle, thus doubling the number of instructions. In other cases, power control instructions may be made every x cycles. Thus, the maximum number of power control instructions per unit of code is preferably maintained, and the actual value of x may be set in consideration of the total power consumed during the execution of the inserted LPM instruction and the total size of the program by the presence or absence of the LPM instruction. Can be. Each embedded LPM instruction may degrade program performance because the instruction occupies one execution cycle that may be used for other instructions, and may consume power during fetching and execution. The total power consumed to execute the LPM instruction should be kept below the power saved by turning off the virtual Vdd / ground of units 101-107 (see FIG. 3).

Referring to FIG. 6, an example for implementing the table 200 of FIG. 4 with power control instructions added in accordance with the output table 301 of FIG. 5 is provided. In this example, their output table values are turned off in cycles from one to zero. As shown in FIG. 6, the instruction sequence includes a LoadPowerMap (LPM) instruction and includes, within the instruction, an immediate digital data field of, for example, 1111000, which translates this digital word from the power table register 301. Loading to 152 enables or disables nothing or enables or disables some or all logic units / groups 101-107. In this example, digital word 1111000 enables units 101-104 and disables or keeps units 105-107 off. Next, instruction 1 is performed, followed by other LPM instructions 0111000, instructions 2 and 3, LPM instruction 0011000, and instructions 4 and 5. The LPM instruction inserted between instructions 5 and 6 then turns on the additional unit as soon as one cycle to avoid inserting another power mask instruction in the next cycle. Instructions 6, 7, 8LPM 1000110, 9, and 10 are then performed.

Correct operation of the program actively controlling the power map register 152 with the LPM instruction ensures that the correct state of the register is maintained across the program interrupt. The processing of the state of the power map register 152 is preferably integrated with the interrupt processing program. When a program interrupt occurs, always as a result of an external event, the currently running program with the associated power map register state is stopped and the interrupt handling program is called. The interrupt handling program first ensures that all execution resources required by the program are powered up by setting a value in the power map register 152 that is appropriate to the program's needs. The program is delayed until the LPM instruction is executed and the state of the power of the execution unit corresponds to the state loaded in the register 152. This delay is due to the general pipeline delay between fetching an instruction (in this case LPM) and its execution (i.e. turning on any off unit that may be needed).

In one embodiment, the state of the power map register 152 of the interrupted program may be stored before loading a new value corresponding to the execution resource request of the interrupt handler program. This allows the interrupt handler to restore its value to the power map register just before resuming the interrupted program. However, this is not required for correct program operation.

On the other hand, the interrupted program can be restarted with all "1" values in the power mask register with some loss of power savings. The next LPM instruction, executed in the restarted program, sets the power mask register to the correct value.

The present invention described above provides a device and compiler method for a single issue, i.e., an in-order processor. The compiler described herein assumes that instructions are executed in terms of machine concepts, and the compiler performs the analysis on that basis. However, the present invention is also applicable to multi-issue, out of order machines. This may be implemented by using additional hardware to the issue logic of such a machine to analyze the mask of the LPM instruction. This logic is similar to the logic required for scoreboard register usage, and the addition of logic reduces power savings accordingly.

Although preferred embodiments for controlling power of a processor using a hardware structure controlled by a compiler having a cumulative instruction profile have been described (these are illustrative only and not limiting), variations and modifications may be made by those skilled in the art from the foregoing description. Could be done. Accordingly, modifications may be made to certain embodiments of the invention within the spirit and scope of the invention as described by the appended claims. Although the present invention has been described by the detailed description required by the patent law, matters claimed and protected by a patent certificate are disclosed in the appended claims.

Claims (20)

In a microprocessor, At least one logic circuit, A selection device coupled to the at least one logic circuit to switch the at least one logic circuit on / off based on a stored logic value; A program instruction for setting the stored logic value to control the on / off state of the at least one logic circuit based on an expected usage amount of the at least one logic circuit in accordance with the instruction sequence of the microprocessor Microprocessor comprising a. The method of claim 1, The selection device includes a switch to provide a connection from a supply voltage to a power line of the at least one logic circuit in an on state. The method of claim 1, The selection device includes a switch to provide a connection from ground to a power line of the at least one logic circuit in an on state. The method of claim 1, And a register coupled to the selection device to store the stored logical value. The method of claim 4, wherein The register is updated after a number of instruction cycles. The method of claim 1, And an input table comprising an instruction sequence and associated resources required for the at least one logic circuit, wherein the estimated usage is determined according to the input table. The method of claim 1, The expected usage of the at least one logic circuit comprises the usage of the at least one logic circuit after a number of instruction cycles. The method of claim 1, An output table including a logic state corresponding to a power saving on / off state of the at least one logic circuit, The program instruction sets the stored logic value to control the at least one logic circuit in accordance with the power saving on / off state. Microprocessor. In a microprocessor, A plurality of logic circuits divided into functional groups, A selection device coupled to each of the functional groups, for switching the corresponding functional group to an on / off state based on a logical value stored in a register; Program instructions for setting the logical value in the register to control an on / off state of the functional group; A compiler program that generates the logical value set in the register based on an instruction sequence that anticipates usage of each functional group Microprocessor comprising a. The method of claim 9, The selection device each including a switch to provide a connection from a supply voltage to a power line of the functional group in an on state. The method of claim 9, The selection device each including a switch that provides a connection from ground to the power line of the functional group in an on state. The method of claim 9, Said register containing one memory location for each functional group. The method of claim 9, The register is updated after a number of instruction cycles. The method of claim 9, And an input table generated by the compiler program and including an instruction sequence and related resources required for each functional group, wherein usage of the functional group is determined according to the input table. The method of claim 9, The usage of the functional group comprises the usage of the functional group after a plurality of instruction cycles. The method of claim 9, And an output table including a logic state corresponding to a power saving on / off state of the functional group. A method of generating an inserted instruction sequence for controlling power to a logic circuit in a microprocessor, the method comprising: Generating an instruction sequence for controlling a functional program for the microprocessor; Analyzing the instruction sequence to determine which of the logic circuits is active for each instruction cycle; Comparing a number of instruction cycles, each logic circuit being inactive after a current instruction cycle, with a value for each instruction cycle of the function program; Inserting an instruction sequence to turn each of said logic circuits on or off based on said comparing step Instruction sequence generation method comprising a. The method of claim 17, The instruction sequence inserting step includes programming a register to a logic value, wherein each of said logic circuits is turned on or off based on said logic value. The method of claim 17, And wherein the value of the comparing step comprises a number determined to provide pure power savings in the logic circuit. A program storage device readable by a machine that actually implements a program of instructions executable by the machine to perform the method steps of claim 17.