JP2000330762A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption in an arithmetic and logic circuit constituting a semiconductor integrated circuit. SOLUTION: This semiconductor integrated circuit which has a program memory where a plurality of instruction codes are stored, an instruction register which receives an instruction code outputted from the program memory and an arithmetic and logic which executes prescribed processing in accordance with an output from the instruction register and includes an arithmetic and logic device 11 and an adder-subtracter 12 is provided with a decoder 17 which outputs a control signal showing which operates between the arithmetic and logic device and the adder-subtracter by decoding a part of an instruction code held by the instruction register, demultiplexers 18 and 19 that control which input data holding circuits 13 and 14 or 15 and 16 input data Ain and Bin to the arithmetic and logic circuit are inputted to between the arithmetic and logic device and the adder-subtracter in accordance with an output control signal from the decoder 17 and a multiplexer 20 that controls which output between the arithmetic and logic device and the adder-subtracter is outputted as output data Out of the arithmetic and logic circuit in accordance with the output control signal from the decoder 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for configuring a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As a semiconductor integrated circuit, a semiconductor integrated circuit having an arithmetic and logic operation circuit (ALU) including at least one adder / subtracter and one or more logical operation units will be considered. At this time, in the prior art, as shown in FIG. 3, both instructions (the logical operation unit 31 and the addition / subtraction unit 3)
Usually, the input data Ain and Bin are held in the input data holding circuits (FF) 33 to 36 of 2). That is, in the arithmetic and logic operation circuit, the circuits (FFs 33 and 34 or FFs 35 and 36) which do not need to operate originally operate. Reference numeral 37 denotes a multiplexer for switching the output.
The output from 1 or 32 is output as output data Out.

For example, consider the case where an integrated circuit executes a simple addition instruction. At this time, if a flag or the like is required, the operation of the logical operation unit 31 is necessary. However, if a flag or the like is not required, only the adder / subtractor 32 needs to operate.
The logical operation unit 31 does not need to operate. Nevertheless, the input data holding circuit (FF) 3 of the logical operator 31
Data was also stored in 3,34. If the input held data changes, the unnecessary portion of the circuit operates. As a result, wasteful power is consumed. In particular, as in recent years, when the data width is steadily increasing, the wasted power consumed by the arithmetic and logic operation circuit having a large scale in proportion to the data width is not negligible.

In view of this problem, Japanese Patent Application Laid-Open No. 4-127210 discloses a "low power consumption processor" as a technique for reducing the power consumption of an integrated circuit from the viewpoint of preventing unnecessary circuits from operating. This technique is used when decoding instructions.
A block in the integrated circuit which requires an operation is determined, and supply of a clock signal to the unnecessary block is stopped. As a result, wasteful power consumption can be eliminated and low power consumption can be achieved. However, the problem with this method is that an effect cannot be obtained for an arithmetic logic circuit that operates every cycle. Is a point.

As a technique for reducing power consumption from the viewpoint of suppressing useless changes in data, Japanese Patent Application Laid-Open No. H5-25-2
There is a 65706 “arithmetic unit”. This technique is intended for a circuit having a repetitive structure of a register and an arithmetic unit, such as that found in pipeline control of a processor. According to this technique, a reset signal is input to all blocks in a circuit, thereby suppressing the process of clearing data once and updating it again, thereby reducing the data change probability. As a result, the transition probability of data is reduced, and power consumption is reduced. The problem with this method is that it can only be applied to circuits with a pipeline structure, and is not versatile.

[0006]

As described in the section of the prior art, the two prior arts have the following problems, respectively.

The first prior art, which is a technique for stopping the supply of a clock signal to a block that does not need to operate, is effective when reducing power consumption in large units. However, in this method, if the clock signal is stopped in an extremely small unit, the area and power consumption due to the clock distribution are greatly increased, and the area and power consumption due to the decoder for the control cannot be ignored. . Further, as described above, it is impossible to reduce the power consumption of an arithmetic and logic operation circuit that operates every cycle in an integrated circuit.

Also, the second prior art is not general-purpose because it can be applied only to circuits having a pipeline structure.

An object of the present invention is to provide a technique for reducing power consumption in a small range of an arithmetic and logic operation circuit, as compared with the prior art. However, the ratio of the power consumption of the arithmetic and logic operation circuit to the power consumption of the entire circuit is large as described later, and the low power consumption technology specialized in this portion requires the power consumption of the entire integrated circuit. It is very effective. Further, as the data width increases, as in recent years, the scale of the arithmetic and logic operation circuit also increases, and the effect of reducing power consumption also increases.

[0010]

According to the present invention, there is provided a semiconductor integrated circuit comprising: a program memory storing a plurality of instruction codes; an instruction register receiving, storing, and outputting the instruction codes output from the program memory. An arithmetic and logic circuit including at least one adder / subtracter and at least one logical operator for executing a predetermined process in accordance with the output from the instruction register. A decoder that outputs a control signal indicating which of the adder / subtractor and the logical operation unit operates by decoding a part of the instruction code, and the arithmetic and logical operation according to an output control signal from the decoder. Input control means for controlling which of the adder / subtractor and the logical operator is input to the circuit;
Output control means for controlling which output of the adder / subtractor or the logical operation unit is connected to the output of the arithmetic and logic operation circuit in accordance with an output control signal from the decoder. Things.

Further, the semiconductor integrated circuit of the present invention is characterized in that in the semiconductor integrated circuit, a demultiplexer is provided as the input control means, and a multiplexer is provided as the output control means. is there.

Further, in the semiconductor integrated circuit according to the present invention, in the semiconductor integrated circuit, an input data holding circuit is provided between the demultiplexer, the adder / subtractor, and the logical operation unit. After the input data input through the data holding circuit is held in the data holding circuit, the data is input to the adder / subtractor or the logical operation unit.

According to the semiconductor integrated circuit of the present invention,
By decoding a part of the instruction code held in the instruction register by the newly provided decoder, a control signal indicating which of the adder / subtractor and the logical operation unit operates is output. This decoding operation is to determine whether the instruction code requires an operation of an adder / subtractor or a logical operation unit by looking at an appropriate part in the instruction code, that is, the bit data of that part. In this decoding operation, a control signal indicating which of the adder / subtractor and the logical operation unit operates is output. Usually, in a well-designed instruction set, it is sufficient for this decoder to have a few bits of input. In accordance with an output control signal from the decoder, a demultiplexer for controlling whether to input the input data to the arithmetic and logic operation circuit to an adder / subtractor or a logical operation unit is controlled, and one of the operation units is controlled. Input data is input only to the input data holding circuit of FIG. That is, data input to the input data holding circuit of the other arithmetic unit is not performed. Further, in accordance with a control signal from the decoder, a multiplexer for controlling which output of the adder / subtractor or the logical operation unit is connected to the output of the arithmetic and logic operation circuit is controlled, and the selected side (data input) is controlled. The output data from the computing unit on the side where is performed is output as the output of the arithmetic and logic operation circuit.

According to the semiconductor integrated circuit of the present invention, when there are many instructions that operate only one of the adder / subtracter and the logical operation unit, the effect of reducing the power consumption is great. In recent years, in general, among the total power consumption of integrated circuits,
The ratio of the power consumption of the arithmetic logic operation circuit has become very large. The power consumption in the arithmetic and logic operation circuit is going to increase more and more in the future due to the following factors.

1. 1. Increase in data width (shift to 32 bit width or more) Widespread instruction-level parallelism by dynamic scheduling, pipeline processing including superscalar and its extended version. A circuit having these functions includes a plurality of arithmetic and logic operation circuits.

3. Instruction-level parallel processing with static scheduling. In the VLIW method and its extended version, parallel execution is performed by extracting a part that can be executed in parallel statically by a compiler. Even in such a case, the integrated circuit includes a plurality of arithmetic logic operation circuits.

By implementing the present invention, it is possible to perform fine control at the instruction level with respect to the increase in power consumption in such an arithmetic and logic operation circuit. As a result, the power consumption is greatly reduced. It is possible to achieve a significant reduction.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 1A is a configuration diagram in a state where a logical operation unit is operating. FIG. 4B is a configuration diagram in a state where the adder / subtracter side is operating.

In the drawing, reference numeral 11 denotes a logic operation unit, 12 denotes an addition / subtraction unit, 13 and 14 denote input data holding circuits (FF) of the logic operation unit 11, and 15 and 16 denote input data holding circuits of the addition / subtraction unit 12. (FF). The logical operation unit 11, the adder / subtractor 12, and the input data holding circuits 13-1
6 constitutes an arithmetic and logic operation circuit. 1
Reference numeral 7 denotes a decoder which is a feature of the present invention, and is a program memory (not shown) for storing a plurality of instruction codes.
By decoding a predetermined part of the instruction code read from the instruction register and held in an instruction register (not shown), a control signal indicating which of the logical operation unit 11 and the adder / subtractor 12 operates is output. Things. 18 and 19
Is based on an output control signal from the decoder 17,
A demultiplexer for controlling which side of the logical operation unit 11 or the adder / subtractor 12 receives the input data Ain and Bin to the arithmetic and logic operation circuit.
in and Bin are input to and held by the input data holding circuits 13, 14 or 15 and 16 of the logical operation unit 11 or the adder / subtractor 12 selected by the demultiplexers 18 and 19, respectively. Alternatively, it is input to the adder / subtractor 12. Also, 20 is the logical operation unit 11 according to the output control signal from the decoder 17.
And a multiplexer that controls which output of the adder / subtractor 12 is connected to the output of the arithmetic and logic operation circuit. The output data on the side selected by the multiplexer 20 is output data of the arithmetic and logic operation circuit as Out data What is output.

As described above, FIG. 1A is a state diagram when the logical operation unit 11 operates, and the instruction code stored in the instruction register requires only the operation of the logical operation unit 11. It is a state diagram in case of an instruction. in this case,
A control signal indicating that the logical operation unit 11 operates is output from the decoder 17, and in accordance with the control signal, the logical operation unit side is selected in the demultiplexers 18, 19 and the multiplexer 20, and the input data Ain And B
In is input to and held in input data holding circuits 13 and 14 of the logical operation unit 11 via demultiplexers 18 and 19, and the logical operation unit 11 based on an output from the holding circuit.
Is output as output data Out via the multiplexer 20. Arrows indicate the flow of data. In this case, no data is input to the input data holding circuits 15 and 16 of the adder / subtracter 12, and the input data hold circuits 15 and 16 continue to hold the data of the previous cycle, and the adder / subtractor does not operate at all. .
Therefore, useless power consumption at the adder / subtractor side is not performed at all, and low power consumption in the arithmetic and logic operation circuit is achieved.

On the other hand, FIG. 1B is a state diagram when the adder / subtractor 12 operates, and shows a state where the instruction code held in the instruction register is an instruction requiring only the operation of the adder / subtractor 12. FIG. In this case, a control signal indicating that the adder / subtractor 12 operates is output from the decoder 17, and the demultiplexers 18, 1
9 and the multiplexer 20, the adder / subtractor side is selected, and the input data Ain and Bin are input to and held by the input data holding circuits 15 and 16 of the adder / subtractor 12 via the demultiplexers 18 and 19. The operation result in the adder / subtracter 12 based on the output from the data holding circuit is output via the multiplexer 20 to the output data Ou.
Output as t. Arrows indicate the flow of data. In this case, no data is input to the input data holding circuits 13 and 14 of the logical operation unit 11, and the input holding circuits 13 and 14 continue to hold the data of the previous cycle, and the logical operation unit does not operate at all. do not do. Accordingly, no unnecessary power consumption is performed on the logical operation unit side, and low power consumption in the arithmetic and logic operation circuit is achieved.

FIG. 1 shows a case where the logical operation unit 11 and the adder / subtractor 12 operate exclusively, but as shown in FIG. 2, the circuit configuration of FIG. Therefore, the present invention can be applied to a case where the operation of the logical operation unit 11 and the operation of the adder / subtractor 12 based on the same input data are executed successively. FIG. 2 shows a case where the addition and subtraction and the logical operation based on the same input data are continuously executed over two cycles.

FIG. 2A shows a state in which the adder / subtracter 12 operates in the first cycle. In this cycle, the decoder 17 outputs the logical operation unit. 11 and a control signal indicating that both the adder / subtractor 12 operate, and according to the control signal, the demultiplexers 18 and 19 output the input data Ain, B
in is the input data holding circuits 13, 14 and 1
The input data is set in a state where the input data is input to the input data storage circuits 5 and 16, and the input data is stored in both input data storage circuits. The multiplexer 20 on the output side is set in a state of selecting the adder / subtractor side. In this cycle, the adder / subtracter 12 operates, and the operation result is output via the multiplexer 20 as output data out. This completes the operation of the first cycle.

Next, FIG. 2B shows the state when the logical operation unit 11 operates in the second cycle. Multiplexer 20 according to the output control signal of
Is switched to a state of selecting the logical operation unit 11 side.
In this cycle, the logical operation unit 11 operates, and the operation result is output as output data Out via the multiplexer 20. In the figure, the demultiplexers 18 and 19 are also controlled by the output control signal from the decoder 17 in the second cycle.
Is set to a state where input data Ain and Bin are input to both input data holding circuits 13, 14, 15, and 16. In the first cycle, the same data is already input to the logical operation unit 11. Input data holding circuits 13 and 14
, And is held, so there is no need to re-input, and the data Ai
The configuration may be such that the connection between n and Bin and the input data holding circuits 13 to 16 is cut off.

[0026]

As described above in detail, according to the present invention, the power consumption of the arithmetic and logic operation circuit can be reduced only by adding a circuit having a simple structure. It is possible to provide a simple semiconductor integrated circuit. The effect of the present invention is particularly large when there are many instructions that operate only one of the adder / subtracter and the logical operation unit. In such a case, the power consumption can be significantly reduced. Can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.
And (b) is a configuration diagram when the adder / subtracter 12 operates.

FIG. 2 is a configuration diagram showing a circuit state in a case where addition and subtraction based on the same input data and a logical operation are continuously performed over two cycles in the embodiment;
FIG. 3 is a configuration diagram showing a circuit state when addition and subtraction are performed in a first cycle, and FIG. 4B is a configuration diagram showing a circuit state when a logical operation is performed in a second cycle. is there.

FIG. 3 is a block diagram showing a configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 Reference Signs List 11 Logical operation unit 12 Adder / subtractor 13-16 Input data holding circuit 17 Decoder 18, 19 Demultiplexer 20 Multiplexer Ain, Bin Input data Out Output data

Claims (3)

[Claims] 1. A program memory in which a plurality of instruction codes are stored, an instruction register for receiving, holding and outputting the instruction code output from the program memory, and a predetermined register corresponding to an output from the instruction register. A semiconductor integrated circuit having an arithmetic and logic operation circuit including at least one adder / subtracter and at least one logical operation unit for executing processing, by decoding a part of the instruction code held in the instruction register, A decoder that outputs a control signal indicating which of the adder / subtracter and the logical operation unit operates;
An input control means for controlling which of the adder / subtractor and the logic operator inputs the input data to the arithmetic and logic operation circuit in accordance with an output control signal from the decoder; and an output control signal from the decoder. And an output control means for controlling which output of the adder / subtracter or the logical operation unit is connected to the output of the arithmetic and logic operation circuit. 2. The semiconductor integrated circuit according to claim 1, wherein a demultiplexer is provided as said input control means, and a multiplexer is provided as said output control means. 3. An input data holding circuit is provided between the demultiplexer, the adder / subtracter, and the logical operation unit, and input data input via the demultiplexer is held in the data holding circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the signal is input to the adder / subtractor or the logical operation unit after the operation.