KR20040100510A - Test patern forming method in semiconductor process - Google Patents

Test patern forming method in semiconductor process Download PDF

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Publication number
KR20040100510A
KR20040100510A KR1020030032897A KR20030032897A KR20040100510A KR 20040100510 A KR20040100510 A KR 20040100510A KR 1020030032897 A KR1020030032897 A KR 1020030032897A KR 20030032897 A KR20030032897 A KR 20030032897A KR 20040100510 A KR20040100510 A KR 20040100510A
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South Korea
Prior art keywords
pattern
resistance pattern
forming
test
small
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KR1020030032897A
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Korean (ko)
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김종수
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주식회사 하이닉스반도체
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Priority to KR1020030032897A priority Critical patent/KR20040100510A/en
Publication of KR20040100510A publication Critical patent/KR20040100510A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Abstract

PURPOSE: A method of forming a semiconductor test pattern is provided to perform smoothly a corresponding test without the degradation of a small resistive pattern and to secure the reliability of the test by forming thickly a connection line between the small resistive pattern and a large resistive pattern. CONSTITUTION: A plurality of pads(34,36,38,40,42,44) are arrayed to test a small resistive pattern(30) and a large resistive pattern(32). A connection line(46) is formed between at least one out of the pads and a withdrawal position of the large resistive pattern. The width of the connection line is larger than that of the large resistive pattern.

Description

반도체 테스트 패턴 형성 방법{Test patern forming method in semiconductor process}Test pattern forming method in semiconductor process

본 발명은 반도체 테스트 패턴 형성 방법에 관한 것으로서, 보다 상세하게는 켈빈 패턴(Kelvin Pattern)을 사용하여 테스트 패턴을 형성함에 있어서 큰 패턴 저항과 작은 패턴 저항에 공유되는 패드들의 연결선을 큰 패턴으로 형성시킴으로써 정확한 전류 측정을 구현하는 기술에 관한 것이다.The present invention relates to a method for forming a semiconductor test pattern, and more particularly, in forming a test pattern using a Kelvin pattern, by forming connection lines of pads shared by a large pattern resistance and a small pattern resistance in a large pattern. The present invention relates to a technique for implementing accurate current measurement.

통상, 반도체 제조 공정은 다양한 단위 공정들을 포함하며, 이들 공정에 대한 평가 방법 중 시트 저항을 측정하는 것이 포함된다.Typically, semiconductor manufacturing processes include various unit processes, and measuring sheet resistance is one of evaluation methods for these processes.

종래의 시트 저항의 패턴은 도 1과 같은 일반 저항 패턴(1)의 양쪽에패드(2)를 형성하는 형태를 이룬다. 도 1과 같은 저항의 형태를 일명 도그 본 저항(Dog Bone Resister)이라고 한다.The conventional sheet resistance pattern forms a pad 2 on both sides of the general resistance pattern 1 as shown in FIG. 1. The shape of the resistor as shown in FIG. 1 is called a dog bone resistor.

도 1의 저항 패턴은 전압을 인가하고 전류를 측정하기 위해서 한쪽 단자를 분리해야하는 불편함이 있다. 또한 큰 패턴의 저항을 형성하는 경우에는 패턴을 만들 공간이 부족하다.The resistance pattern of FIG. 1 is inconvenient to separate one terminal in order to apply voltage and measure current. In addition, when forming a large pattern of resistance, there is insufficient space to create a pattern.

따라서, 상기한 문제점을 해결하기 위하여 도 2와 같은 켈빈 패턴이 사용된다. 켈밴 패턴은 어레이(Array) 식으로 패드를 구성하여 면적이 줄어드는 효과가 있다.Therefore, the Kelvin pattern as shown in FIG. 2 is used to solve the above problem. The Kelvan pattern has the effect of reducing the area by forming pads in an array manner.

도 2에는 작은 저항 패턴(10)과 큰 저항 패턴(12)이 구성된다. 도 2의 테스트 패턴은 하나의 저항 패턴에 대하여 패드를 4개 사용한다. 즉, 한 쌍의 패드를 이용하여 전류를 공급하고, 다른 한 쌍의 패드를 이용하여 전압을 측정하여 저항값을 계측한다.2, the small resistance pattern 10 and the large resistance pattern 12 are comprised. The test pattern of FIG. 2 uses four pads for one resistance pattern. That is, current is supplied using a pair of pads, and voltage is measured using a pair of pads to measure resistance values.

도 2에는 작은 저항 패턴(10)과 큰 저항 패턴(12)의 저항을 측정하기 위하여 이용되는 패드들(14, 16, 18, 20, 22, 24)이 어레이 식으로 형성된다.In FIG. 2, pads 14, 16, 18, 20, 22, and 24 used to measure the resistance of the small resistance pattern 10 and the large resistance pattern 12 are formed in an array manner.

도 2의 경우 작은 저항 패턴(10)과 큰 저항 패턴(12) 사이가 연결 배선으로 연결되며, 이 연결 배선에 접속된 패드(18, 20)는 공유된다.In the case of FIG. 2, the small resistance pattern 10 and the large resistance pattern 12 are connected by connection wiring, and the pads 18 and 20 connected to the connection wiring are shared.

이 경우, 작은 저항 패턴(10) 쪽의 패드를 큰 패턴 저항(1b)의 패드로 사용함으로써 작은 저항 패턴(10)이 취약해지거나 패턴이 끊어지면 큰 저항 패턴(12)이 동시에 측정되지 않거나 그대로 반영되는 현상이 발생된다.In this case, when the pad of the small resistance pattern 10 is used as the pad of the large pattern resistance 1b, when the small resistance pattern 10 becomes weak or the pattern is broken, the large resistance pattern 12 is not measured at the same time or remains as it is. Reflected phenomenon occurs.

그러므로, 종래의 테스트 패턴은 작은 저항 패턴이 취약해져서 같이 묶여진패드에 의하여 큰 패턴 또한 측정이 안되는 문제점이 있다.Therefore, the conventional test pattern has a problem in that a small resistance pattern is vulnerable so that a large pattern can not be measured by the pads bundled together.

본 발명의 목적은 테스트 패턴을 형성함에 있어서 작은 저항 패턴과 큰 저항 패턴이 공존할 때 작은 저항 패턴과 큰 저항 패턴 사이의 연결 배선을 큰 저항 패턴을 이루는 배선 이상의 두께가 되도록 형성함에 있다.SUMMARY OF THE INVENTION An object of the present invention is to form a connection wiring between a small resistance pattern and a large resistance pattern to have a thickness greater than a wiring forming a large resistance pattern when the small resistance pattern and the large resistance pattern coexist in forming the test pattern.

도 1은 종래의 반도체 테스트 패턴 형성 방법을 설명하는 레이아웃도1 is a layout illustrating a conventional method for forming a semiconductor test pattern.

도 2는 종래의 켈빈 패턴을 사용한 반도체 테스트 패턴 형성 방법을 설명하는 레이아웃도2 is a layout diagram illustrating a method for forming a semiconductor test pattern using a conventional Kelvin pattern.

도 3은 본 발명에 따른 반도체 테스트 패턴 형성 방법을 설명하는 레이아웃도3 is a layout for explaining a method for forming a semiconductor test pattern according to the present invention.

본 발명에 따른 반도체 테스트 패턴 형성 방법은, 작은 저항 패턴과 큰 저항 패턴을 형성하고, 이들을 테스트 하기 위한 패드들을 어레이 식으로 형성하고, 상기 작은 저항 패턴과 큰 저항 패턴 사이에 형성된 최소한 하나 이상의 패드들과 상기 큰 저항 패턴의 인출 위치 사이에 연결 배선을 형성하되 상기 연결 배선은 폭이 상기 큰 저항 패턴을 이루는 패턴의 폭 이상으로 형성한다.The semiconductor test pattern forming method according to the present invention comprises forming a small resistance pattern and a large resistance pattern, forming pads for testing them in an array manner, and at least one or more pads formed between the small resistance pattern and the large resistance pattern. And a connection line between the lead-out position of the large resistance pattern and the connection wiring is formed to have a width greater than or equal to the width of the pattern forming the large resistance pattern.

이하, 본 발명에 따른 반도체 테스트 패턴 형성 방법의 바람직한 실시예에 대하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of a method for forming a semiconductor test pattern according to the present invention will be described in detail with reference to the accompanying drawings.

본 발명에 따른 실시예가 도 3에 개시되고, 도 3을 참조하면 작은 저항 패턴(30)과 큰 저항 패턴(32)이 형성되고, 패드들(34, 36, 38, 40, 42, 44)이 어레이 식으로 배치된다.An embodiment according to the present invention is disclosed in FIG. 3, referring to FIG. 3, a small resistance pattern 30 and a large resistance pattern 32 are formed, and pads 34, 36, 38, 40, 42, 44 are formed. Arranged in an array manner.

작은 저항 패턴(30)의 일측에는 패드(34, 36)가 병렬로 연결된다. 그리고, 작은 저항 패턴(30)과 큰 저항 패턴(32) 사이는 연결 배선(46)으로 연결되며, 연결 배선(46)에는 패드(38, 40)가 병렬로 연결된다. 그리고, 큰 저항 패턴(32)의 다른 일측에는 패드(42, 44)가 연결된다.Pads 34 and 36 are connected in parallel to one side of the small resistance pattern 30. The small resistance pattern 30 and the large resistance pattern 32 are connected to each other by a connection line 46, and pads 38 and 40 are connected in parallel to the connection line 46. The pads 42 and 44 are connected to the other side of the large resistance pattern 32.

작은 저항 패턴(30)을 이루는 패턴은 그 폭이 큰 저항 패턴(32)을 이루는 패턴보다 작다. 그리고, 연결 배선(46)은 큰 저항 패턴(32)로부터 인출되는 지점부터 패드(38) 및 패드(40)에 접속되는 지점까지 그 폭이 큰 저항 패턴(32)의 폭보다 같거나 크게 형성된다.The pattern constituting the small resistance pattern 30 is smaller than the pattern constituting the large resistance pattern 32. The connecting wiring 46 is formed to be equal to or larger than the width of the large resistance pattern 32 from the point drawn out from the large resistance pattern 32 to the point connected to the pad 38 and the pad 40. .

그러므로, 도 3의 실시예로써 작은 저항 패턴(30) 쪽의 패드를 큰 패턴 저항(40)의 패드로 사용하여도, 작은 저항 패턴(30)이 취약해지거나 끊어지는 현상이 발생되지 않는다.Therefore, even when the pad on the side of the small resistance pattern 30 is used as the pad of the large pattern resistor 40 in the embodiment of FIG. 3, the phenomenon that the small resistance pattern 30 becomes weak or broken does not occur.

그러므로, 작은 저항 패턴(30)을 큰 저항 패턴(32)과 동시에 측정할 수 있다.Therefore, the small resistance pattern 30 can be measured simultaneously with the large resistance pattern 32.

아울러, 패드가 형성된 층과 연결 배선이 형성된 층 간의 전기적 연결을 위한 컨택 플러그의 최소 폭은 해당 패턴 폭의 반 이하로 형성됨이 바람직하다.In addition, the minimum width of the contact plug for electrical connection between the pad-formed layer and the layer on which the connection wiring is formed is preferably formed to be less than half of the width of the corresponding pattern.

본 발명은 반도체 공정 평가를 위한 테스트 패턴 측정시 작은 저항 패턴 쪽의 패드를 큰 패턴 저항의 패드로 사용하여도 작은 저항 패턴이 취약해지거나 끊어지는 현상해소될 수 있으므로 테스트가 원활히 수행될 수 있으며, 테스트 신뢰성이 확보되는 효과가 있다.In the present invention, even when a pad of a small resistance pattern side is used as a pad of a large pattern resistance when a test pattern is measured for semiconductor process evaluation, the test may be smoothly performed since the small resistance pattern may be vulnerable or broken. The test reliability is secured.

Claims (3)

작은 저항 패턴과 큰 저항 패턴을 형성하고, 이들을 테스트 하기 위한 패드들을 어레이 식으로 형성하는 반도체 테스트 패턴 형성 방법에 있어서,In the semiconductor test pattern formation method of forming a small resistance pattern and a large resistance pattern, and forming pads for testing them in an array manner, 상기 작은 저항 패턴과 큰 저항 패턴 사이에 형성된 최소한 하나 이상의 패드들과 상기 큰 저항 패턴의 인출 위치 사이에 연결 배선을 형성하되 상기 연결 배선은 폭이 상기 큰 저항 패턴을 이루는 패턴의 폭 이상으로 형성함을 특징으로 하는 반도체 테스트 패턴 형성 방법.A connection wiring is formed between at least one pad formed between the small resistance pattern and the large resistance pattern and the withdrawal position of the large resistance pattern, wherein the connection wiring is formed to have a width greater than or equal to the width of the pattern forming the large resistance pattern. Method of forming a semiconductor test pattern, characterized in that. 제 1 항에 있어서,The method of claim 1, 상기 큰 저항 패턴과 상기 작은 저항 패턴은 켈빈 패턴으로 형성됨을 특징으로 하는 반도체 테스트 패턴 형성 방법.And the large resistance pattern and the small resistance pattern are formed of a Kelvin pattern. 제 1 항에 있어서,The method of claim 1, 상기 패드가 형성된 층과 상기 연결 배선이 형성된 층 간의 전기적 연결을 위한 컨택 플러그의 최소 폭은 상기 해당 패턴 폭의 반 이하로 형성됨을 특징으로 하는 반도체 테스트 패턴 형성 방법.And a minimum width of the contact plug for electrical connection between the pad-formed layer and the layer on which the connection wiring is formed is less than half of the width of the corresponding pattern.
KR1020030032897A 2003-05-23 2003-05-23 Test patern forming method in semiconductor process KR20040100510A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100775916B1 (en) * 2006-10-16 2007-11-15 한국표준과학연구원 Electricity conductivity measurement equipment for four terminal resistance measurement method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100775916B1 (en) * 2006-10-16 2007-11-15 한국표준과학연구원 Electricity conductivity measurement equipment for four terminal resistance measurement method

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