KR20040098899A - Delay lock loop and phase locking method of synchronous dram - Google Patents

Abstract

PURPOSE: A delay locked loop and a phase locking method of a synchronous semiconductor memory device are provided to reduce current consumption according to phase locking and also to reduce skew and jitter by increasing accurate resolution. CONSTITUTION: An input signal from a clock buffer(11) is inputted to a divider(18) and is inputted to a phase comparator(12) at the same time. The clock buffer generates an internal clock signal by referring to a clock inputted from the external. The phase comparator compares a phase of an input clock with a phase of an output clock and then outputs a control signal to a delay controller(13). The internal clock signal from the clock buffer is inputted to the phase comparator directly.

Description

DELAY LOCK LOOP AND PHASE LOCKING METHOD OF SYNCHRONOUS DRAM}

The present invention relates to a delay lock loop (DLL) used in SDRAM, and more particularly, to provide a technique for faster phase lock of a delay lock loop.

The delay lock loop (DLL) of the DRAM compensates for a clock skew in which a clock input from the outside is phase-delayed by logic circuits such as an input clock buffer and a data output buffer, which are internal circuits of the DRAM, such that the internal clock is an external clock. It performs the function of being synchronized to. That is, the DLL performs timing control so that data sensed and output from the DRAM core is out of phase with the external clock.

1 is a block diagram illustrating a conventional delay locked loop (DLL) configuration, and in particular, a register controlled DLL.

The delay locked loop of FIG. 1 includes a clock buffer 1, a phase comparator 2, a delay controller 3, a delay line 4, a dummy delay line 5, a clock signal line 6, and an output buffer 7. , A clock divider 8, and a replica delay circuit 9.

The clock buffer 1 generates an internal clock signal based on a clock input from the outside.

The phase comparator 2 is a device for comparing the phase of the input clock and the output clock. Phase comparators typically compare the input clock with a lower frequency while passing through a clock divider to the output clock. Lowering the frequency is to reduce the power consumption of the DLL.

More specifically, the phase comparator 2 causes the input clock signal passing through the clock buffer 1 to pass through the clock divider 8 again, and based on the resultant clock signal, the inside of the delay locked loop DLL Compare the phase with the output clock fed back through the circuit. The comparison result is input as a signal for controlling the delay controller 3 to be described later. The output signals of the phase comparator 2 are three types: lag, lead, and locking. 2 and 3 show an example of the configuration of a specific circuit.

The delay controller 3 is composed of a shift register and a logic circuit. The delay controller 3 operates under the control of the phase comparator 2 to move the clock path input to the delay line 4 and the dummy delay line 5 back and forth. At this time, the change in the degree of delay is made by the logic circuit in the delay controller 3. In addition, the delay line 4 and the dummy delay line 5 are arranged to be tied to the output of the same of the shift registers in the delay controller 3 to form the same clock path.

Delay line 4 is a circuit for delaying the phase of a signal from outside. The degree of phase delay is determined by the phase comparator 2 and a delay path is formed to determine the phase delay under the control of the delay controller 3. The delay line 4 is constituted by a plurality of unit delay cells, and the output of the delay controller 3 is input to each of the unit delay cells.

The dummy delay line 5 forms a phase comparison path that creates a feedback clock and directs it to the phase controller 2. The dummy delay line 5 has a configuration substantially the same as that of the delay line 4, and operates under the control of the delay controller 3 in the same manner as the delay line 4. However, the output signals of the dummy delay line 5 and the delay line 4 are used for different purposes by different devices. That is, delay line 4 is used to make the output clock while dummy delay line 5 is used to make the feedback clock.

The clock signal line 6 functions as a clock driver device that uses the output of the delay line 4 to generate a data output device drive signal.

The output buffer 7 receives the signal of the clock signal line and outputs data to an external output terminal.

The clock divider 8 divides the output clock of the clock buffer 1 into 1 / n (Clock Devider). At this time, n is a positive integer, usually n = 4 or n = 8 is used a lot. The structural example is shown in FIG.

A replica delay circuit 9 receives the output of the dummy delay line 5 as an input and delays the phase of the input clock according to predetermined information and outputs it to the phase comparator 2. This constant information models the phase delay caused by internal circuitry in the clock path of a real DRAM. The device creates the same conditions as the clock path and adds the same phase delay.

2 and 3 show an example of a more specific phase comparator 2.

The phase comparator of FIG. 2 is an example of a basic phase comparator, and the phase comparator of FIG. 3 illustrates a configuration in which an acceleration function is added to the phase comparator of FIG. 2.

First, the phase comparator of FIG. 2 will be described.

The operation of the phase comparator compares the reference clock ref and the feedback clock fb in two flip flops to determine whether the feedback clock is lead, lag or lock. The circuit consists of a reference clock (ref) connected to the clock pulse input of the flip-flop, and a feedback clock (fb) to the other input stage, the phase comparator examines the state of the clock input to the two input stages and the two clocks Determine the phase difference between. However, one flip-flop is connected to the same unit delay cell 21 as that of the delay line 4 and a delay is applied to the feedback clock.

In the phase comparator of this configuration, the outputs coming out of the output stages PC1, PC2, PC3, and PC4 of the flip flop are three combinations as shown in the table of Fig. 5, and according to the output state, The state of the lag and lock is determined.

As a result, phase comparison is performed for each edge of the clock coming into the input terminal of the phase comparator 2 of FIG. 2, and the shift control information 22 of the type shown in the right side of FIG. Will be sent.

At this time, in order to reduce power consumption of the delay locked loop DLL, phases are compared by dividing a clock frequency coming into the delay locked loop DLL using a clock that has been divided by a divider.

However, when the divider is used, a lot of time is required for phase lock, and thus an algorithm for adding an acceleration function as shown in FIG. 3 is used.

The phase comparator with the acceleration function shown in FIG. 3 adds one flip flop more than that of FIG. Several unit delay cells are added at the front of the added flip-flop, and the number is equal to the frequency division ratio of the divider.

FIG. 6 is a diagram showing an example of the configuration of the unit delay cells 21 and 23 and the multi-stage unit delay cells 24 and 25 of FIGS. 2 and 3.

FIG. 6A shows an example of the configuration of a single unit delay cell 21 of the phase comparator shown in FIG. 2 when the division ratio is 8. FIG. FIG. 6B shows an example of the configuration of the multi-stage unit delay cells 24 and 25 of the phase comparator of the acceleration function shown in FIG. 3 when the division ratio is 8. FIG.

The phase comparator using the acceleration algorithm sends a total of four control signals (ground, phase, in-phase, acceleration) to the delay controller. At this time, when the delay controller receives a control signal of 'acceleration', the delay controller moves the delay line by using an undivided high frequency clock which is directly input to a delay locked loop (DLL) instead of a divided clock.

For example, considering the case of using a frequency divider having a frequency division ratio of 8, when the circuit of FIG. 3 using the acceleration function is employed in the period of performing one register shift operation by employing the circuit of FIG. You can do it. As a result, fast phase lock is possible.

When the acceleration algorithm having the configuration as shown in the example of FIG. 3 is adopted, there is an advantage that the phase lock is performed in a shorter time than the basic configuration as shown in the example of FIG. However, if the phase delay is possible by moving the unit delay cell less than the division ratio, the performance is the same, and thus the advantage of speed improvement is lost.

For example, when the 8 division ratio is used, there is no effect of speed improvement when the phase difference between the reference clock and the feedback clock is less than 7 unit delay cells at the starting point.

In addition, if the acceleration function is used and there are seven unit delay cell differences between the two clocks, the acceleration operation is stopped.

However, if the phase difference between the two clocks is more than half of the frequency division ratio, the phase shift can be performed more quickly by accelerating once and then shifting (see FIG. 10). This is because the algorithm used for all phase comparators attempts to lock the phase of the reference clock and the feedback clock equally by shifting the delay controller on only one side.

In addition, in the case of using the conventional phase comparison algorithm, the range in which phase fixing can be performed within 200 cycles, which is a predetermined standard, also loses. That is, when seven accelerations are not operated, since 56 cycles are required for the phase lock operation, the acceleration can be accelerated to only 144 cycles.

7 shows a timing diagram of a delay locked loop employing the acceleration function of FIG.

Prior art related to the present invention is US Pat. No. 6,144,713. This patent aims to shorten the clock synchronization time in the delay lock loop (DLL) by increasing the delay in the phase comparator as the phase difference between the external clock and the internal clock increases.

According to the present invention, in a phase comparator used in a delay locked loop (DLL) of a semiconductor memory device, a phase delay is generated by using the same number of unit delay cells as the division ratio of the divider for the operation of the acceleration function. It is a technical object of the present invention to propose a new configuration for overcoming the disadvantages of the prior art, which compares the phase of the feedback clock.

1 is a block diagram illustrating a register controlled DLL (DLL), which is one of conventional delay locked loop (DLL) configurations;

FIG. 2 illustrates an example of the phase comparator of FIG. 1 in detail; FIG.

3 is a view illustrating in detail an example of a phase comparator added with an acceleration function;

4 is a diagram showing a configuration example of a clock divider of FIG. 1;

FIG. 5 is a table showing an example output of the phase comparator output terminal of FIG. 2; FIG.

FIG. 6 is a diagram illustrating a configuration example of a unit delay cell and a multi-stage unit delay cell of FIGS. 2 and 3;

7 is a timing diagram of a delay locked loop employing the acceleration function of FIG. 3;

8 is a block diagram showing the configuration of a delay locked loop according to the present invention;

9 is a view showing a configuration example of a multi-stage delay cell according to the present invention;

10 is a diagram for explaining a comparison between the phase lock algorithm in the prior art of FIGS. 2 and 3 and the lock algorithm in the present invention of FIG. 8;

11 is a timing diagram of a delay locked loop according to the present invention, and

12 is a table showing an example output of the phase comparator output stage according to the present invention.

* Explanation of symbols for main parts of the drawings

1, 11: clock buffer

2, 12: phase comparator

3, 13: delay controller

4, 14: delay line

5, 15: dummy delay line

8, 18: divider

9, 19: simulation delay circuit

According to the first aspect of the present invention for realizing the above technical problem,

A divider for dividing the frequency of the clock signal input from the outside at a division ratio of 2n, a phase comparator for comparing the phases of the first and second phase delay lines, the reference clock and the feedback clock, and the output of the phase comparator. A method of fixing a phase delay in a delay lock loop (DLL) of a synchronous semiconductor memory device comprising a phase controller for controlling a phase delay of the phase delay line by means of: in the phase comparator, a difference between a reference clock and a feedback clock Comparing the phase with the phase difference between the reference clock and the feedback clock as smaller than n, and performing a normal operation to control the delay controller to move one unit delay cell in one comparison. If the phase difference between the reference clock and the feedback clock is greater than 2n, move 2 * n unit delay cells in one comparison. If the difference between the reference clock and the feedback clock is greater than n and less than 2n in the phase comparator, move 2 * n unit delay cells in one comparison and then add one unit delay cell in one comparison. Controlling a delay controller to move; and a phase delay lock method in a delay lock loop of a semiconductor memory device.

According to the second aspect of the present invention for realizing the above-described technical problem, the frequency of the clock buffer for generating the internal clock signal from the clock signal input from the outside and the clock signal from the clock buffer is divided by 2n. And a first phase delay line composed of a plurality of unit delay circuits and configured to receive an output signal of a clock buffer to change a delay time, and a plurality of unit delay circuits to output an output signal of the divider. A second phase delay line capable of receiving a delay time, a delay controller controlling phase delays of the first phase delay line and the second phase delay line, and an internal delay based on an output of the second phase delay line. A simulation delay circuit for implementing modeling of a path, a clock signal output through a divider from the clock buffer, and feedback from the simulation delay circuit. Compare the phase difference between clock signals and output a control signal to the delay controller according to the result, and determine the number of times the input terminal of the unit delay cell is changed by the divider using the clock frequency before being divided by the divider. A delay locked loop of a synchronous semiconductor memory device including a phase comparator is provided.

By providing the present invention having such a configuration, it is possible to manufacture a semiconductor memory device capable of reducing the circuit construction area and the current consumption according to the reduction of the circuit by exhibiting fewer circuits and a fast phase fixing effect.

Hereinafter, with reference to the accompanying drawings to explain the configuration of the present invention in more detail.

8 is a block diagram showing an overall configuration of a delay locked loop (DLL) according to the present invention.

In terms of the schematic configuration of the delay locked loop (DLL), the block diagram of FIG. 8 is similar to that of FIG. 1, and the phase comparator 12 is simultaneously inputted from the clock buffer 11 to the divider 18. The only difference is that it is also entered.

However, according to this difference, the internal configuration of the phase comparator 12 has been changed. The other part employ | adopted the same structure as the conventional one shown in FIG.

The clock buffer 11 generates an internal clock signal based on a clock input from the outside.

The phase comparator 12 compares the phases of the input clock and the output clock and outputs a control signal to the delay controller 13. The phase comparator 12 causes the input clock signal passed through the clock buffer 12 to pass through the clock divider 18 again, and is fed back through an internal circuit in the delay lock loop DLL based on the resultant clock signal. The phase with the output clock.

The internal clock signal which is an output signal of the clock buffer 11 is also input directly to the phase comparator 12. The input clock signal input from the clock buffer 11 is used to determine the number of times the unit delay cell input terminal in the delay line is changed using a clock of a high frequency in an undivided state.

An alternative configuration of the phase comparator 12 is the same as that of the conventional phase comparator with the acceleration function shown in FIG. However, the configuration of the multi-stage delay cells 24 and 25 is different from that of FIG.

The core of the present invention differs from the prior art by changing the configuration of the multi-stage delay cells 24, 25 of FIG. 3 (see FIG. 6) to change the algorithm for setting the conditions for acceleration.

9 is a diagram illustrating a configuration example of a multi-stage delay cell according to the present invention. 9 shows the configuration of a multi-stage unit delay cell when the frequency division ratio of the frequency divider 18 is set to 8 as in the conventional case of FIG.

The operation of the delay locked loop (DLL) according to the present invention shows the following difference from the case of adopting the acceleration algorithm described with reference to FIG.

In the operation of the delay locked loop using the conventional acceleration algorithm shown in FIG. 3, when the unit delay cell such as the division ratio is used for the multi-stage delay cell, the delay amount between the reference clock and the feedback clock is used for the multi-stage delay cell. If it is smaller than the number, the acceleration function becomes ineffective.

This loss occurs when the phase difference between the reference clock and the feedback clock is greater than half the division rate.If the feedback clock is lag compared to the reference clock by one acceleration, the feedback clock is pulled forward and then reversed. This can be solved by fixing the phase through the shifting operation.

In the present invention, in order to prevent such a loss, the number of stages of the multi-stage delay cell is one step higher than the number divided by half.

In this case, the acceleration function may be applied in two cases even when the feedback clock is earlier than the reference clock.

One of the two methods is to move the unit delay cells of the delay line by the division ratio all at once, and then reduce the delay of the feedback clock without accelerating according to the inverted phase. After stopping, it is generally shifted by one step using the divided clock.

In FIG. 8, the delay controller 13 operates under the control of the phase comparator 12 to move the clock path input to the delay line 14 and the dummy delay line 15 back and forth. At this time, the change of the degree of delay is made according to the configuration of the logic circuit in the delay controller 13.

The delay line 14 is controlled by the phase controller 13 to delay the phase of the externally input signal by a delay amount determined by the phase comparator 12.

The dummy delay line 15 operates under the control of the delay controller 13, and forms a phase comparison path that creates a feedback clock and directs it to the phase controller 12.

The clock signal line 16 functions as a clock driver device that uses the output of the delay line 14 to generate a data output device drive signal.

The output buffer 17 receives the signal of the clock signal line and outputs data to an external output terminal.

The clock divider 18 divides the output clock of the clock buffer 11 into 1 / n (Clock Devider). The structure is the same as the conventional structure example shown in FIG.

The simulation delay circuit 19 receives the output of the dummy delay line 15 as an input and delays the phase of the input clock and outputs it to the phase comparator 2. The device creates the same conditions as the clock path and adds the same phase delay.

Hereinafter, the operation of the phase comparator 12 according to the present invention will be described in comparison with the configuration of FIG. 3 as an example in which a phase difference is generated between the reference clock divided by the division ratio 8 and the feedback clock by 79 unit delay cells. Do it.

In the configuration employing the acceleration function shown in Fig. 3, the 72 acceleration steps are performed by operating the 9 acceleration functions using the acceleration function. Thereafter, the phase comparator determines that the feedback clock delayed by the unit delay cells of the eight stages is behind the reference clock, and then shifts the remaining seven stages using the divided clock without accelerating.

On the other hand, in the case of using the technique of the present invention, the phase of the feedback clock and the reference clock which is phase-delayed by five stage delay cells after nine acceleration operations are compared with the conventional algorithm. This adds one acceleration because the feedback clock is still in phase with the reference clock. This operation causes the phase to be inverted between the two clocks, which then triggers the delay controller to shift the feedback clock on the opposite side of the phase comparator.

In summary, when the algorithm of the present invention is used, a total of 10 acceleration operations are performed, and a shift operation using one divided clock is performed.

As a result, using the prior art requires a total of 9 * 8 (acceleration enabled) + 7 * 8 (normal) = 128 cycles of phase lock time. On the other hand, when using the technique of the present invention, only 10 * 8 (acceleration use) + 1 * 8 (normal) = 88 cycles are required.

The range in which the fast phase lock time can be realized by applying the algorithm of the present invention is as follows.

The conventional algorithm is shifted in only one direction, so when there is a phase difference between two clocks by a unit delay cell smaller than the division ratio, it is better to shift to one side as in the conventional algorithm. However, if the difference between the two clocks is greater than the division ratio, it is faster to shift the phase after changing the fast phase through one acceleration.

In particular, this algorithm has a larger performance difference when using a high ratio divider.

FIG. 10 is a diagram for explaining and comparing the phase lock algorithm in the prior art of FIGS. 2 and 3 with the lock algorithm in the present invention of FIG. 8. As shown in the figure, it can be seen that the phase lock algorithm according to the present invention has an excellent acceleration effect compared to the case of not applying the acceleration algorithm or the conventional phase lock algorithm.

Fig. 11 shows a timing chart of the phase lock circuit in the case of employing the acceleration algorithm of the present invention.

12 shows four output results according to the state of the feedback clock versus the reference clock in the present invention.

While the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to these embodiments and various modifications can be made without departing from the spirit of the present invention.

By providing the present invention having the configuration described above, it is possible to provide a delay locked loop (DLL) designed to further reduce the phase lock time of the synchronous semiconductor memory device. In particular, even after losing some of the 200 cycles due to an unstable situation outside the delay lock loop (DLL), it is possible to meet the specification through fast phase lock.

In addition, the risk of mismatches between the unit delay cells of the actual delay line and the unit delay cells used in the phase comparator is reduced.

In addition, there is no additional burden on the circuit, and the reduction of the circuit can be accompanied, thereby reducing the charge area and the current consumption, and also reducing the current consumption due to fast phase lock.

Conventionally, when the frequency divider of division ratio 8 is operated, the number of unit delay cells of the delay line that can be used maximum when the conventional algorithm is used should be less than 159 stages. However, by providing the present invention, unit delay cells of less than 180 stages are provided. Has become available. As a result, more unit delay cells can be used, which enables precise resolution by reducing delay values of unit delay cells, and further reduces skew and jitter.

Claims (9)

A divider for dividing the frequency of the clock signal input from the outside at a division ratio of 2n, a phase comparator for comparing the phases of the first and second phase delay lines, the reference clock and the feedback clock, and the output of the phase comparator. A method of fixing a phase delay in a delay lock loop (DLL) of a synchronous semiconductor memory device including a phase controller for controlling a phase delay of the phase delay line by In the phase comparator, Comparing the difference between the reference clock and the feedback clock; As a result of the comparison, when the phase difference between the reference clock and the feedback clock is less than n, the delay controller is controlled to move one unit delay cell in one comparison by performing a normal operation, and the phase comparator between the reference clock and the feedback clock. If the phase difference of is greater than 2n, the delay controller is controlled to move 2 * n unit delay cells in one comparison.If the difference between the reference clock and the feedback clock in the phase comparator is greater than n and less than 2n, Controlling the delay controller to move 2 unit delay cells in one comparison and then move one unit delay cell in one comparison in a comparison. . The method of claim 1, In the phase comparator, A phase delay lock method in a delay lock loop of a semiconductor memory device, characterized by comparing a phase of a reference clock and a feedback clock with a unit delay cell and a multi-stage unit delay cell. The method of claim 2, And wherein the multi-stage unit delay cells are configured using n or more unit delay cells of n to 2n or less. The method according to any one of claims 1 to 3, In the phase comparator If the phase difference between the reference clock and the feedback clock is greater than the number of multi-stage delay cells, the delay controller is controlled to move the unit delay cell stage by using the clock before division. Phase delay lock method. A clock buffer for generating an internal clock signal from a clock signal input from the outside, a divider for dividing the frequency of the clock signal from the clock buffer at a division ratio of 2n; A first phase delay line composed of a plurality of unit delay circuits and configured to receive an output signal of a clock buffer and change a delay time; A second phase delay line composed of a plurality of unit delay circuits and configured to receive an output signal of the divider and change a delay time; A delay controller controlling phase delays of the first phase delay line and the second phase delay line; A simulation delay circuit for implementing modeling of an internal delay path based on an output of a second phase delay line; Comparing the phase difference between the clock signal output from the clock buffer through a divider and the feedback clock signal from the simulation delay circuit and outputs a control signal to the delay controller according to the result, wherein the delay controller of the unit delay cell A phase locked loop of a synchronous semiconductor memory device comprising a phase comparator for determining the number of times of changing the input stage using a clock frequency before being divided by the divider. The method of claim 5, The phase comparator As a result of comparing the difference between the reference clock and the feedback clock, If the phase difference between the reference clock and the feedback clock is less than n, the normal operation is performed to control the delay controller to move one unit delay cell in one comparison. In the phase comparator, the phase difference between the reference clock and the feedback clock If greater than 2n, the delay controller is controlled to move 2 * n unit delay cells in one comparison, and if the difference between the reference clock and the feedback clock in the phase comparator is greater than n and less than 2n, 2 * in one comparison A delay lock loop of a synchronous semiconductor memory device, characterized in that the delay controller is controlled to move n unit delay cells and then move one unit delay cell in one comparison. The method of claim 6, The phase comparator A delay locked loop of a synchronous semiconductor memory device characterized by comparing a phase of a reference clock and a feedback clock with a unit delay cell and a multi-stage unit delay cell. The method of claim 7, wherein And the multi-stage unit delay cells are configured using at least n and at most 2n unit delay cells. The method according to any one of claims 5 to 7, The phase comparator When the phase difference between the reference clock and the feedback clock is greater than the number of multi-stage delay cells, the delay controller is controlled to move the unit delay cell stage by using the clock before the clock signal is divided by the divider. Fixed loops.