KR20040084569A - method of fabricating a split gate flash memory cell - Google Patents

Abstract

PURPOSE: A method for manufacturing a split gate type flash memory cell is provided to restrain bird's beak formed at lower of a nitride layer by oxidizing a polysilicon spacer at sidewalls of an opening part when forming a floating gate poly oxide layer. CONSTITUTION: A substrate(100) defined with common source line and cell active regions(130,140) is prepared. A gate insulating layer(200) is formed on the active regions. A polysilicon layer is formed on the resultant structure. A nitride pattern with an opening part is formed on the polysilicon layer. A spacer is formed at sidewalls of the opening part. A floating gate poly oxide layer is formed in the opening part by oxidizing the spacer and the exposed polysilicon layer. The nitride pattern is removed. A floating gate(320) is then formed by etching the polysilicon layer using the floating gate poly oxide layer as a mask.

Description

Method of fabricating a split gate flash memory cell {method of fabricating a split gate flash memory cell}

The present invention relates to a method of manufacturing a nonvolatile memory cell, and more particularly, to a method of manufacturing a split gate type flash memory cell.

Non-volatile memory that retains stored data even when the power is cut off includes mask ROM, PROM, EPROM, EEPROM, Flash Memory, etc. Among them, the flash memory is a highly integrated non-volatile memory which is capable of erasing data and electrically programming, developed by combining the advantages of Ipyrom and Ipyrom.

Such a flash memory is divided into a cell having a stacked gate structure, a structure in which a separate selection transistor is formed, and a split gate structure. In the case of a flash memory having a stacked gate structure, a bit line leakage current increases due to over erase, and thus a structure in which a separate selection transistor is formed is used to solve this problem. It works against you. Therefore, the split gate type flash memory is widely used at present.

1 is a plan view showing a portion of a typical split gate type flash memory cell array region.

Referring to FIG. 1, an active region 150 is disposed in a predetermined region of a semiconductor substrate. The active region 150 includes a plurality of common source line active regions 130 parallel to each other and a plurality of cell active regions 140 disposed to cross the common source line active regions 130. . A pair of floating gates 320 spaced apart from each other are disposed on the cell active regions 140. The floating gates 320 are disposed to be adjacent to the common source lines 130. A pair of parallel word lines 800 is disposed between the common source lines 130. The word lines 800 cross the upper portions of the cell active regions 140 and the floating gates 320.

2A through 2C are cross-sectional views illustrating a method of manufacturing a conventional split gate type flash memory cell taken along the cutting line II-II ′ of FIG. 1.

Referring to FIG. 2A, device isolation layers 150a are formed in predetermined regions of the semiconductor substrate 100 to define cell active regions 140 and common source line active regions 130 of FIG. 1. A gate insulating layer 200 is formed on the active regions. The floating gate polysilicon layer 300 is formed on the entire surface of the semiconductor substrate including the gate insulating layer 200. A nitride film 500 having openings 550 exposing a predetermined region of the floating gate polysilicon film 300 is formed on the floating gate polysilicon film 300. The openings are positioned above predetermined regions of the cell active regions 140.

Referring to FIG. 2B, the semiconductor substrate including the nitride film 500 is thermally oxidized to form floating gate poly oxides 310 in the openings 550. As a result, a bird's beak 315 is formed under the nitride film 500 adjacent to the openings 550. In order to implement a highly integrated flash memory device, the gap between the openings 550, that is, the gap between the cell active regions 140 must be reduced. In this case, the floating gate poly oxide films 310 adjacent to each other may be in contact with each other due to the buzz beak 315 as shown in FIG. 2B.

Referring to FIG. 2C, after removing the nitride film 500, the floating gate poly silicon film 300 is etched using the floating gate poly oxide film 310 as an etching mask. As a result, the floating gates 320 are formed under the floating gate poly oxide layers 310. However, as shown in FIG. 2B, when the neighboring floating gate poly oxide layers 310 contact each other, the neighboring floating gates 300 are electrically connected to each other. This causes a malfunction of the flash memory cell.

As described above, according to the related art, it is difficult to electrically insulate neighboring floating gates when the spacing between adjacent cell active regions is narrow. Accordingly, there is a limit to increasing the degree of integration of the split gate type flash memory device.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above-mentioned problems of the prior art, and a method of manufacturing a split gate flash memory cell that facilitates an increase in integration by suppressing the occurrence of a buzz beak in the floating gate poly oxide film formation process. In providing.

1 is a plan view showing a portion of a typical split gate type flash memory cell array region.

2A through 2C are cross-sectional views illustrating a method of manufacturing a conventional split gate type flash memory cell taken along the cutting line II-II ′ of FIG. 1.

3A to 3E are cross-sectional views illustrating a method of manufacturing split gate type flash memory cells according to an exemplary embodiment of the present invention taken along the cutting line II ′ of FIG. 1.

4A through 4E are cross-sectional views illustrating a method of manufacturing split gate type flash memory cells according to an exemplary embodiment of the present invention taken along the cutting line II-II ′ of FIG. 1.

(Explanation of symbols for main parts of drawing)

100 semiconductor substrate 130 common source line active region

140: cell active area 150: active area

150a: device isolation layer 200: gate insulating layer

300: floating gate polysilicon film

310: floating gate poly oxide

315: bird's beak 320: floating gate

400: buffer oxide 500: nitride film

550: opening 610: polysilicon spacer

700: tunnel insulation film

800: control gate, word line

The present invention provides a method of manufacturing a split gate type flash memory cell.

This method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. After forming a gate insulating film on the active region, a floating gate polysilicon film is formed on the entire surface of the substrate having the gate insulating film. A nitride film pattern having an opening that exposes a portion of the floating gate polysilicon film is formed on the floating gate polysilicon film, and then a spacer is formed on the sidewall of the opening. The spacer and the exposed floating gate polysilicon layer are thermally oxidized to form a floating gate poly oxide in the opening. After removing the nitride layer pattern, the floating gate poly oxide layer is etched using the floating gate poly oxide as a mask to form a floating gate covering a portion of the active region.

The spacer is an oxidizable material, preferably polysilicon.

Before forming the nitride film pattern, it is preferable to form a buffer oxide film on the floating gate polysilicon film. The buffer oxide film serves as an etch stop film during the formation of the spacer and is removed after removal of the nitride film pattern.

After the floating gate is formed, a tunnel insulating film is formed on the sidewall of the floating gate and the active region around the floating gate, and then a word line is formed to cover the tunnel insulating film. The word line is formed to cross the active region.

The nitride layer pattern may be removed by wet etching. In addition, the buffer oxide film may also be removed by wet etching.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

3A to 3E are cross-sectional views illustrating a method of manufacturing split gate type flash memory cells according to an exemplary embodiment of the present invention taken along the cutting line II ′ of FIG. 1. 4A through 4E are cross-sectional views illustrating a method of manufacturing split gate type flash memory cells according to an exemplary embodiment of the present invention taken along the cutting line II-II ′ of FIG. 1.

3A and 4A, device isolation layers 150a are formed in predetermined regions of the semiconductor substrate 100 to define cell active regions 140 and common source line active regions 130. The device isolation layers 150a may preferably use a shallow trench isolation (STI) method.

A gate insulating layer 200 is formed on the cell active regions 140 and the common source line active regions 130. The gate insulating film may be a thermal oxide film or an oxide film by low pressure chemical vapor deposition (LPCVD), and may have a thickness of about 70 kPa to about 90 kPa.

The floating gate polysilicon layer 300 is formed on the entire surface of the semiconductor substrate including the gate insulating layer 200. After the buffer oxide film 400 and the nitride film 500 are sequentially formed on the entire surface of the semiconductor substrate including the floating gate polysilicon film 300, predetermined regions of the buffer oxide film 400 are formed by photolithography and etching. A pattern of the nitride film 500 having openings 550 to be exposed is formed. The openings 550 are positioned above predetermined regions of the cell active regions 140.

3B and 4B, after stacking polysilicon on a front surface of the semiconductor substrate including the openings 550, the polysilicon is anisotropically etched to form polysilicon spacers on sidewalls of the openings 550. Form the field 610. The anisotropic etching is performed until the buffer oxide layer 400 in the openings 550 that are the etch stop layer is exposed.

3C and 4C, the semiconductor substrate having the polysilicon spacers 610 is thermally oxidized to form floating gate poly oxide layers 310 in the openings 550. The floating gate poly oxide layers 310 are formed by oxidizing the polysilicon spacers 610 and an upper portion of the floating gate polysilicon layer 300 in the openings 550.

In the process of forming the floating gate poly oxide layer 310, the polysilicon spacers 610 on the side walls of the openings 550 are oxidized, so that a buzz beak may be formed under the nitride film 500 adjacent to the openings 550. bird's beak) is suppressed. Therefore, contact due to the buzz beak of the floating gate poly oxide films 310 adjacent to each other is suppressed. As a result, the spacing between the openings 550, that is, the spacing between the cell active regions 140 can be reduced, thereby enabling the implementation of a highly integrated flash memory device.

Referring to FIGS. 3D and 4D, the nitride film 500, which is in contact with the floating gate poly oxide films 310, is removed by wet etching to expose the buffer oxide film 400 below, and the exposed buffer is exposed. The oxide film 400 is also removed by wet etching. As a result, the floating gate polysilicon layer 300 in the region other than the region in which the floating gate poly oxide layers 310 are located is exposed. In the wet etching process of the buffer oxide film 400, the floating gate poly oxide films 310 may also be partially etched.

The floating gate polysilicon layer 300 exposed by the wet etching is etched using the floating gate poly oxide layers 310 as an etching mask. As a result, floating gates 320 are formed under the floating gate poly oxide layers 310. The floating gates 320 are positioned above predetermined regions of the cell active regions 140, and are insulated from the cell active regions 140 by the gate insulating layer 200.

3E and 4E, after the floating gates 320 are formed, the cell active regions 140 and the common source around the sidewalls of the floating gates 320 and the floating gates 320 are formed. A tunnel insulating layer 700 is formed on the line active regions 130 of FIG. 1. The control gate polysilicon is deposited on the entire surface of the semiconductor substrate on which the tunnel insulating layer 700 is formed. Subsequently, the control gates 800, that is, word lines, are formed through photolithography and etching.

The word lines 800 overlap the floating gates 320 and the cell active regions 140 adjacent to the floating gates 320 and the cell active regions 140 adjacent to the floating gates. Are parallel to the common source line active regions 130. The word lines 800 and the floating gates 320 are insulated by the floating gate poly oxide layers 310 and the tunnel insulating layer 700, and the word lines 800 and the cell active regions 140. Is insulated by the gate insulating film 200.

As described above, according to the present invention, in the process of forming the floating gate poly oxide film, the polysilicon spacers of the sidewalls of the openings are oxidized to suppress the formation of a bird's beak under the nitride film adjacent to the openings.

Therefore, the spacing between cell active regions can be reduced, thereby enabling the implementation of highly integrated flash memory devices.

Claims (6)

Defining an active region by forming an isolation layer in a predetermined region of the semiconductor substrate; Forming a gate insulating film on the active region; Forming a floating gate polysilicon film on an entire surface of the substrate having the gate insulating film; Forming a nitride film pattern on the floating gate polysilicon film, the nitride film pattern having an opening that exposes a portion of the floating gate polysilicon film; Forming a spacer on the sidewall of the opening; Thermally oxidizing the spacer and the exposed floating gate polysilicon layer to form a floating gate poly oxide in the opening; Removing the nitride film pattern; And Forming a floating gate covering a portion of the active region by etching the floating gate polysilicon layer using the floating gate poly oxide as a mask. The method of claim 1, And said spacer is polysilicon. The method of claim 1, Before forming the nitride film pattern, And forming a buffer oxide layer on the floating gate polysilicon layer, wherein the buffer oxide layer serves as an etch stop layer during the formation of the spacer and is removed after removal of the nitride layer pattern. Manufacturing method. The method of claim 1, After forming the floating gate, Forming a tunnel insulating film on sidewalls of the floating gate and the active region around the floating gate; And Forming a word line covering the tunnel insulating layer, wherein the word line is formed to cross the active region. The method of claim 1, And removing the nitride film pattern by wet etching. The method of claim 2, The method of claim 1, wherein the buffer oxide film is removed by wet etching.