KR100519790B1 - a split gate flash memory cell and method of fabricating the same - Google Patents

Abstract

A split gate flash memory cell and a method of manufacturing the same are provided. This split gate type flash memory cell has a device isolation film formed on a semiconductor substrate to define an active region. A floating gate in the form of a spacer having a sidewall and an inclined sidewall perpendicular to the active region is disposed. A word line overlapping at least the vertical sidewall and crossing the active area is disposed. An insulating film spacer is interposed between the vertical sidewall and the word line. A source region formed in the active region adjacent to the inclined sidewall and positioned opposite the word line and a drain region formed in the active region adjacent to the word line and positioned opposite the source region are disposed. The floating gate protrudes from a lower region of the vertical sidewall and has a horizontal extension interposed between the lower surface of the insulating layer spacer and the active region. By forming the floating gate in the form of a spacer, it is possible to reduce the dependency on the photo process equipment. Therefore, it is easy to form a fine pattern floating gate, thereby enabling the implementation of a highly integrated flash memory device.

Description

Split gate flash memory cell and method of fabricating the same

TECHNICAL FIELD The present invention relates to a nonvolatile memory cell and a method of manufacturing the same, and more particularly, to a split gate flash memory cell and a method of manufacturing the same.

Non-volatile memory that retains stored data even when the power is cut off includes mask ROM, PROM, EPROM, EEPROM, Flash Memory, etc. Among them, the flash memory is a highly integrated non-volatile memory which is capable of erasing data and electrically programming, developed by combining the advantages of Ipyrom and Ipyrom.

Such a flash memory is divided into a cell having a stacked gate structure, a structure in which a separate selection transistor is formed, and a split gate structure. In the case of a flash memory having a stacked gate structure, a bit line leakage current increases due to over erase, and thus a structure in which a separate selection transistor is formed is used to solve this problem. It works against you. Therefore, the split gate type flash memory is widely used at present.

1 is a plan view showing a portion of a conventional split gate type flash memory cell array region.

Referring to FIG. 1, an active region 15 is disposed in a predetermined region of a semiconductor substrate. The active region 15 includes a plurality of common source line active regions 13 parallel to each other and a plurality of cell active regions 14 disposed to cross the common source line active regions 13. A pair of floating gates 35 spaced apart from each other are disposed on the cell active regions 14. The floating gates 35 are disposed to be adjacent to the common source lines 13. A pair of parallel word lines 95 are disposed between the common source lines 13. The word lines 95 cross the upper portions of the cell active regions 14 and the floating gates 35.

2A through 2C are cross-sectional views illustrating a method of manufacturing a conventional split gate type flash memory cell taken along the cutting line I-I of FIG. 1.

Referring to FIG. 2A, the cell active regions 14 and the common source line active regions 13 are defined in a predetermined region of the semiconductor substrate 10. A gate insulating film 20 is formed on the active regions. The floating gate polysilicon film 30 and the nitride film 40 are sequentially formed on the entire surface of the semiconductor substrate including the gate insulating film 20.

Subsequently, a photoresist film 50 having photoresist openings 50a exposing a predetermined region of the nitride film 40 is formed on the nitride film 40. The photoresist openings 50a are located in a region where the floating gates 35 of FIG. 1 are to be formed.

In this case, corner rounding of photoresist openings may occur on some regions of the semiconductor substrate 10 due to a lack of a margin for a resolution limit of the photolithography process. As a result, a region in which the opening of the photoresist film is not sufficient, that is, a photoresist-incomplete opening region 50b or a region in which the opening of the photoresist film is not opened, that is, the photoresist unopened region 50c is formed.

Referring to FIG. 2B, the nitride film 40 is etched using the photoresist film 50 as an etching mask, thereby forming nitride film openings 40a exposing a portion of the floating gate polysilicon film 30. The semiconductor substrate having the nitride openings 40a is thermally oxidized to form floating gate poly oxides 33 in the nitride openings 40a.

At this time, the photoresist insufficient opening region 50b is also insufficiently formed in the opening of the nitride film 40 to become the nitride film insufficient opening region 40b, and the photoresist unopened region 50c is the nitride film 40. Is not opened, resulting in the nitride film unopened region 40c.

Referring to FIG. 2C, after the nitride layer 40 is removed, the floating gate polysilicon layer 30 is etched using the floating gate poly oxide layer 33 as an etching mask. As a result, the floating gates 35 are formed under the floating gate poly oxide layers 33. The tunnel insulating layer 80 is formed on the entire surface of the semiconductor substrate having the floating gates 35. A word line 95 is formed on the tunnel insulating layer 80 to cross the cell active regions 14 and the floating gates 35.

In this case, an incomplete floating gate 35b in which the floating gate is not formed properly is formed in the nitride film insufficient opening region 40b, and no floating gate is formed in the nitride film non-opening region 40c.

In order to implement a highly integrated flash memory device, a fine floating gate 35 should be formed. For this purpose, a fine photoresist opening 50a should be formed. However, as described above, the formation of the fine photoresist opening 50a causes the problems 50b and 50c when the margin for the resolution limit of the photographing process is insufficient. Therefore, since the conventional floating gate flash memory cell manufacturing method is not easy to form a fine floating gate, there is a limit in increasing the integration degree of the split gate flash memory device.

The technical problem to be solved by the present invention is to solve the above problems of the prior art, a split gate type flash memory cell including a floating gate in the form of at least a spacer having a width smaller than the resolution limit of the photographic process (resolution limit) And a fabrication method thereof to facilitate an increase in the degree of integration of a split gate type flash memory device.

In order to achieve the above technical problem, the present invention provides a split gate type flash memory cell and a method of manufacturing the same.

The split gate type flash memory cell according to the present invention includes an isolation layer formed on a semiconductor substrate to define an active region. A floating gate in the form of a spacer having a sidewall and an inclined sidewall perpendicular to the active region is disposed. A word line overlapping at least the vertical sidewall and crossing the active area is disposed. A source region formed in the active region adjacent to the inclined sidewall and positioned opposite the word line and a drain region formed in the active region adjacent to the word line and positioned opposite the source region are disposed.

The semiconductor device may further include an insulation layer spacer interposed between the vertical sidewall and the word line. In this case, the floating gate protrudes from the lower region of the vertical sidewall and has a horizontal extension interposed between the lower surface of the insulating film spacer and the active region.

A gate insulating layer may be interposed between the floating gate and the active region, and a tunnel insulating layer may be interposed between the floating gate and the word line and between the word line and the active region.

The insulating layer spacer may be an oxide layer.

A method of manufacturing a split gate type flash memory cell according to the present invention includes forming an isolation layer on a semiconductor substrate to define an active region. A gate insulating film is formed on the entire surface of the semiconductor substrate including the active region. A floating gate overlapping the active region is formed on the gate insulating layer, and the floating gate includes at least a spacer-shaped floating gate having a vertical sidewall and an inclined sidewall. A tunnel insulating film is formed on the entire surface of the substrate including the floating gate. A word line overlapping the at least one vertical sidewall and crossing the active region is formed on the tunnel insulating layer.

The forming of the floating gate may include forming a sacrificial layer pattern crossing the active region on the gate insulating layer, forming a preliminary floating gate having a spacer shape on a sidewall of the sacrificial layer pattern, and then removing the sacrificial layer pattern. Preferably exposing the vertical sidewalls of the preliminary floating gate.

Forming the floating gate preferably includes forming a lower floating gate film on the entire surface of the semiconductor substrate having the gate insulating film. A sacrificial layer pattern is formed on the lower floating gate layer to cross the active region. An upper floating gate layer is formed on the entire surface of the semiconductor substrate having the sacrificial layer pattern. The upper and lower floating gate layers are anisotropically etched to form a lower preliminary floating gate pattern remaining below the upper preliminary floating gate and the lower portion of the sacrificial layer pattern together with the upper preliminary floating gate covering the sidewalls of the sacrificial layer pattern. The sacrificial layer pattern is removed to expose the vertical sidewall of the upper preliminary floating gate and the upper surface of the lower preliminary floating gate. An insulating layer spacer is formed on the vertical sidewall, and the lower preliminary floating gate is etched using the insulating layer spacer as an etch mask to form a lower floating gate remaining under the upper preliminary floating gate and under the insulating layer spacer.

The sacrificial layer pattern may be formed of a nitride layer.

The insulating layer spacer may be formed of an oxide layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms.

In the figures, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

3A, 4A, 5A, and 6A are plan views illustrating a method of manufacturing split gate type flash memory cells according to process steps, according to an exemplary embodiment. FIGS. 3B, 4B, 5B, and 6B are FIGS. Are cross-sectional views taken along the cutting line I-I of FIGS. 3A, 4A, 5A, and 6A, respectively.

3A and 3B, device isolation layers 150a are formed on the semiconductor substrate 100 to define the active region 150. The device isolation layers 150a may be formed using a conventional trench device isolation technique. The active region 150 includes common source line active regions 130 and cell active regions 140. The cell active regions 140 are disposed to cross the common source line active regions 130.

A gate insulating layer 200 is formed on the active region 150. The gate insulating layer 200 may be a thermal oxide film or a CVD oxide film. The thickness is preferably about 50 to 100 mm 3.

It is preferable to form a sacrificial layer pattern 400 on the gate insulating layer 200. The sacrificial layer pattern 400 may be formed in a line shape in parallel with the common source line active regions 130 across the cell active regions 140.

The sacrificial layer pattern may be formed of a nitride layer.

Referring to FIGS. 4A and 4B, after the floating gate layer is stacked on the entire surface of the semiconductor substrate including the sacrificial layer pattern 400, the floating gate layer is selectively anisotropically etched to form sidewalls of the sacrificial layer pattern 400. Preliminary floating gates 610 in the form of covering spacers are formed. Since the preliminary floating gates 610 are formed along sidewalls of the sacrificial layer pattern 400, the preliminary floating gates 610 are formed in a line shape in parallel with the common source line active regions 130.

The floating gate film is preferably polysilicon. In addition, the anisotropic etching is preferably dry etching by RIE (Reactive Ion Etching).

Subsequently, after the photoresist pattern exposing the common source line active regions 130 is formed, predetermined impurities are implanted into the exposed common source line active regions 130 to form common source regions 135.

5A and 5B, the sacrificial layer pattern 400 is removed to expose the cell active regions 140, and the preliminary floating gates 610 are etched to isolate the cell active regions 140. The floating gates 650 are formed.

The floating gates 650 have a spacer shape. In other words, each of the floating gates 650 has a vertical sidewall 650a and an inclined sidewall 650b. The inclined sidewalls 650b are adjacent to the common source regions 135. The vertical sidewalls 650a are opposite to the common source region 135. In addition, each of the floating gates 650 has a sharp protrusion 650c formed on the upper side of the vertical sidewall 650a and the inclined sidewall 650a.

The sacrificial layer pattern 400 is preferably removed by wet etching.

6A and 6B, a tunnel insulating layer 800 is formed on the entire surface of the semiconductor substrate including the floating gates 650. The tunnel insulating film 800 may be a thermal oxide film or a CVD oxide film, and the thickness thereof is preferably 100 to 300 kPa.

Word lines 950 are formed on the tunnel insulating layer 800 to overlap at least the vertical sidewalls 650a of the floating gates 650 and cross the cell active regions 140. The word lines 950 may cover the pointed protrusions 650c on the floating gates 650.

Subsequently, after forming a photoresist pattern exposing the cell active regions 140 between the word lines 950, a predetermined impurity is injected into the exposed cell active regions 140 to drain the region 145. Form them.

Referring back to Figures 6A and 6B, split gate type flash memory cells according to one embodiment of the present invention are described.

The split gate type flash memory cells include an active region 150 defined in a predetermined region of the semiconductor substrate 100. The active region 150 includes a plurality of common source line active regions 130 and a plurality of cell active regions 140 crossing the common source line active regions 130. Common source regions 135 having a line shape doped with a predetermined impurity are positioned on surfaces of the common source line active regions 130.

A pair of floating gates 650 spaced apart from each other are disposed on the cell active regions 140. The floating gates 650 have a spacer shape. In other words, each of the floating gates 650 has a vertical sidewall 650a and an inclined sidewall 650b. The inclined sidewalls 650b are adjacent to the common source regions 135. The vertical sidewalls 650a are opposite to the common source region 135. In addition, each of the floating gates 650 has a pointed protrusion 650c on which the vertical sidewall 650a and the inclined sidewall 650b meet each other.

A gate insulating layer 200 is interposed between the floating gates 650 and the cell active region 140. The gate insulating film 200 may be a thermal oxide film or a CVD oxide film, and the thickness thereof is preferably 50 to 100 GPa.

At least the vertical sidewalls 650a are covered with word lines 950. The word lines 950 extend to cross the cell active regions 140. As a result, a pair of parallel word lines 950 are disposed between the common source line active regions 130 adjacent to each other.

A tunnel insulating layer 800 is interposed between the word lines 950 and the floating gates 650. In addition, the tunnel insulating layer 800 is interposed between the word lines 950 and the cell active regions 140. The tunnel insulating film 800 may be a thermal oxide film or a CVD oxide film, the thickness is preferably 100 to 300 내지.

 Drain regions 145 doped with a predetermined impurity are positioned on surfaces of the cell active regions 140 between the word lines 950.

 The word lines 950 may cover the pointed protrusions 650c. In this case, when a positive erase voltage is applied to the word lines 950 and the common source region 135 and the drain region 145 are grounded, an electric field is applied to the protrusions 650c. Are concentrated. As a result, the efficiency of injecting electrons in the floating gates 650 into the wordlines 950 may be significantly increased. In other words, when the protrusions 650c overlap with the word lines 950, the erase efficiency of the flash memory cell is remarkably improved.

7A, 8A, 9A, 10A, 11A, and 12A are plan views illustrating a method of manufacturing split gate type flash memory cells according to a process step, according to another embodiment of the present invention, and FIGS. 7B and 8B. 9B, 10B, 11B, and 12B are cross-sectional views taken along the cutting line I-I of FIGS. 7A, 8A, 9A, 10A, 11A, and 12A, respectively.

7A and 7B, device isolation layers 150a are formed on the semiconductor substrate 100 to define the active region 150. The device isolation layers 150a may be formed using a conventional trench device isolation technique. The active region 150 includes common source line active regions 130 and cell active regions 140. The cell active regions 140 are disposed to cross the common source line active regions 130.

A gate insulating layer 200 is formed on the active region. The gate insulating layer 200 may be a thermal oxide film or a CVD oxide film. The thickness is preferably about 50 to 100 mm 3.

The lower floating gate layer 300 is formed on the gate insulating layer 200. Preferably, the lower floating gate layer 300 is made of polysilicon, and its thickness is preferably about 300 to 1000 mm.

A sacrificial layer pattern 400 is formed on the lower floating gate layer 300. The sacrificial layer pattern 400 may be formed in a line shape in parallel with the common source line active regions 130 across the cell active regions 140.

The sacrificial layer pattern may be formed of a nitride layer.

Referring to FIGS. 8A and 8B, after the upper floating gate layer is stacked on the entire surface of the semiconductor substrate 100 having the sacrificial layer pattern 400, the upper floating gate layer and the lower floating gate layer underneath are selectively formed. Anisotropically etch. In this case, the lower preliminary floating gate 320 remaining below the upper preliminary floating gates 620 and the lower portion of the sacrificial layer pattern 400 together with the upper preliminary floating gates 620 covering the sidewalls of the sacrificial layer pattern 400. ) Is formed. The upper preliminary floating gates 620 are in the form of spacers having vertical sidewalls 620a and inclined sidewalls 620b, respectively. In addition, since the upper preliminary floating gates 620 are formed along the sidewall of the sacrificial layer pattern 400, the upper preliminary floating gates 620 are lined in parallel with the common source line active regions 130.

The upper floating gate layer is preferably made of the same material as the lower floating gate layer 300. Therefore, it is preferable that the upper floating gate film is also polysilicon, and the thickness thereof is preferably 1000 to 2000 GPa. The anisotropic etching is preferably dry etching by reactive ion etching (RIE).

Subsequently, after the photoresist pattern exposing the common source line active regions 130 is formed, predetermined impurities are implanted into the exposed common source line active regions 130 to form common source regions 135.

9A and 9B, the sacrificial layer pattern 400 is removed to expose the vertical sidewalls 620a and the upper surface of the lower preliminary floating gate 320. Subsequently, the upper and lower preliminary floating gates are etched to form upper preliminary floating gates 630 and lower preliminary floating gates 330 isolated by the cell active regions 140.

The sacrificial layer pattern 400 may be removed by wet etching.

10A and 10B, insulating layer spacers 750a are formed on vertical sidewalls 630a of the upper preliminary floating gates 630. In this case, the insulating layer spacers 750b may be formed on the inclined sidewalls 630b as well as the vertical sidewalls 630a of the upper preliminary floating gates 630. The insulating layer spacers 750a and 750b may be oxide layers.

11A and 11B, the lower preliminary floating gates 330 are etched using the insulating layer spacers 750a as etch masks, thereby lowering the upper preliminary floating gates 630 and lower portions of the insulating layer spacers 750a. Lower floating gates 340 remaining in the formation are formed. The lower floating gate 340 and the upper preliminary floating gate 630 thereon constitute a floating gate 650. As a result, a pair of floating gates 650 spaced apart from each other are formed on each cell active region 140.

The floating gates 650 have a spacer shape. In other words, each floating gate 650 has a vertical sidewall 650a and an inclined sidewall 650b. The inclined sidewalls 650b are adjacent to the common source regions 135. The vertical sidewalls 650a are opposite to the common source region 135. In addition, each of the floating gates 650 has a sharp protrusion 650c formed on the upper side of the vertical sidewall 650a and the inclined sidewall 650b meet each other. In addition, the floating gates 650 may have horizontal extensions p due to the lower floating gates 340 under the insulating layer spacers 750a.

12A and 12B, a tunnel insulating film 800 is formed on the entire surface of the semiconductor substrate including the floating gates 650. The tunnel insulating film 800 may be a thermal oxide film or a CVD oxide film, and the thickness thereof is preferably 100 to 300 kPa.

Word lines 950 are formed on the tunnel insulating layer 800 to overlap at least the vertical sidewalls 650a and cross the cell active regions 140. The word lines 950 may cover the pointed protrusions 650c on the floating gates 650.

Subsequently, after forming a photoresist pattern exposing the cell active regions 140 between the word lines 950, a predetermined impurity is injected into the exposed cell active regions 140 to drain the region 145. Form them.

Referring back to FIGS. 12A and 12B, split gate type flash memory cells according to another embodiment of the present invention will be described.

The split gate type flash memory cells include an active region 150 defined in a predetermined region of the semiconductor substrate 100. The active region 150 includes a plurality of common source line active regions 130 and a plurality of cell active regions 140 crossing the common source line active regions 130. Common source regions 135 having a line shape doped with a predetermined impurity are positioned on surfaces of the common source line active regions 130.

A pair of floating gates 650 spaced apart from each other are disposed on the cell active regions 140. The floating gates 650 have a spacer shape. In other words, each of the floating gates 650 has a vertical sidewall 650a and an inclined sidewall 650b. The inclined sidewalls 650b are adjacent to the common source regions 135. The vertical sidewalls 650a are located opposite the common source regions 135. In addition, each of the floating gates 650 has a pointed protrusion 650c on which the vertical sidewall 650a and the inclined sidewall 650a meet each other.

The insulating layer spacer 750a is disposed on the vertical sidewalls 650a of the floating gates 650. In addition, the insulating layer spacer 750b is disposed on the remaining sidewalls of the floating gates 650.

In addition, the floating gates 650 have horizontal extensions p. The horizontal extensions p protrude from lower regions of the vertical sidewalls 650a, and lower surfaces of the insulating layer spacers 750a formed on the vertical sidewalls 650a and the cell active regions 140. It is interposed in between.

A gate insulating layer 200 is interposed between the floating gates 650 and the cell active region 140. The gate insulating film 200 may be a thermal oxide film or a CVD oxide film, and the thickness thereof is preferably 50 to 100 GPa.

At least the vertical sidewalls 650a are covered with word lines 950. The word lines 950 extend to cross the cell active regions 140. As a result, a pair of parallel word lines 950 are disposed between the common source line active regions 130 adjacent to each other.

A tunnel insulating layer 800 is interposed between the word lines 950 and the floating gates 650. In addition, the tunnel insulating layer 800 is interposed between the word lines 950 and the cell active regions 140. The tunnel insulating film 800 may be a thermal oxide film or a CVD oxide film, the thickness is preferably 100 to 300 내지.

Drain regions 145 doped with a predetermined impurity are positioned on surfaces of the cell active regions 140 between the word lines 950.

The word lines 950 may cover the pointed protrusions 650c. In this case, when a positive erase voltage is applied to the word lines 950 and the common source region 135 and the drain region 145 are grounded, an electric field is applied to the protrusions 650c. Are concentrated. As a result, the efficiency of injecting electrons in the floating gates 650 into the wordlines 950 may be significantly increased. In other words, when the protrusions 650c overlap with the word lines 950, the erase efficiency of the flash memory cell is remarkably improved.

As described above, according to the present invention, a margin for a resolution limit of a photo process is formed by forming a floating gate in the form of a spacer using a sacrificial layer pattern without forming a corresponding photoresist opening. It is possible to reduce the dependency of photo processing equipment such as corner rounding caused by the lack of photoresist openings. Therefore, it is easy to form a floating gate having a width smaller than the resolution limit of the photolithography process, thereby enabling the implementation of a highly integrated flash memory device.

1 is a plan view showing a portion of a conventional split gate type flash memory cell array region.

2A through 2C are cross-sectional views illustrating a method of manufacturing a conventional split gate type flash memory cell taken along the cutting line I-I of FIG. 1.

3A, 4A, 5A, and 6A are plan views illustrating a method of manufacturing split gate type flash memory cells according to process steps, according to an exemplary embodiment.

3B, 4B, 5B, and 6B are cross-sectional views taken along the cutting line I-I of FIGS. 3A, 4A, 5A, and 6A, respectively.

7A, 8A, 9A, 10A, 11A, and 12A are plan views illustrating a method of manufacturing split gate type flash memory cells according to process steps, according to another exemplary embodiment.

7B, 8B, 9B, 10B, 11B, and 12B are cross-sectional views taken along the cutting line I-I of FIGS. 7A, 8A, 9A, 10A, 11A, and 12A, respectively.

(Explanation of symbols for main parts of drawing)

100: semiconductor substrate 130: common source line active region

140: cell active area 150: active area

200: gate insulating film 650: floating gate

750a and 750b insulating film spacer 800 tunnel insulating film

950: wordline

Claims (9)

An isolation layer formed on the semiconductor substrate to define an active region; A floating gate in the form of a spacer disposed on the active region and having a vertical sidewall and an inclined sidewall; A word line overlapping at least the vertical sidewall and crossing the active area; An insulating film spacer interposed between the vertical sidewall and the word line; A source region formed in the active region adjacent to the inclined sidewall and positioned opposite the word line; And And a drain region formed in the active region adjacent to the word line and positioned opposite to the source region, wherein the floating gate protrudes from a lower region of the vertical sidewall and between the lower surface of the insulating layer spacer and the active region. A flash memory cell having a horizontal extension interposed therein. delete The method of claim 1, A gate insulating layer interposed between the floating gate and the active region; And And a tunnel insulating layer interposed between the floating gate and the word line and between the word line and the active region. The method of claim 1, And the insulating film spacer is an oxide film. Forming an isolation layer on a semiconductor substrate to define an active region, Forming a gate insulating film on the entire surface of the semiconductor substrate including the active region; Forming a floating gate overlapping the active region on the gate insulating layer, wherein the floating gate includes at least a spacer-shaped floating gate having a vertical sidewall and an inclined sidewall, Forming a tunnel insulating film on the entire surface of the substrate including the floating gate; Forming a word line overlapping at least the vertical sidewall on the tunnel insulating layer and crossing the active region; The floating gate may be formed by forming a lower floating gate layer on an entire surface of the semiconductor substrate having the gate insulating layer, forming a sacrificial layer pattern crossing the active region on the lower floating gate layer, and forming the sacrificial layer pattern. An upper floating gate layer is formed on the entire surface of the semiconductor substrate, and the upper and lower floating gate layers are anisotropically etched to cover the sidewalls of the sacrificial layer pattern. A lower preliminary floating gate remaining on the lower portion is formed, and the sacrificial layer pattern is removed to expose a vertical sidewall of the upper preliminary floating gate and an upper surface of the lower preliminary floating gate, and an insulating layer spacer is disposed on the vertical sidewall. And using the insulating film spacer as an etching mask. And etching the lower preliminary floating gate to form a lower floating gate remaining under the upper preliminary floating gate and under the insulating layer spacer. delete delete The method of claim 5, And the sacrificial layer pattern is formed of a nitride layer. The method of claim 5, And the insulating film spacer is formed of an oxide film.