KR20040083836A - Method for scanning wafer on semiconductor fabrication process - Google Patents

Abstract

PURPOSE: A method for scanning a wafer in a semiconductor fabrication process is provided to reduce OSC errors of a wafer and improve productivity by scanning ion beams to the parallel direction or to the vertical direction to the flat zone. CONSTITUTION: A semiconductor wafer includes a transistor cell array(100). A flat zone is formed on one side of the transistor cell array. The transistor cell array is parallel to the flat zone. An ion beam scanning process for the semiconductor wafer is performed to the parallel direction to the flat zone or to the vertical direction to the flat zone. The ion beam scanning process corresponds to a controlled threshold voltage ion implantation process.

Description

Method for scanning wafer on semiconductor fabrication process

The present invention relates to a wafer scanning method of a semiconductor manufacturing process.

In recent years, more precise impurity control is required to cope with higher integration and higher density of semiconductor devices, and furthermore, in terms of technology, reproducibility and processing capability are required to be improved. Among them, ion implantation technology is becoming more and more important, and it has been put to practical use in place of the prior art.

Ion implantation is a semiconductor manufacturing technology that injects an appropriate amount of impurities into a desired region by making impurities into an ionic state and then accelerating them to scan a specific portion on the semiconductor substrate. Ion implantation technology has the advantage that it is possible to selectively implant the impurity, precise control of the impurity concentration, excellent reproducibility and uniformity.

1 is a schematic view showing a conventional ion implantation apparatus.

As shown in FIG. 1, a typical ion implanter includes an ion source 1, a mass analyzer 2, a beam accelerator 3, a focus lens 4, an electrostatic classifier 5, and a Y-axis. A syringe 6, a gate 7, an X-axis syringe 8 and a wafer scanning device 9 are provided.

The ion beam emitted from the ion generator 1 passes through the mass spectrometer 2 to remove ions of unwanted type. The mass spectrometer 2 functions to select and pass only a desired ion beam using different principles of diffraction effects even if the ions having the same energy in the magnetic field have different masses. The ion beam passing through the mass spectrometer 2 is accelerated to have a desired energy during ion implantation while passing through the beam accelerator 3. The ion beam accelerated while passing through the beam accelerator 3 is focused by the focus lens 4, and the neutral beam is removed by the electrostatic classifier 5 again. The ion beam passing through the electrostatic classifier 5 passes through the Y-axis syringe 6, the gate 7, and the X-axis syringe 8 to finally reach the semiconductor wafer 10 mounted on the wafer scanning device 9. Done. The wafer scanning device 9 is a device in which an ion beam is scanned on the entire surface of the wafer 8 by mounting the wafer 10 and moving a predetermined distance, that is, within a scanning range.

2 is a plan view showing a scanning line by conventional wafer scanning.

As shown in FIG. 2, a scan line S for scanning an ion beam onto a wafer 10 of an LCD Drive IC (hereinafter referred to as LDI) is shown. Here, the X axis is a direction parallel to the plane on which the flat zone 10a is formed.

The scan line S is parallel to the V direction. The V direction is a direction inclined at 45 degrees with respect to the X axis. That is, the ion beam scan is inclined at 45 degrees with respect to the flat zone. The ion beam scan frequency is divided into an X-scan frequency and a Y-scan frequency. In general, the X-scan frequency from the scan line S1 to the scan line S2 is about 1000 Hz, and once the scan is completed on the wafer 10 from the scan line S1, The Y-scan frequency returning to the scan line S1 is around 100 Hz. The time to complete all scans on the wafer 10 usually takes 10 seconds.

The ion beam scanning method is commonly applied in a process in which ion implantation is performed in the manufacturing process of the wafer 10.

However, conventional ion beam scans for LDI series wafers have the following problems.

3 is a plan view showing a defective state of an LDI series wafer manufactured by a conventional ion beam scanning method.

As shown in FIG. 3, on the LDI series wafer 20 manufactured by a conventional ion beam scanning method, an oscillation signal defect (hereinafter, referred to as' OSC defect) in an OSC block is performed along the same direction as the V direction, which is an ion beam scan direction. A large number of defective chips 20a appear. Therefore, the problem that the yield in a semiconductor manufacturing process falls significantly arises.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an ion implantation method of a semiconductor manufacturing process which is improved to reduce signal defects of semiconductor chips in an LDI series wafer.

1 is a schematic view showing a conventional ion implantation apparatus.

2 is a plan view showing a scanning line by conventional wafer scanning.

3 is a plan view showing a defective state of an LDI series wafer manufactured by a conventional ion beam scanning method.

Fig. 4A is a plan view showing a LDI series S6B0723A model wafer.

FIG. 4B is a plan view illustrating an ion beam scan region for region A1 of FIG. 4A.

FIG. 5 is a beam profile of the ion beam for II ′ in FIG. 4B.

Fig. 6A is a plan view showing an LDI series S6B0724A model wafer.

FIG. 6B is a plan view illustrating an ion beam scan region for region A2 of FIG. 6A.

<Description of the symbols for the main parts of the drawings>

30: S6B0723A Model Wafer

40: S6B0724A Model Wafer

30a, 40a: flat zone

100: first transistor cell array

101 to 130: first to thirtieth transistor cells

60, 70, 80, and 90: first, second, third, and fourth ion beam scan areas

In an ion implantation method of a semiconductor manufacturing process according to the present invention, a flat zone is formed on one side, and an ion beam is scanned on a wafer including a transistor cell array arranged in a direction parallel to the flat zone. A wafer scanning method of a semiconductor manufacturing process, characterized by scanning an ion beam with respect to the wafer in a direction parallel or perpendicular to the flat zone.

The ion implantation method of the semiconductor manufacturing process according to the present invention includes a transistor cell array in which a flat zone is formed on one side and arranged in a direction parallel to the flat zone, and a controlled threshold ion implantation process (controlled threshold) A wafer scanning method of a semiconductor manufacturing process in which an ion beam is scanned on a wafer manufactured by a semiconductor manufacturing process including a voltage ion implantation process, wherein the ion beam is scanned on the wafer in a direction parallel or perpendicular to the flat zone. It is characterized in that it is carried out in the controlled threshold voltage ion implantation process.

According to a preferred embodiment of the present invention, it is characterized by including an over scan method in which the focusing of the ion beam on the wafer is overlapped.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The ion implantation process in the manufacturing process of LDI series wafers includes N-well ion implantation process, P-well ion implantation process, depletion N-MOS process, and depli Sean P-MOS process, low threshold voltage N-ion implantation process, first low threshold voltage P-ion implantation process, second low threshold voltage P-ion implantation process, A controlled threshold voltage ion implantation process (hereinafter referred to as a CVt IIP process) and a source drain process are included.

Here, CVt IIP process becomes a process with the lowest dose amount. In other words, the CVt IIP process has the lowest density of implanted ions. In the CVt IIP process, ion energy is 80 KeV and ion dose is 2.2x10 ¹² (piece / cm <2>).

In the ion implantation scanning according to the present invention, the scanning direction of the ion implantation process is parallel to the X axis in FIG. 2 only in the CVt IIP process, and the ion implantation scanning direction is different from the conventional ion implantation process. Likewise parallel to the V direction in FIG. That is, the ion implantation scanning direction is parallel to the X axis in FIG. 2 only in the ion implantation process with the lowest ion dose.

Hereinafter, the ion implantation scanning in the CVt IIP process will be described in the above-described ion implantation process according to the present invention.

FIG. 4A is a plan view illustrating an LDI series S6B0723A model wafer, and FIG. 4B is a plan view illustrating an ion beam scan region for the A1 region of FIG. 4A.

As shown in FIG. 4A, the charge P-transistor area A1 included in the OSC block in the LDI series S6B0723A model wafer 30 is shown.

As shown in FIG. 4B, the first transistor cell array 100 is disposed in the charge P-transistor region A1. For reference, model S6B0723A is an LDI product manufactured by Samsung Electronics.

The first transistor cell array 100 includes thirty first to thirty transistor cells 101 to 130. The first to thirtieth transistor cells 101 to 130 are arranged in a line along the X axis in parallel with the flat zone (30a in FIG. 4A).

The ion beam scan according to the present invention is an over scan method in which focusing on the first ion beam scan region 60 and the second ion beam scan region 70 overlaps each other with respect to the first transistor cell array 100. The ion beam scan according to the present invention is performed in a direction parallel to the array direction of the first transistor cell array 100. That is, scanning is performed in the X-axis direction of FIG. 4A. Although not shown in the drawings, the scan may be performed in a direction perpendicular to the arrangement direction of the first transistor cell array 100.

FIG. 5 is a beam profile of the ion beam for II ′ in FIG. 4B.

As shown in FIG. 5, the inclined portion 60a for the beam profile of the first ion beam scan region 60 and the inclined portion 70b for the beam profile of the second ion beam scan region 70 overlap each other and are dotted. An overlapping beam profile portion 65 is indicated. Here, the B direction refers to a direction in which the intensity of the beam is large.

By the overlapping beam profile portion 65, the ion concentration injected into the wafer during ion beam scanning may be relatively uniform. Theoretically, the overlapping beam profile portion 65 should have the same height as the surrounding beam profile and have a flat shape, but the current focusing techniques fall short of performing an ion beam scan to do so.

In addition to the above-described overscan method, there is a sharp scan method in which the pitches of the first ion beam scan area 60 and the second ion beam scan area 70 are further widened and scanned, but the variation of the quality characteristics of the wafer is not limited to the over scan method. There is a problem that grows significantly.

FIG. 6A is a plan view illustrating an LDI series S6B0724A model wafer, and FIG. 6B is a plan view illustrating an ion beam scan region for the A2 region of FIG. 6A.

As shown in FIG. 6A, a charge P-transistor area A2 included in the OSC block in the LDI series S6B0724A model wafer 40 is shown.

As shown in FIG. 6B, a second transistor cell array 200 is disposed in the charge P-transistor region A2. For reference, model S6B0724A is an LDI product manufactured by Samsung Electronics.

The second transistor cell array 200 includes thirty thirty-first through sixty transistor cells 201 through 230. The thirty first to sixty transistor cells 201 to 230 are arranged in a line along the X axis in parallel with the flat zone (40a in FIG. 6A).

The ion beam scan according to the present invention is an overscan method in which the third ion beam scan region 80 and the fourth ion beam scan region 90 overlap each other with respect to the second transistor cell array 200. The ion beam scan according to the present invention is performed in a direction parallel to the array direction of the second transistor cell array 200. That is, scanning is performed in the Y axis direction. Although not shown in the drawings, the scan may be performed in the X-axis direction perpendicular to the arrangement direction of the second transistor cell array 200.

Hereinafter, the results of the wafer scanning according to the present invention will be described.

Table 1 compares the conventional ion implantation method of the S6B0723A model wafer among the LDI series wafers and the yield and OSC defect rate of each wafer according to the ion implantation method according to the present invention.

Model S6B0723A yield(%) OSC Defective Rate (%) Conventional The present invention Conventional The present invention applied amount 256 45 256 45 Average 88.30 90.97 5.43 1.61 Standard Deviation 7.69 3.94 8.19 2.76

Table 2 compares the yield and OSC defect rate of each wafer according to the conventional ion implantation method and the ion implantation method according to the present invention in the S6B0724A model wafer among the LDI series wafers.

Model S6B0724A yield(%) OSC Defective Rate (%) Conventional The present invention Conventional The present invention applied amount 375 16 375 16 Average 89.00 92.37 2.51 0.05 Standard Deviation 6.91 1.82 5.03 0.07

Table 3 compares the yield and OSC defect rate of each wafer according to the conventional ion implantation method and the ion implantation method according to the present invention in the S6B0759X model wafer among the LDI series wafers. For reference, the S6B0759X is an LDI product manufactured by Samsung Electronics.

Model S6B0759X yield(%) OSC Defective Rate (%) Conventional The present invention Conventional The present invention applied amount 159 13 159 13 Average 89.16 92.61 2.36 0.43 Standard Deviation 6.57 1.85 4.52 0.88

As shown in Tables 1 to 3, the wafer scanning method according to the present invention compared to the conventional wafer scanning method, the wafer yield is improved by 2-3%, the OSC defect rate is also improved to around 2%. have. In particular, it can be seen that the semiconductor manufacturing process is more stabilized because the yield and OSC defect variation on the wafer are significantly reduced.

The cause analysis for these results is as follows

First, the problem that the CVt IIP process is the owner of the ion implantation process in the semiconductor manufacturing process is inferred because the uniformity of the ion beam is the most unstable because the CVt IIP process is the lowest in the ion implantation process.

Second, in the CVt IIP process, the ion beam scanning should be performed only in a specific direction. Referring to FIG. 4B, when the ion beam scanning is performed in a direction parallel or perpendicular to the arrangement direction of the first transistor cell array 100, the ion beam is scanned. Even when scan haunting occurs due to scanning, there is no difference in doping concentration between adjacent transistor cells in the first transistor cell array 100. Therefore, it is inferred that the threshold voltage Vt and the drain current Id are made uniform between adjacent transistors, thereby suppressing OSC defects.

As mentioned above, although the preferred embodiment for illustrating the principle of this invention was shown and demonstrated, this invention is not limited to the structure and operation as it was shown and described. Rather, those skilled in the art will appreciate that various changes and modifications can be made to the present invention without departing from the spirit and scope of the appended claims. Accordingly, all such suitable changes, modifications, and equivalents should be considered to be within the scope of the present invention.

In the wafer scanning method of the semiconductor manufacturing process according to the present invention, by scanning the ion beam in a direction parallel or perpendicular to the arrangement direction of the array of transistor cells in the wafer, the OSC defect of the wafer is reduced and the yield is improved, thereby improving the efficiency of the semiconductor manufacturing process. This has the advantage of being improved.

Claims (3)

In a wafer scanning method of a semiconductor manufacturing process, a flat zone is formed on one side, and an ion beam is scanned on a wafer including a transistor cell array arranged in a direction parallel to the flat zone. And scanning an ion beam with respect to the wafer in a direction parallel or perpendicular to the flat zone. A flat zone is formed on one side, and includes a transistor cell array arranged in a direction parallel to the flat zone, and by a semiconductor manufacturing process including a controlled threshold voltage ion implantation process. In the wafer scanning method of the semiconductor manufacturing process which scans an ion beam with respect to the manufactured wafer, And scanning the ion beam with respect to the wafer in a direction parallel or perpendicular to the flat zone is performed in the controlled threshold voltage ion implantation process. The method of claim 2, further comprising an over scan method in which focusing of the ion beams on the wafer is overlapped.