KR20040082218A - Method For Manufacturing The CMOS Transitor - Google Patents
Method For Manufacturing The CMOS Transitor Download PDFInfo
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- KR20040082218A KR20040082218A KR1020030016908A KR20030016908A KR20040082218A KR 20040082218 A KR20040082218 A KR 20040082218A KR 1020030016908 A KR1020030016908 A KR 1020030016908A KR 20030016908 A KR20030016908 A KR 20030016908A KR 20040082218 A KR20040082218 A KR 20040082218A
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Abstract
Description
본 발명은 CMOS형 트랜지스터에 관한 것으로서, 특히, 고에너지, 고효율의 이온주입장치를 사용하여 웨이퍼의 내부에 피모스트랜지스터와 엔모스트랜지스터를 3차원적으로 대칭적으로 형성하므로 소자의 집적도를 증대하도록 하는 3차원 CMOS 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS transistor, and in particular, by using a high energy, high efficiency ion implantation device, a three-dimensional symmetrical formation of a PMOS transistor and an NMOS transistor inside a wafer is performed so as to increase the device integration. It relates to a three-dimensional CMOS transistor manufacturing method.
일반적으로, 반도체소자의 집적도가 증가함에 따라 CMOS트랜지스터가 칩 전체 면적에서 차지하는 면적을 줄여야 하는 문제가 발생하고, 또한, 게이트전극의 선폭과 두께가 작아져서 게이트전극의 저항이 증대되어 반도체소자의 동작속도가 느려지는 문제가 발생되고 있다.In general, as the degree of integration of a semiconductor device increases, a problem arises in that the CMOS transistor needs to reduce the area occupied in the entire area of the chip. In addition, the line width and thickness of the gate electrode decrease, which increases the resistance of the gate electrode, thereby increasing the operation of the semiconductor device. There is a problem of slowing down.
종래에는 CMOS소자의 게이트전극은 실리콘 기판 위에 산화막을 증착한 다음, 단지 폴리실리콘게이트막을 형성하는 방법을 주로 이용하였으며, 엔모스트랜지스터와 피모스트랜지스터가 반도체기판의 상부면에 인접하여 형성되어진다.Conventionally, a gate electrode of a CMOS device mainly uses a method of depositing an oxide film on a silicon substrate, and then forming only a polysilicon gate film, and an NMOS transistor and a PMOS transistor are formed adjacent to the upper surface of the semiconductor substrate.
도 1은 종래의 일반적인 CMOS형 트랜지스터의 구조를 보인 도면이다.1 is a view showing the structure of a conventional general CMOS transistor.
종래의 CMOS 트랜지스터의 제조방법은, 반도체기판(1)상에 NMOS와 PMOS에 이온을 각각 주입하여 웰영역(2)을 형성하도록 한다.In the conventional method of manufacturing a CMOS transistor, the well region 2 is formed by implanting ions into the NMOS and the PMOS on the semiconductor substrate 1, respectively.
그리고, 상기 반도체기판(1) 상에 산화막으로 된 소자분리막(3)을 형성하도록 한다.Then, an element isolation film 3 made of an oxide film is formed on the semiconductor substrate 1.
그리고, 상기 반도체기판(1) 상에 게이트산화막(4)과 게니트전극층(5)을 적층한 후, 식각하여 게이트전극을 형성하도록 한다.The gate oxide layer 4 and the gate electrode layer 5 are stacked on the semiconductor substrate 1 and then etched to form a gate electrode.
그리고, 상기 게이트전극의 양측면부분에 이온을 주입하여 반도체기판(1)에 소오스/드레인영역을 형성하도록 한다.Then, ions are injected into both side portions of the gate electrode to form a source / drain region in the semiconductor substrate 1.
그런데, 상기한 바와 같이, CMOS트랜지스터의 N-WELL에 있는 P형정션영역 및 N형정션영역을 따로 형성하여 소자분리막으로 분리되어지므로 CMOS 트랜지스터의 크기가 커지게 되므로 반도체소자의 칩의 크기가 커지는 문제점을 지니고 있었다.However, as described above, since the P-type junction region and the N-type junction region in the N-WELL of the CMOS transistor are formed separately and separated into device isolation layers, the size of the CMOS transistor increases because the size of the CMOS transistor increases. I had a problem.
본 발명의 목적은 상기한 점을 감안하여 안출한 것으로서, 고에너지, 고효율의 이온주입장치를 사용하여 웨이퍼의 내부에 피모스트랜지스터와 엔모스트랜지스터를 3차원적으로 대칭적으로 형성하므로 소자의 집적도를 증대하도록 하는 것이 목적이다.The object of the present invention was devised in view of the above, and the integration degree of the device is formed by symmetrically forming the PMOS transistor and the NMOS transistor in the wafer using a high energy and high efficiency ion implantation device. The purpose is to increase the number.
도 1은 종래의 일반적인 CMOS형 트랜지스터의 구조를 보인 도면이고,1 is a view showing the structure of a conventional general CMOS transistor,
도 2 내지 도 16은 본 발명에 따른 CMOS형 트랜지스터 제조방법을 순차적으로 보인 도면이다.2 through 16 are views sequentially showing a method of manufacturing a CMOS transistor according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체기판 12 : 피웰영역10 semiconductor substrate 12 pewell region
14 : 감광막 16 : 엔모스소오스/드레인영역14 photosensitive film 16 NMOS source / drain region
22 : 피모스전극 26 : 소자분리막22: PMOS electrode 26: device isolation film
28 : 게이트산화막 32 : 게이트전극28: gate oxide film 32: gate electrode
36 : 격리막 38 : 게이트산화막36: separator 38: gate oxide film
40 : 감광막 42 : 소자분리막40: photosensitive film 42: device isolation film
46 : 엔웰영역 50 : 피모스소오스/드레인영역46: Enwell area 50: PMOS source / drain area
54 : 엔모스전극 58 : 절연막플러그54 NMOS electrode 58 Insulation plug
60 : 감광막 62 : 콘택홀60: photosensitive film 62: contact hole
64 : 메탈전극64: metal electrode
이러한 목적은, 반도체소자의 CMOS형성방법에 있어서, 반도체기판 상에 감광막을 증착하고, 피모스가 형성될 부분에 반도체기판 내부에 보론을 주입하여 피웰영역을 형성한 후, 감광막을 통하여 상기 피웰영역에 포스포러스이온을 주입하여 엔모스 소오스/드레인영역을 형성하는 단계와; 상기 단계 후에 상기 엔모스 소오스/드레인영역의 인접 부분에 감광막을 통하여 이온을 주입하여 엔모스전극을 형성한 후, 감광막을 통하여 이온을 주입하여 상기 엔모스 소오스/드레인영역과 엔모스전극 사이에 소자분리막을 형성하는 단계와; 상기 단계 후에 상기 반도체기판의 상부면에 이온을 주입하여 게이트산화막을 적층한 후, 연속하여 감광막을 통하여 게이트전극을 형성하는 단계와; 상기 단계 후에 상기 반도체기판 상에 산소이온을 주입하여 엔모스영역과 격리되는 격리막을 형성한 후, 상기 격리막 상에 이온을 주입하여 게이트산화막을 형성하는 단계와; 상기 단계 후에 상기 반도체기판 상에 감광막을 적층하고 이온을 주입하여 소자분리막을 형성한 후, 감광막을 통하여 포스포러스이온을 주입하여 엔웰영역을 형성하는 단계와; 상기 단계 후에 상기 반도체기판 상에 감광막을 적층하여 보론이온을 주입하여 소자분리막사이에 피모스 소오스/드레인영역을 형성한 후, 재차 감광막(52)을 통하여 포스포러스 이온을 주입하여 엔모스전극을 형성하는 단계와; 상기 단계 후에 상기 결과물 상에 감광막을 통하여 상기 피모스 소오스/드레인영역으로 연결되는 콘택홀을 형성한 후, 콘택홀에 산소이온을 주입하여 절연막플러그를 형성하는 단계와; 상기 단계 후에 상기 절연막플러그의 중심부분에 감광막을 통하여 식각하여 콘택홀을 형성한 후, 상기 콘택홀 내에 금속을 매립하여 상기 피모스 소오스/드레인영역에 연결되는 메탈전극을 형성하는 단계를 포함하여 이루어진 3차원 CMOS 트랜지스터 제조방법을 제공함으로써 달성된다.In the CMOS forming method of a semiconductor device, a photosensitive film is deposited on a semiconductor substrate, a boron is injected into a semiconductor substrate at a portion where a PMOS is to be formed, and then a pwell region is formed through the photowell film. Implanting phosphorus ions into the MOS source / drain regions; After the step, the ion is implanted through the photosensitive film to the adjacent portion of the NMOS source / drain region to form an NMOS electrode, and then the ion is implanted through the photosensitive film to form a device between the NMOS source / drain region and the NMOS electrode. Forming a separator; After the step of laminating a gate oxide film by implanting ions into the upper surface of the semiconductor substrate, and subsequently forming a gate electrode through the photosensitive film; Injecting oxygen ions onto the semiconductor substrate to form an isolation layer that is isolated from the NMOS region after the step, and then implanting ions on the isolation layer to form a gate oxide layer; Stacking a photoresist film on the semiconductor substrate and implanting ions to form a device isolation film after the step; After the above step, a photoresist film is stacked on the semiconductor substrate to inject boron ions to form a PMOS source / drain region between the device isolation layers, and then phosphorus ions are injected again through the photoresist layer 52 to form an NMOS electrode. Making a step; After the step of forming a contact hole connected to the PMOS source / drain region through the photosensitive film on the resultant, and forming an insulating film plug by injecting oxygen ions into the contact hole; And forming a contact hole by etching a photoresist in the central portion of the insulating film plug after the step, and then filling a metal into the contact hole to form a metal electrode connected to the PMOS source / drain region. It is achieved by providing a three-dimensional CMOS transistor manufacturing method.
그리고, 상기 소자분리막은, 산소이온을 주입 산화하여 형성하는 것이 바람직 하다.The device isolation layer is preferably formed by implanting and oxidizing oxygen ions.
그리고, 상기 게이트산화막은, 산소이온을 주입 산화하여 형성하도록 한다.The gate oxide film is formed by implanting and oxidizing oxygen ions.
또한, 상기 엔모스영역과 피모스영역을 분리하는 격리막은, 산소이온을 주입산화하여 형성하도록 한다.In addition, the separator that separates the NMOS region and the PMOS region is formed by implanting and oxidizing oxygen ions.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2에 도시된 바와 같이, 반도체기판(10) 상에 감광막(14)을 증착하고, 피모스(P-MOS)가 형성될 부분에 반도체기판(10) 내부에 보론(Boron)이온을 주입하여 피웰(P-WELL)영역(12)을 형성하도록 한다.As shown in FIG. 2, the photoresist film 14 is deposited on the semiconductor substrate 10, and boron ions are injected into the semiconductor substrate 10 at a portion where the P-MOS is to be formed. The P-WELL region 12 is formed.
그리고, 도 3에 도시된 바와 같이, 상기 반도체기판(10) 상에 감광막(18)을 증착하고 개방하여 상기 피웰영역(12)에 포스포러스(Phosphrous)이온을 주입하여 상기 피웰영역(12) 내에 엔모스 소오스/드레인영역(16)을 형성하도록 한다.As shown in FIG. 3, a photoresist film 18 is deposited on the semiconductor substrate 10 and opened to inject phosphor ions into the pwell region 12, thereby forming a photoresist 18 in the pewell region 12. The NMOS source / drain regions 16 are formed.
그리고, 도 4에 도시된 바와 같이, 상기 엔모스 소오스/드레인영역(16)의 인접 부분에 감광막(20)을 통하여 보론이온을 주입하여 엔모스전극(22)을 형성하도록한다.As shown in FIG. 4, boron ions are injected into the adjacent portion of the NMOS source / drain region 16 through the photosensitive film 20 to form the NMOS electrode 22.
그리고, 도 5에 도시된 바와 같이, 상기 반도체기판(10) 상에 감광막(24)을 통하여 산소이온을 주입하여 상기 엔모스 소오스/드레인영역(16)과 엔모스전극(22) 사이에 소자분리막(26)을 형성하도록 한다.As shown in FIG. 5, an oxygen ion is implanted on the semiconductor substrate 10 through the photosensitive film 24 to separate the device isolation layer between the NMOS source / drain region 16 and the NMOS electrode 22. (26) to form.
도 6에 도시된 바와 같이, 상기 반도체기판(10)의 상부 전체면에 산소이온을 주입하여 게이트산화막(28)을 적층하도록 한다.As shown in FIG. 6, oxygen ions are injected into the entire upper surface of the semiconductor substrate 10 to stack the gate oxide layer 28.
도 7에 도시된 바와 같이, 상기 반도체기판(10) 상에 연속하여 감광막(30)을 증착하여 식각한 후, 게이트산화막(28) 상에 포스포러스이온을 주입하여 게이트전극(32)을 형성하도록 한다.As shown in FIG. 7, the photoresist layer 30 is sequentially deposited and etched on the semiconductor substrate 10, and then phosphorus ions are implanted onto the gate oxide layer 28 to form the gate electrode 32. do.
그리고, 도 8에 도시된 바와같이, 상기 반도체기판(10) 상에 산소이온을 주입하여 엔모스영역과 격리되도록 상기 게이트전극(32)을 제외한 부분에 격리막(36)을 형성하도록 한다.As shown in FIG. 8, the isolation layer 36 is formed on portions of the semiconductor substrate 10 except for the gate electrode 32 to be insulated from the NMOS region by injecting oxygen ions.
그리고, 도 9에 도시된 바와 같이, 상기 결과물의 격리막(36) 상에 상소 이온을 주입하여 게이트산화막(38)을 형성하도록 한다.And, as shown in Figure 9, by implanting the ions on the isolation layer 36 of the resultant to form a gate oxide film 38.
그리고, 도 10에 도시된 바와 같이, 상기 반도체기판(10) 상에 감광막(40)을 적층하여 이온을 주입하여 소자분리막(42)을 형성하도록 한다.As shown in FIG. 10, the photosensitive film 40 is stacked on the semiconductor substrate 10 to implant ions to form the device isolation film 42.
그리고, 도 11에 도시된 바와 같이, 상기 반도체기판(10)상에 감광막(44)을 적층하여 식각한 후, 개방부를 통하여 포스포러스 이온을 주입하여 엔웰(N-WELL)영역(46)을 형성하도록 한다.As shown in FIG. 11, after the photoresist layer 44 is stacked and etched on the semiconductor substrate 10, phosphorus ions are implanted through the opening to form an N-WELL region 46. Do it.
그리고, 도 12에 도시된 바와 같이, 상기 반도체기판(10) 상에 감광막(48)을 적층하여 식각으로 개방한 후, 보론이온을 주입하여 소자분리막(42)사이에 피모스 소오스/드레인영역(50)을 형성하도록 한다.As shown in FIG. 12, the photoresist film 48 is stacked on the semiconductor substrate 10 to be etched, and then boron ions are implanted to form a PMOS source / drain region between the device isolation layers 42. 50).
그리고, 도 13에 도시된 바와 같이, 감광막(52)을 통하여 포스포러스 이온을 주입하여 소자분리막(42) 사이에 엔모스전극(54)을 형성하도록 한다.As shown in FIG. 13, phosphorus ions are implanted through the photosensitive film 52 to form the NMOS electrode 54 between the device isolation layers 42.
그리고, 도 14에 도시된 바와 같이, 상기 결과물 상에 감광막(56)을 통하여 상기 피모스 소오스/드레인영역(50)으로 연결되는 콘택홀을 형성한 후, 콘택홀 산소이온을 주입하여 절연막플러그(58)를 형성하도록 한다.As shown in FIG. 14, after forming a contact hole connected to the PMOS source / drain region 50 through the photoresist layer 56 on the resultant product, contact hole oxygen ions are injected to form an insulating film plug ( 58).
그리고, 도 15에 도시된 바와 같이, 상기 절연막플러그(58)의 중심부분에 감광막(60)을 통하여 상기 피모스 소오스/드레인영역(50)에 연결되는 콘택홀(62)을형성하도록 한다.As shown in FIG. 15, a contact hole 62 connected to the PMOS source / drain region 50 is formed in the central portion of the insulating film plug 58 through the photosensitive film 60.
그리고, 상기 콘택홀(62) 내에 금속을 매립하여 상기 피모스 소오스/드레인영역(50)에 연결되는 메탈전극(64)을 형성하도록 한다.A metal electrode 64 connected to the PMOS source / drain region 50 may be formed by filling metal in the contact hole 62.
상기한 바와 같이, 본 발명에 따른 3차원 CMOS트랜지스터 제조방법을 이용하게 되면, 고에너지, 고효율의 이온주입장치를 사용하여 웨이퍼의 내부에 피모스트랜지스터와 엔모스트랜지스터를 3차원적으로 대칭적으로 형성하므로 소자의 집적도를 증대하도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the three-dimensional CMOS transistor manufacturing method according to the present invention is used, a three-dimensional symmetrical arrangement of the PMOS transistor and the N-MOS transistor inside the wafer using a high-energy, high-efficiency ion implantation apparatus. It is a very useful and effective invention to increase the degree of integration of the device by forming.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100687431B1 (en) * | 2004-12-30 | 2007-02-27 | 동부일렉트로닉스 주식회사 | Manufacturing method of semiconductor device |
| US8600800B2 (en) | 2008-06-19 | 2013-12-03 | Societe Stationnement Urbain Developpements et Etudes (SUD SAS) | Parking locator system including promotion distribution system |
| US9749823B2 (en) | 2009-12-11 | 2017-08-29 | Mentis Services France | Providing city services using mobile devices and a sensor network |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100687431B1 (en) * | 2004-12-30 | 2007-02-27 | 동부일렉트로닉스 주식회사 | Manufacturing method of semiconductor device |
| US8600800B2 (en) | 2008-06-19 | 2013-12-03 | Societe Stationnement Urbain Developpements et Etudes (SUD SAS) | Parking locator system including promotion distribution system |
| US8688509B2 (en) | 2008-06-19 | 2014-04-01 | Societe Stationnement Urbain Developpements Et Etudes (Sude Sas) | Parking locator system providing variably priced parking fees |
| US9749823B2 (en) | 2009-12-11 | 2017-08-29 | Mentis Services France | Providing city services using mobile devices and a sensor network |
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