KR20040080637A - Semiconductor device having improving reliability and method forming the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent short between a plate electrode and a contact plug and to secure photo-misalign margin by forming a spacer at both sidewalls of an insulating layer and a bit line contact hole. CONSTITUTION: A plurality of cell transistors(220) are formed on a substrate(100). The first interlayer dielectric(240) is formed on the cell transistor and provided with a storage node contact pad(260) and a bit line contact pad(280). A plurality of cell capacitors are formed on the first interlayer dielectric and provided with storage electrodes(360) and a dielectric film(380a) and a plate electrode(400a). The second interlayer dielectric is formed on the resultant structure. An insulating layer(480) is formed at end parts of the plate electrode. Spacers(500) are formed at both sidewalls of the insulating layer and a bit line contact hole. The third insulating layer(540a) is formed on the resultant structure. A plurality of bit line plugs(600) are formed in the bit line contact hole to connect the bit line contact pad.

Description

Semiconductor device and method of manufacturing semiconductor device with improved reliability {SEMICONDUCTOR DEVICE HAVING IMPROVING RELIABILITY AND METHOD FORMING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device having improved reliability. It is about.

The development of high-speed information technology has increased the need for high-speed memory. In addition to these needs, the need for memory-megred-logic (MML), which integrates existing memory devices and logic devices onto the same wafer, has been increased to build a system with improved overall performance. Among such MMLs, a chip in which DRAMs and logic elements are integrated together, which enables low-cost high integration, is used.

A DRAM is a semiconductor memory device including a cell array, which is a collection of cells that store information, and a peripheral circuit that transfers information to the outside accurately and quickly. Therefore, an important factor in the DRAM of the semiconductor memory device is the capacitance of the cell capacitor that stores the information. The capacitance of the capacitor that stores the data should be maintained at 25 fF per cell capacitor to prevent loss of stored information due to soft errors or noise by alpha-alpha particles.

In light of this, each company is studying how to use materials with large dielectric constants to increase the charge storage capacity of capacitors, how to reduce the thickness of dielectric materials, and how to increase the surface area of capacitors. The method of increasing the surface area of a capacitor is mainly used. Such high integration of semiconductor devices and high capacity of capacitors cause new problems. In other words, due to the reduction of design rules due to the fabrication of high density and high capacity memory devices, the margin of photo misalignment, bit line contact size, and plate electrode size due to insufficient gap between plate electrode and bit line contact Therefore, there is a problem in reducing the device size by affecting design rules. Insufficient insulation margin between the plate electrode and the bit line contact plug caused the possibility of conduction. Therefore, there is a problem of low yield and reliability.

Accordingly, an object of the present invention is to provide a semiconductor device having an improved structure between a plate electrode and a bit line contact plug in order to solve the above problems.

Another object is to provide a method of manufacturing a semiconductor device having an improved structure between a plate electrode and a bit line contact plug in order to solve the above problems.

1A to 1M are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

<Description of Signs of Main Drawings>

100 semiconductor substrate 120 device isolation region

140: active region 160,180: gate electrode

200: gate protective film 220: gate line (transistor)

240: first interlayer insulating film 260: storage electrode contact pad

280: bit line contact pad 300: etch stop film

320: second interlayer insulating film 340: opening for storage electrode

360: storage electrode 380: dielectric film

400: second conductive film for plate electrode 420: silicon nitride film

420a: hard mask layer 440: first bit line opening

460: second bit line opening 480: insulating layer

500: spacer 520: third bit line opening

540: third interlayer insulating film 560: photoresist pattern

580: bit line contact hole 600: bit line contact plug

In order to achieve the above object, the semiconductor device according to the present invention covers a plurality of cell transistors and the plurality of cell transistors formed on a surface of a semiconductor substrate, and contacts the first contact region (source. SOURCE) of each cell transistor. A storage electrode contact pad of the plurality of cell transistors is formed on the first interlayer insulating layer and the first interlayer insulating layer including a storage electrode contact pad and a bit line contact pad contacting the second contact region (drain, DRAIN). A plurality of cell capacitors having a plurality of storage electrodes in contact with each other, a dielectric layer covering the plurality of storage electrodes, a plate electrode covering the dielectric layer, a second interlayer insulating layer covering the plurality of cell capacitors, and the plurality of storage electrodes. Regions respectively located between the electrodes and overlapping the top portions of the bit line contact pads of the corresponding cell transistors. An insulating layer formed at an end of the plate electrode, a plurality of sidewall spacers formed on each of the sidewalls of the opening, and the second interlayer insulating film and a plurality of sidewalls to insulate an end of the plate electrode exposed to the sidewall of the opening. The bit line contact pad top portion of the cell transistors formed on the lower interlayer insulating layers in a self-aligned manner from the surface of the third interlayer insulating layer covering the spacers and the surface of the third interlayer insulating layer to the bottom interlayer insulating layers in a self-aligned manner. A plurality of bit line plugs are embedded in the exposed bit line contact holes and electrically connected to the bit line contact pads.

A semiconductor device manufacturing method according to the present invention comprises the steps of covering the plate electrodes of the plurality of cell capacitors with a first insulating film, forming a bit line opening in the first insulating layer and the plate exposed on the sidewalls of the bit line openings Forming an exposed end of an electrode as an insulating layer, forming a spacer on a sidewall of the bitline opening, covering the first insulating film and the bitline opening with a second insulating film, and forming the sidewall from the surface of the second insulating film. And forming a bit line contact hole in the lower insulating film in a self-aligned manner through a region defined by a spacer, and forming a bit line plug in the bit line contact hole.

According to the present invention, a plurality of surface treatment insulating layers respectively formed at the ends of the plate electrodes exposed in the bit line openings and a plurality of side wall spacers respectively formed on the sidewalls of the bit line openings are used to form a photo mistliner. Secured. In addition, by preventing conduction between the plate electrode and the bit line contact plug, yield is improved and device reliability is secured.

Hereinafter, with reference to the accompanying drawings will be described in detail according to the present invention.

1A to 1M are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, a shallow trench isolation (STI) process is used to define an active region and an inactive region on a semiconductor substrate 100. That is, when the semiconductor substrate 100 is etched to a predetermined depth to form a trench and the trench isolation layer 120 is filled in the trench, trench isolation is completed and the semiconductor substrate surrounded by the trench isolation layer 120 is active. Is defined as region 140.

The next process is to form a transistor in the semiconductor substrate 100. First, an ion implantation process for adjusting a well and a transistor threshold voltage is performed in a conventional manner.

Next, a transistor 220 including a gate oxide layer (not shown), gate electrodes 160 and 180, and a gate protection layer 200 is formed on the semiconductor substrate 100 by a conventional method. The gate electrode layer is formed of a double layer of metal silicide and polysilicon, and the gate protective layer is formed of a nitride spacer.

After the first interlayer insulating film 240 is deposited on the entire surface of the semiconductor substrate in order to separate the formed transistors in units of cells, etching for planarization is performed to planarize. The first interlayer insulating film is formed of an oxide film.

Next, a storage electrode contact hole (not shown) and a bit line contact hole (not shown) are formed by using a photolithography process to electrically connect the transistor to the storage electrode and the bit line of the capacitor. That is, the first interlayer insulating film between the gate lines is etched through the photolithography process. In addition, the storage electrode contact hole and the bit line contact hole are formed of conductive polysilicon. The conductive polysilicon is subjected to a chemical mechanical polishing (CMP) or etch back process to form a storage electrode contact pad 260 and a bit line contact pad 280.

Next, an etch stop layer 300 is formed. The etch stop layer 300 serves as an etch stop layer when the next capacitor storage electrode is formed. The etch stop layer 300 is formed of silicon nitride.

A second interlayer insulating film 320 (also called a mold oxide film) is formed on the etch stop film 300. The thickness of the second interlayer insulating layer 320 is determined so as to determine the height of the capacitor storage electrode to obtain the desired capacitance.

The second interlayer insulating layer 320 and the etch stop layer 300 are etched to form an opening 340 for a capacitor storage electrode that is connected to a semiconductor substrate (a source region) that is a first contact region of a transistor in the cell region. do.

Next, referring to FIG. 1B, a first conductive layer (not shown) for a capacitor storage electrode is formed on the inside of the opening 340 and the second insulating layer 320. The first conductive film is formed of, for example, a conductive polysilicon or a heat resistant metal such as Ti, Ta, W, or a heat resistant metal compound such as TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, WN. Next, in order to separate the storage electrodes, a node separation process is performed on the first conductive film (not shown) for the storage electrodes to form the storage electrodes 360 separated from each other.

Next, referring to FIG. 1C, the next dielectric layer 380 is formed. A capacitor dielectric layer 380 is sequentially deposited on the node storage device 360 and the second interlayer insulating layer 320. The capacitor dielectric film 380 includes a TiO2 film, a Ta2O5 film, an Al2O3 film, a BaTiO3 film, an SrTiO3 film, a Bi4Ti3O12 film, a PbTiO3 film, a SiO2 film, a (Ba, Sr) TiO3 film, a (Pb, La) (Zr, Ti) O3 film. The Pb (Zr, Ti) O3 film, the SrBi2Ta2O9 film, and any one material film selected from the SiN film and the composite film including the same.

Next, referring to FIG. 1D, TiN is formed as the second conductive layer 400 for the plate electrode on the resultant shown in FIG. 1C. In addition, the second conductive film 400 for a plate electrode may be formed of, for example, a metal film, a metal oxide film, or a composite film thereof. Specifically, the metal film may be a Pt film, an Ir film, a Ru film, an Rh film, an Os film, or a Pd film. The metal oxide film may be a RuO 2 film, an IrO 2 film, a (Ca, Sr) RuO 3 film, or a LaSrCoO 3 film.

Next, referring to FIG. 1E, a silicon nitride film 420 is formed on the second conductive film 400 for the plate electrode.

Next, referring to FIG. 1F, the silicon nitride layer 420 is patterned to form a hard mask layer 420a having a first bit line opening 440 that exposes a bit line forming region between adjacent storage electrodes.

Referring to FIG. 1G, the plate electrode conductive layer is patterned using the hard mask layer as an etching mask to form a plate electrode having a second bit line opening 460.

Referring to FIG. 1H, an exposed sidewall of the plate electrode is surface treated to form an insulating layer 480. At this time, the surface treatment is a PLASMA treatment using oxygen (O2), fluorine (F) and chlorine (Cl) gas to form an insulating layer 480 converted to TiO2, TiF, TiCL and the like.

Next, referring to FIG. 1I, a silicon nitride layer is continuously deposited on the hard mask pattern 420a, the insulating layer 480, and the second interlayer insulating layer 320, and then anisotropically etched to form a spacer 500.

Next, referring to FIG. 1J, a third interlayer insulating layer 540 is formed on the resultant shown in FIG. 1I to fill the third bit line opening 520.

Next, referring to FIG. 1K, a photoresist pattern 560 for forming a bit line contact hole is formed on the third interlayer insulating layer 540.

Next, referring to FIG. 1L, using the photoresist pattern 560 as an etching mask, a second interlayer insulating film 540 and a second interlayer insulating film defined by the spacer 500 are formed on the bit line forming portion. The bit line contact holes 580 exposing the bit line contact pads 280 are sequentially formed by etching 320.

In this case, a process margin may be secured by performing self alignment etching using the insulating layer 480 and the spacer 500 during etching. Specifically, a bit connecting the semiconductor substrate (drain region) on the other side of the transistor in the cell region through the third interlayer insulating layer 540, the spacer 500, the second interlayer insulating layer 320, and the etch stop layer 300. The line contact hole 580 is formed.

Next, referring to FIG. 1M, polysilicon or tungsten is sequentially deposited on the third interlayer insulating layer 540 and the bit line contact hole 580, and then the bit line contact plug is formed by planarization or etching back. 600).

According to the present invention, the photo-misaligned margin is secured by forming the surface treatment insulating layer formed at the end of the plate electrode and the sidewall spacers formed at the sidewall of the bit line opening. In addition, by preventing conduction between the plate electrode and the bit line contact plug, yield is improved and device reliability is secured.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. You can understand that you can.

Claims (6)

Semiconductor substrates; A plurality of cell transistors formed on a surface of the semiconductor substrate; A first interlayer insulating layer covering the plurality of cell transistors and including a storage electrode contact pad contacted with the first contact region of each cell transistor and a bit line contact pad contacted with the second contact region; A plurality of storage electrodes formed on the first interlayer insulating layer and having a plurality of storage electrodes in contact with the storage electrode contact pads of the plurality of cell transistors, a dielectric film covering the plurality of storage electrodes, and a plate electrode covering the dielectric film, respectively. Cell capacitors; A second interlayer insulating film covering the plurality of cell capacitors; Each sidewall of the opening to insulate an end of the plate electrode positioned between the plurality of storage electrodes and exposed to the sidewall of the opening including an area overlapping the top of the bitline contact pad of the corresponding cell transistor. A plurality of sidewall spacers formed; A third interlayer insulating film covering the second interlayer insulating film and the plurality of sidewall spacers; And Is formed in the lower interlayer insulating films in a self-aligned manner through a region defined by the respective sidewall spacers from the surface of the third interlayer insulating film and is buried in the exposed bitline contact hole of the bit line contact pad top of the cell transistor corresponding to the bottom. And a plurality of bit line plugs electrically connected to the bit line contact pads. The semiconductor device according to claim 1, further comprising a plurality of insulating layers formed at the ends of the plate electrodes to insulate the ends of the plate electrodes. The semiconductor device according to claim 2, wherein the plurality of insulating layers formed at the end of the plate electrode is any one selected from TiO 2, TiF, and TiCl. In the method of manufacturing a semiconductor device comprising a plurality of cell transistors and a plurality of cell capacitors, and having a bit line formed on the plurality of cell capacitors, Covering plate electrodes of the plurality of cell capacitors with a first insulating layer; Forming a bit line opening in the first insulating layer; Forming an exposed end of the plate electrode exposed to the sidewall of the bit line opening as an insulating layer; Forming sidewall spacers on sidewalls of the bitline openings; Covering the first insulating layer and the opening with a second insulating layer; Forming a bit line contact hole in the lower insulating film in a self-aligned manner from a surface of the second insulating film to a region defined by the sidewall spacers; And And forming a bit line plug in the bit line contact hole. The method of manufacturing a semiconductor device according to claim 4, wherein TiN is used as plate electrodes of the plurality of cell capacitors. The semiconductor device of claim 4, wherein forming the exposed end of the plate electrode exposed to the sidewall of the bit line opening as an insulating layer is any one selected from among O 2 PLASMA, F PLASMA, and Cl PLASMA processes. Manufacturing method.