KR20040074837A - Semiconductor memory device using charge transferred pre-sensing scheme - Google Patents

Abstract

PURPOSE: A semiconductor device using a CPTS(Charge Transferred Pre-sensing Scheme) is provided to perform a CTPS operation stably without an additional potential generator. CONSTITUTION: According to the semiconductor device(300), the first bit line pair(BL,BLB) are precharged with the first power supply voltage respectively during a precharge operation. The second bit line pair(SBL,SBLB) are precharged with the second power supply voltage respectively during the precharge operation. And a bit line separation circuit(320) connects the first bit line pair and the second bit line pair electrically in response to the first control signal.

Description

Semiconductor device using charge transferred pre-sensing scheme

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly, to a semiconductor device using a charge transfer pre-sensing scheme (CTPS).

In general, semiconductor devices using CTPS have been developed to improve the sensing margin at low power supply voltage.

1 shows a circuit diagram of a semiconductor device having a general CTPS function. For a semiconductor device using the CTPS shown in Fig. 1, Lawrence Heller et al, "High Sensitivity Charge Transfer Sense Amplifier", IEEE JSSC, Vol. SC-11, no. 4, Oct. 1976, pp. It is described in detail in 596-601.

2 is an operation timing diagram for describing an operation of the semiconductor device illustrated in FIG. 1. A semiconductor device using CTPS will be briefly described with reference to FIGS. 1 and 2 as follows.

Here, the capacitor Csa represents a load capacitor of the sense amplifier bit line BLS / A, and the capacitor Cb represents a load capacitor of the cell bit line BLcell.

When control signal φ1 is activated (e.g., logic 'high'), transistor Q1 is turned on, so sense amplifier bitline node BLS / A is precharged to first power supply voltage VH, and the cell The bit line node BLcell is precharged to the voltage VR-Vth minus the threshold voltage Vth of the transistor Q2 from the second power supply voltage VR. At this time, the first power supply voltage VH is higher than the second power supply voltage VR.

Then, when the word line WL is activated, the charge stored in the cell capacitor Cs (for example, the charge corresponding to the data "0 ') is transferred to the cell bit line node BLcell through the transistor Q3 and the bit line BL. In this case, the voltage of the cell bit line node BLcell decreases by ΔV due to charge sharing.

Since charge is transferred from the sense amplifier bit line node BLS / A to the cell bit line node BLcell by the charge transfer transistor Q2, the voltage of the cell bit line node BLcell is changed to the voltage VR-Vth. Restored to its original state.

By the charge transfer operation, the voltage of the sense amplifier bit line node BLS / A is changed by ΔV (Cb + Cs) / Csa.

Accordingly, since the sense amplifier senses and amplifies the voltage variation of the sense amplifier bit line node BLS / A, the sense amplifier can increase the sensing margin even at a low voltage.

However, the semiconductor device using the CTPS shown in FIG. 1 includes a transistor Q1 for precharging the sense amplifier bit line node BLS / A and a first power generator for generating a first power voltage VH (not shown). And a second power generator for generating a second power supply voltage VR. Therefore, the layout area of the semiconductor device is increased.

In addition, since the sense amplifier bit line node BLS / A and the cell bit line node BLcell need to be precharged with the first power supply voltage VH and the second power supply voltage VR, in a semiconductor device using a conventional CTPS. The current consumed is increased.

In addition, semiconductor devices using CTPS are disclosed in detail in US Pat. No. 6,154,402. The semiconductor device disclosed in US Pat. No. 6,154, 402 requires a separate gate potential generator and a bit linepotential generator.

In the semiconductor device disclosed in US Pat. No. 6,154, 402, the gate voltage generator is from Vcc + Vth (V) to 0 (V), from 0 (V) to β + Vth (V) and from β + Vth (V) to Vcc. It is necessary to generate a voltage that is sequentially changed to + Vth (V), and the bit line voltage generator is from 1/2 Vcc (V) to Vcc (1 + γ) (V) and from Vcc (1 + γ) (V) to 1 Generate a voltage that is sequentially variable to / 2Vcc (V).

Therefore, there is a problem in that the output voltage of the gate voltage generator and the output voltage of the bit line voltage generator must be precisely controlled according to each timing.

Accordingly, a technical problem to be achieved by the present invention is to provide a semiconductor memory device that can perform a stable CTPS operation without a separate voltage generator.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 shows a circuit diagram of a semiconductor device having a general CTPS function.

2 is an operation timing diagram for describing an operation of the semiconductor device illustrated in FIG. 1.

3 shows a circuit diagram of a semiconductor device according to an embodiment of the present invention.

4 is an operation timing diagram for describing an operation of the semiconductor device illustrated in FIG. 3.

FIG. 5 is a timing diagram illustrating a simulation result of the semiconductor device illustrated in FIG. 3.

In accordance with another aspect of the present invention, a semiconductor device includes: a first bit line pair respectively precharged to a first power supply voltage during a precharge operation; A second bit line pair respectively precharged to a second power supply voltage during the precharge operation; And a bit line separation circuit electrically connecting the first bit line pair and the second bit line pair in response to a first control signal, wherein the bit line separation circuit corresponds to a corresponding angle among the second bit line pairs. First and second switching circuits cross-coupled to bit lines and switched in response to voltages of the respective cross-coupled bit lines; A third switching circuit connected between the bit lines in the first pair of bit lines and the first switching circuit and switched in response to the first control signal; And a fourth switching circuit connected between the complementary bit line of the first bit line pair and the second switching circuit, and switched in response to the first control signal, wherein the semiconductor device comprises the first bit line pair. A fifth switching circuit connected between the bit line of the bit line and the bit line of the second bit line pair and switched in response to a second control signal; And a sixth switching circuit connected between the complementary bit lines in the first bit line pair and the complementary bit lines in the second bit line pair, and switched in response to the second control signal. The voltage is lower than the second power supply voltage.

A semiconductor device according to the present invention includes a first bit line; A first complementary bit line; A second bit line; A second complementary bit line; A first switching circuit and a third switching circuit connected between the first bit line and the second bit line and connected in series; A second switching circuit and a fourth switching circuit connected between the first complementary bit line and the second complementary bit line and connected in series; A first precharge circuit connected between the first bit line and the first complementary bit line and configured to precharge the first bit line and the first complementary bit line to a first power supply voltage during a precharge operation; A second precharge circuit connected between the second bit line and the second complementary bit line and configured to precharge the second bit line and the second complementary bit line to a second power supply voltage during the precharge operation; And the first switching circuit is switched in response to the voltage of the second complementary bit line, and the second switching circuit is switched in response to the voltage of the second bit line, and the third switching circuit and the fourth The switching circuit is switched in response to a first control signal, wherein the first power supply voltage is lower than the second power supply voltage.

The semiconductor device further includes a sense amplifier connected to the second bit line and the second complementary bit line and for amplifying a voltage difference between the second bit line and the second complementary bit line.

The semiconductor device may further include: a fifth switching circuit connected between the first bit line and the second bit line and switched in response to a second control signal; And a sixth switching circuit connected between the first complementary bit line and the second complementary bit line and switched in response to the second control signal. The first control signal and the second control signal are activated with a predetermined time difference.

A semiconductor device according to the present invention includes a first bit line; A first complementary bit line; A second bit line; A second complementary bit line; A first transistor and a third transistor connected between the first bit line and the second bit line and connected in series; A second transistor and a fourth transistor connected between the first complementary bit line and the second complementary bit line and connected in series; A fifth transistor connected between the first bit line and the second bit line and receiving a second control signal through a gate; A sixth transistor connected between the first complementary bit line and the second complementary bit line and receiving the second control signal through a gate; A first precharge circuit connected between the first bit line and the first complementary bit line and configured to precharge the first bit line and the first complementary bit line to a first power supply voltage during a precharge operation; A second precharge circuit connected between the second bit line and the second complementary bit line and configured to precharge the second bit line and the second complementary bit line to a second power supply voltage during the precharge operation; And a gate of the first transistor is connected to the second complementary bit line, a gate of the second transistor is connected to the second bit line, and a first control signal is connected to the third transistor and the fourth transistor. The first power supply voltage is input to a gate and is lower than the second power supply voltage.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 shows a circuit diagram of a semiconductor device according to an embodiment of the present invention.

For convenience of description, the semiconductor device 300 illustrated in FIG. 3 may include the memory cell MCi, the first bit line pair BL and BLB, the second bit line pair SBL and SBLB, and the peripheral circuits 310 to 300. 350). The memory cell MCi typically represents a plurality of memory cells constituting the memory cell array and is connected to the first bit line BL.

The semiconductor device 300 may include a memory cell MCi, a first precharge circuit 310, a bit line isolation circuit 320, a second precharge circuit 330, a sense amplifier 340, and a column select circuit 350. And input / output line pairs IO and IOB.

The memory cell MCi includes one transistor GT and one cell capacitor C. FIG. When the word line WL is activated, the charge (or data) stored in the cell capacitor of the memory cell MCi is transferred to the first bit line BL through the transistor GT.

The first precharge circuit 310 is connected between the first bit line pairs BL and BLB, and the first bit line pair BL and BLB in response to the first precharge enable signal BLEQi during the precharge operation. Each is precharged to the first power supply voltage VBL.

For example, when the first precharge enable signal BLEQi is activated (for example, logic high), the first precharge circuit 310 transfers each of the cell bit line pairs BL and BLB to the first power voltage VBL. Precharge.

The second precharge circuit 330 is connected between the second bit line pairs SBL and SBLB, and the second bit line pairs SBL and SBLB in response to the second precharge enable signal PRE during the precharge operation. Each is precharged with a second power supply voltage VCCA.

For example, when the second precharge enable signal PRE is inactivated (eg, logic low), the second precharge circuit 330 sets the second bit line pairs SBL and SBLB to the second power supply voltage VCCA. Precharge with. At this time, the second power supply voltage VCCA is higher than the first power supply voltage VBL. For example, the first power supply voltage VBL is preferably half of the second power supply voltage VCCA (VBL = 0.5 VCCA).

The second precharge circuit 330 may be implemented with two PMOS transistors P1 and P2. The PMOS transistor P1 is connected between the second power supply voltage VCCA and the second bit line SBL, and the second precharge enable signal PRE is input to the gate of the PMOS transistor P1. The PMOS transistor P2 is connected between the second power supply voltage VCCA and the second complementary bit line SBLB, and the second precharge enable signal PRE is input to the gate of the PMOS transistor P2.

The bit line isolation circuit 320 is implemented with a plurality of NMOS transistors N1 to N6, but is not limited to NMOS transistors. Therefore, when each of the NMOS transistors N1 and N2 is replaced with a PMOS transistor, the gate and the drain of each PMOS transistor are connected to the first bit line BL and the first complementary bit line BLB, respectively.

The bit line isolation circuit 320 electrically connects the first bit line pair BL and BLB and the second bit line pair SBL and SBLB in response to the first control signal PSEi.

The bit line isolation circuit 320 is cross-coupled to the bit lines SBL and SBLB corresponding to each of the second bit line pairs SBL and SBLB, and the voltages of the bit-coupled bit lines SBL and SBLB are respectively. And a first switching circuit N1 and a second switching circuit N2 which are respectively switched in response.

The first switching circuit and the third switching circuits N1 and N3 are connected in series between the second bit line SBL and the first bit line BL. The control terminal of the first switching circuit N1, that is, the gate of the NMOS transistor N1 is connected to the second complementary bit line SBLB. Therefore, the first switching circuit N1 is controlled by the voltage of the second complementary bit line SBLB. The first control signal PSEi is input to the control terminal of the third switching circuit N3, that is, the gate of the NMOS transistor N3.

The second switching circuit and the fourth switching circuits N2 and N4 are connected in series between the second complementary bit line SBLB and the first complementary bit line BLB. The control terminal of the second switching circuit N2, that is, the gate of the NMOS transistor N2, is connected to the second bit line SBL. Therefore, the second switching circuit N2 is controlled by the voltage of the second bit line SBL.

The first control signal PSEi is input to the control terminal of the fourth switching circuit N4, that is, the gate of the NMOS transistor N4. Therefore, the third switching circuit N3 and the fourth switching circuit N4 are turned on / off in response to the first control signal PSEi.

The fifth switching circuit N5 is implemented with an NMOS transistor, the NMOS transistor N5 is connected between the first bit line BL and the second bit line SBL, and the second control signal RSTi is an NMOS transistor. It is input to the gate of N5. Therefore, the fifth switching circuit N5 is turned on / off in response to the second control signal RSTi.

The sixth switching circuit N6 is implemented with an NMOS transistor, the NMOS transistor N6 is connected between the first complementary bit line BLB and the second complementary bit line SBLB, and the second control signal RSTi is It is input to the NMOS transistor N6. Therefore, the sixth switching circuit N6 is turned on / off in response to the second control signal RSTi.

The sense amplifier 340 is connected between the second bit line SBL and the second complementary bit line SBLB, and senses and amplifies a voltage difference between the second bit line pairs SBL and SBLB. The sense amplifier 340 has cross-coupled NMOS transistors N7 and N8 and cross-coupled PMOS transistors P7 and P8.

That is, the MOS transistors N7 and N8 connected in series are connected between the second bit line SBL and the second complementary bit line SBLB, and the sense amplifier enable signal SAN is connected to the MOS transistors N7. , N8) is input to the common contact.

The MOS transistors P7 and P8 connected in series are connected between the second bit line SBL and the second complementary bit line SBLB, and the second power supply voltage VCCA is connected to the MOS transistors P7 and P7. Input to common contact of P8). Gates of the respective MOS transistors N8 and P8 are connected to the second bit line SBL, and gates of the respective MOS transistors N7 and P7 are connected to the second complementary bit line SBLB.

The column select circuit 350 is connected between the second bit line SBL and the second complementary bit line SBLB, and the second bit line SBL and the second complementary bit line in response to the column select signal CSL. The data of (SBLB) is transferred to the input / output line pairs IO and IOB, respectively.

4 is an operation timing diagram for describing an operation of the semiconductor device illustrated in FIG. 3. An operation of the semiconductor device 300 will now be described with reference to FIGS. 3 and 4.

For convenience of explanation, it is assumed that a memory corresponding to data 1 is stored in the memory cell MCi connected to the first bit line BL.

VSS represents a ground voltage, VCCA represents a second power supply voltage, VPP represents a voltage higher than the second power supply voltage VCCA, and VCC is the same voltage as the second power supply voltage VCCA.

When the first precharge enable signal BLEQi is activated, each of the first bit line pairs BL and BLB is precharged with the first power supply voltage VBL, and the second precharge enable signal PRE is inactivated. Each of the second bit line pairs SBL and SBLB is precharged with the second power supply voltage VCCA.

Each of the precharge enable signals BLEQi and PRE then transitions to inactive / activated before the word line WL is activated, so that each of the first bit line pair BL and BLB and the second is Each of the bit line pairs SBL and SBLB is in a floating state.

After that, when the word line WL is activated, the charge stored in the memory cell MCi moves to the first bit line BL, respectively, so that the voltage of the first bit line BL rises and the first complementary bit line is increased. The voltage of BLB is kept constant. That is, charge sharing occurs.

When the first control signal PSEi is activated, the first bit line pair BL and BLB and the second bit line pair SBL and SBLB correspond to the corresponding first switching circuit N1 and third switching circuit N3. And the second switching circuit N2 and the fourth switching circuit N4.

Therefore, the charge of the second bit line SBL is transmitted to the first bit line BL through the switching circuits N1 and N3 connected in series, and the charge of the second complementary bit line SBL is connected in series. Charge transfer pre-sensing is performed while being transferred to the second complementary bit line BLB through the circuits N2 and N4.

That is, the charges of the second bit line pairs SBL and SBLB, which are respectively precharged by the second power supply voltage VCCA, move to the first bit line pairs BL and BLB, respectively. The voltage of SBLB) is lowered.

In this case, since the voltage of the first complementary bit line BLB is lower than the voltage of the first bit line, the voltage of the second complementary bit line SBLB is lowered faster than the voltage of the second bit line SBL. The first switching circuit N1 is turned off in response to the voltage of the bit line SBLB. Therefore, the voltage of the second bit line SBL is floated or latched.

Subsequently, when the sense amplifier enable signal SAN transitions from the second power supply voltage VCCA to the ground voltage VSS, the NMOS transistor N8 turns on in response to the voltage of the second bit line SBL. Therefore, the voltage of the second complementary bit line SBLB is pulled down to the ground voltage VSS.

Since the PMOS transistor P7 is turned on in response to the voltage of the second complementary bit line SBLB, the voltage of the second bit line SBL is pulled up to the second power supply voltage VCCA.

When the second control signal RSTi is activated, the fifth switching circuit N5 and the sixth switching circuit N6 are turned on, respectively, so that the second bit line SBL and the first bit line BL are turned on. ) Maintains the second power supply voltage VCCA by the PMOS transistor P7, and the voltages of the second complementary bit line SBLB and the first complementary bit line BLB are grounded by the NMOS transistor N8. Maintain the voltage VSS.

FIG. 5 is a timing diagram illustrating a simulation result of the semiconductor device illustrated in FIG. 3.

3 and 5, when the word line WL is activated in response to a word line activation signal as shown in FIG. 5, each of the first bit line pairs BL and BLB is stored in a corresponding memory cell. Charge and charge sharing are performed, and the bit line separation circuit 320 performs CTPS in response to the first control signal PSEi and then senses and amplifies in response to the sense amplifier enable signal SAN. Each of the first bit line pairs BL and BLB is restored in response to the second control signal RSTi. The second control signal RSTi is preferably activated after the first control signal PSEi is activated.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the semiconductor device according to the present invention has an advantage of stably operating CTPS without requiring a separate voltage generator.

Claims (6)

In a semiconductor device, A first bit line pair respectively precharged to a first power supply voltage during a precharge operation; A second bit line pair respectively precharged to a second power supply voltage during the precharge operation; And A bit line separation circuit electrically connecting the first bit line pair and the second bit line pair in response to a first control signal, The bit line separation circuit, A first switching circuit and a second switching circuit which are cross-coupled to respective bit lines among the second bit line pairs, and are switched in response to voltages of the cross-coupled bit lines; A third switching circuit connected between the bit lines in the first pair of bit lines and the first switching circuit and switched in response to the first control signal; And A fourth switching circuit connected between the complementary bit line of the first bit line pair and the second switching circuit and switched in response to the first control signal, The semiconductor device, A fifth switching circuit connected between the bit lines of the first bit line pair and the bit lines of the second bit line pair and switched in response to a second control signal; And A sixth switching circuit connected between the complementary bit line of the first bit line pair and the complementary bit line of the second bit line pair, and switched in response to the second control signal, wherein the first power supply voltage Is lower than the second power supply voltage. In a semiconductor device, A first bit line; A first complementary bit line; A second bit line; A second complementary bit line; A first switching circuit and a third switching circuit connected between the first bit line and the second bit line and connected in series; A second switching circuit and a fourth switching circuit connected between the first complementary bit line and the second complementary bit line and connected in series; A first precharge circuit connected between the first bit line and the first complementary bit line and configured to precharge the first bit line and the first complementary bit line to a first power supply voltage during a precharge operation; A second precharge circuit connected between the second bit line and the second complementary bit line and configured to precharge the second bit line and the second complementary bit line to a second power supply voltage during the precharge operation; Equipped, The first switching circuit is switched in response to the voltage of the second complementary bit line, the second switching circuit is switched in response to the voltage of the second bit line, and the third switching circuit and the fourth switching circuit are And is switched in response to a first control signal, wherein the first power supply voltage is lower than the second power supply voltage. The semiconductor device of claim 2, wherein the semiconductor device is And a sense amplifier connected to the second bit line and the second complementary bit line and for amplifying a voltage difference between the second bit line and the second complementary bit line. The semiconductor device of claim 2, wherein the semiconductor device is A fifth switching circuit connected between the first bit line and the second bit line and switched in response to a second control signal; And And a sixth switching circuit connected between the first complementary bit line and the second complementary bit line and switched in response to the second control signal. The semiconductor device according to claim 4, wherein the first control signal and the second control signal are activated with a predetermined time difference. In a semiconductor device, A first bit line; A first complementary bit line; A second bit line; A second complementary bit line; A first transistor and a third transistor connected between the first bit line and the second bit line and connected in series; A second transistor and a fourth transistor connected between the first complementary bit line and the second complementary bit line and connected in series; A fifth transistor connected between the first bit line and the second bit line and receiving a second control signal through a gate; A sixth transistor connected between the first complementary bit line and the second complementary bit line and receiving the second control signal through a gate; A first precharge circuit connected between the first bit line and the first complementary bit line and configured to precharge the first bit line and the first complementary bit line to a first power supply voltage during a precharge operation; A second precharge circuit connected between the second bit line and the second complementary bit line and configured to precharge the second bit line and the second complementary bit line to a second power supply voltage during the precharge operation; Equipped, The gate of the first transistor is connected to the second complementary bit line, the gate of the second transistor is connected to the second bit line, and the first control signal is input to the gates of the third transistor and the fourth transistor. And the first power supply voltage is lower than the second power supply voltage.