KR20040072265A - Digital equalizer - Google Patents

Abstract

PURPOSE: A digital equalizer is provided to reduce an array area of a high-bit equalizer by using a half-size multiplier. CONSTITUTION: A digital equalizer includes a delay buffer, a first selector, a first storage unit, a second storage unit, an n/2 bit multiplier, an adder/subtracter, a sub-accumulator, and an accumulator. The delay buffer(101-104) is used for storing pulse code modulation data and equalized pulse code modulation data according to a buffer enable signal. The first selector is used for outputting selectively the pulse code modulation data or the output data of the delay buffer according to the first MUX selection signal. The first storage unit stores plural output data of different logic values corresponding to the output data of the first selector according to a register control signal. The second storage unit stores plural output data of different logic values corresponding to plural filter coefficients according to a register control signal. The n/2 bit multiplier(112) is used for multiplying the output data of the first selector by the output data of the second selector according to the second MUX selection signal. The adder/subtracter(115) is used for adding and subtracting the pulse code modulation data, the output data of the n/2 bit multiplier, the equalized pulse code modulation data, and the output data of the sub-accumulator. The sub-accumulator(117) is used for storing the output data of the adder/subtracter and outputting the arbitrary accumulated output data according to an accumulation control signal. The accumulator(116) is used for accumulating the output data of the adder/subtracter according to the accumulation control signal and outputting the equalized pulse code modulation data.

Description

Digital equalizer {Digital equalizer}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital equalizer, and more particularly, a technique for reducing the area of an equalizer by reducing the data size of a parallel multiplier in half when implementing a digital equalizer using a pipeline method.

Equalizers, which are used in digital audio devices to increase or decrease specific frequency band values of audio signals, were previously implemented using analog filters. However, due to the development of digital signal processing engineering, it is common to implement a digital filter using a digital signal processor (DSP) or a high speed micro control unit (MCU).

Parametric filter, a digital filter that is widely used for audio, is an Infinite Impulse Response (IIR) filter, and a filter capable of arbitrarily determining a frequency bandwidth according to a coefficient value and adjusting a size.

Here, the quadratic transfer function of the parametric filter is expressed by Equation 1 below.

[Equation 1]

Equation 1 described above is a second order transfer function of a parametric filter that is frequently used in an audio filter. It is easily represented digitally by the Z transfer function.

Here, x (z) is PCM (Pulse Coded Modulation) data of audio as input, and y (z) represents PCM data which has passed through a filter as an output, respectively. Also, a0, a1, a2, b0, and b1 are coefficients representing filter characteristics, and according to the values of the coefficients, the frequency band and bandwidth in which the filter operates and the degree of increase / decrease of PCM data can be adjusted.

In this case, when a value calculated in advance as a coefficient value of the filter is used, it may be stored in a storage means such as a memory and used when needed, or a new value may be calculated and used at all times. Here, an example of storing and using a precomputed value in the memory will be described.

On the other hand, Equation 2 to be described later is converted to the n-th output y (n) by converting the above-described equation (1) to the time domain (Time domain).

[Equation 2]

Here, the nth output y (n) is represented as the product of the coefficient, the current input and the past input, plus the product of the coefficient and the past output, respectively.

1 is a conceptual block diagram of Equation 2 described above.

x (n) is current PCM data, x (n-1) is PCM data before 1-sample, and x (n-2) indicates PCM data before 2-sample, respectively. y (n) is current equalized PCM data, y (n-1) is equalized PCM data before 1-sample, and y (n-2) is equalized PCM data before 2-sample Respectively.

The secondary parametric filter includes a delay unit 1 for delaying the current PCM data x (n) by one unit delay time, and a delay unit 1 output PCM data x (n-1) by one unit delay time. The delay part 2 is provided.

Amplifier 3 amplifies current PCM data x (n) by a0 times, amplifier 4 amplifies PCM data x (n-1) by a1 times, and amplifier 5 amplifies PCM data x (n-2) A) times a2. The delay unit 9 delays the PCM data y (n) by one unit delay time, and the delay unit 10 delays the output PCM data y (n-1) by one unit delay time.

The amplifier 11 amplifies the PCM data y (n-1) by b0 times, and the amplifier 12 amplifies the PCM data y (n-2) by b1 times. The adder 6 adds the output of the amplifier 3 and the output of the adder 7, the adder 7 adds the output of the amplifiers 4, 11 and the output of the adder 8, and the adder 8. Adds the outputs of amplifiers 5,8. Here, the amplifiers 3 to 5, 11 and 12 may be viewed as multipliers that multiply the PCM data x (n) by a factor multiple.

The parametric filter with this configuration performs 5 multiplications and 4 additions to complete the calculation of 1-sample. Thus, to run this operation in one cycle, five parallel multipliers and four adders are required.

However, parametric filters perform repetitive operations using one multiplier and one adder, respectively, to reduce hardware waste. At this point, it takes 4 to 5 times the cycle to calculate the 1-sample. Also, if one-sample is to be changed to another frequency band characteristic, the filter coefficients are changed to pass the same sample back through the equalizer.

On the other hand, the one-band equalizer refers to an equalizer in which each filter coefficient is defined as one. In addition, the multi-band equalizer can adjust the value of one-sample over several frequency bands because each filter coefficient can have various values.

Figure 2 is an embodiment of a conventional one-band equalizer implemented with hardwired logic.

The conventional one-band equalizer includes a one-band controller 20, a first x delay buffer 21, a second x delay buffer 22, a first y delay buffer 23, Second y delay buffer 24, pre-multiplexer 25, registers 26 and 27, n-bit multiplier 28, multiplexer 29 and 30, and add / A subtractor (Adder / Subtract) 31 and an accumulator (32).

Here, it is assumed that PCM data x (n) and filter coefficients are input from the memory device.

First, the one-band control unit 20 is composed of a state machine and generates various control signals for controlling the overall operation.

The first x delay buffer 21 is enabled by the buffer enable signal buf_load_en and temporarily stores the current PCM data x (n) input from the memory device (not shown) in synchronization with the clock signal clk. do. The second x delay buffer 22 is enabled by the buffer enable signal buf_load_en, and temporarily stores the PCM data x (n-1) output from the first x delay buffer 21 in synchronization with the clock signal clk.

Here, the first x delay buffer 21 and the second x delay buffer 22 temporarily store only one equalized PCM data sample, and after that, receive and store new PCM data.

The second y delay buffer 24 is enabled by the buffer enable signal buf_load_en and temporarily stores the past equalized PCM data y (n) in synchronization with the clock signal clk. The first y delay buffer 23 is enabled by the buffer enable signal buf_load_en, and temporarily stores the PCM data y (n-1) output from the second y delay buffer 24 in synchronization with the clock signal clk.

Here, the PCM data y (n) generated each time the calculation of the one-band equalizer is completed becomes the equalized PCM data of the past when the equalizer is operated on the PCM data of the next calculation. The first y delay buffer 23 and the second y delay butter 24 are configured in two stages and stored up to the second past value.

The premultiplexer 25 outputs the current PCM data x (n) and the PCM data x (n-1) output through the first x delay buffer 21 in response to the mux selection signal pre_mux_sel output from the 1-band control unit 20. ), The PCM data x (n-2) output through the second x delay buffer 22, the past equalized PCM data y (n-1) output through the second y delay buffer 24, and 1 y The equalized PCM data y (n-2) of the past outputted through the delay buffer 23 is selected and output in order. Therefore, the PCM data to be multiplied by the coefficient value of the filter is selected and output in order.

The register 26 stores data output from the pre-multiplexer 25 in accordance with the register control signal mpy_reg_load applied from the one-band control unit 20. The register 27 sequentially stores the coefficients of the filter applied from the memory device in accordance with the register control signal mpy_reg_load.

Parallel n-bit multiplier 28 multiplies the data output from registers 26 and 27.

The multiplexer 29, in response to the mux control signal muxA_sel output from the 1-band controller 20, removes the PCM data excessively included in the equalized PCM data when the equalizer calculation of 1-band is completed. (n) or the output data of the multiplier 28 is selectively output. The multiplexer 30 outputs "0" as an initial value upon equalization of PCM data or selectively outputs an output signal of the accumulator 32 in response to the mux control signal muxB_sel output from the 1-band controller 20.

The adder / subtracter 31 adds / subtracts the output data of the multiplexer 29 and the previous cumulative value output from the multiplexer 30 in response to the control signal sub_en applied from the 1-band controller 20. The accumulator 32 stores the output data of the adder / subtracter 31 and repeated filter coefficients in response to the accumulating control signal acc_load, so that the PCM data y (equalized from the accumulator 32 when the equalizer calculation of one band is completed is obtained. n) is output.

Here, the various control signals of the 1-band control unit 20 takes about 15 to 20 clocks when performing 5 multiplications and 4 additions when using a control method of CISC (Complex Instruction Set Computer).

In addition, the execution time of an equalizer of one band using a pipelined control method takes two pipeline sets, two multiplications and an addition at the same time, and thus takes seven to eight clocks in consideration of five multiplications.

Such a conventional equalizer is a hardware IP inside an audio decoding chip, and it is a general trend to operate in parallel with a decoding core. In this way, a digital equalizer can be implemented without increasing the speed of the overall decoding chip.

However, the equalizer needs to process the speed of the data more than 16 bits inside the decoder to improve the audio quality. Accordingly, the number of bits of the parallel multiplier used in the digital equalizer is increased, and accordingly, the area of the parallel multiplier, which occupies a substantial portion of the total equalizer, is increased.

For example, when data is increased from 16 bits to 32 bits, the number of bits is doubled, but the area is increased by 2 × 2 = 4 times. Therefore, as the number of data bits increases, the array area of the multiplier 28 increases in multiples of the number of bits.

The present invention has been made to solve the above problems, and its object is to reduce the area of the equalizer by reducing the data size of the parallel multiplier in half.

1 is a conceptual block diagram of a conventional parametric filter.

2 is a block diagram of a one-band equalizer implemented with a conventional parametric filter.

3 is a block diagram of a digital equalizer according to the present invention;

According to an aspect of the present invention, there is provided a digital equalizer, including: a delay buffer unit configured to temporarily store pulse code modulation data and equalized pulse code modulation data input according to a buffer enable signal; First selecting means for selectively outputting pulse code modulation data or output data of a delay buffer unit input according to the first mux selection signal; First storage means for sequentially storing a plurality of output data having different logic values corresponding to the output data of the first selection means according to the register control signal; Second storage means for sequentially storing a plurality of data having different logic values corresponding to the plurality of filter coefficients input according to the register control signal; N / 2 bit multiplication means for multiplying the output data of the first storage means and the output data of the second storage means selected in accordance with the second mux selection signal; Addition / subtraction means for adding / subtracting input pulse code modulation data, n / 2-bit multiplication means, equalized pulse code modulation data, and temporary accumulated output data selected according to the mux control signal; A temporary accumulator for temporarily storing output data of the addition / subtraction means according to the temporary accumulation control signal and outputting temporary accumulation output data; And an accumulator for accumulating the output data of the addition / subtraction means according to the accumulation control signal and outputting equalized pulse code modulation data.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a block diagram of a digital equalizer according to the present invention.

The present invention provides a 1-band controller 100, a third x delay buffer 101, a fourth x delay buffer 102, a third y delay buffer 103, and a fourth y delay buffer. (104), pre-multiplexer (105), registers (106-109), multiplexers (110, 111), n / 2-bit multipliers (112), multiplexers (113, 114), An adder / subtractor 115, an accumulator 116, and a temporary accumulator 117 are provided.

Here, it is assumed that PCM data x (n) and filter coefficients are input from the memory device.

First, the one-band control unit 100 is composed of a state machine or the like to generate various control signals for controlling the overall operation.

The third x delay buffer 101 is enabled by the buffer enable signal buf_load_en and temporarily stores the current PCM data x (n) input from the memory device (not shown) in synchronization with the clock signal clk. do. The fourth x delay buffer 102 is enabled by the buffer enable signal buf_load_en and temporarily stores the PCM data x (n-1) output from the third x delay buffer 101 in synchronization with the clock signal clk.

Here, the third x delay buffer 101 and the fourth x delay buffer 102 temporarily store only one equalized PCM data sample, and after that, receive and store new PCM data.

The fourth y delay buffer 104 is enabled by the buffer enable signal buf_load_en and temporarily stores the previously equalized PCM data y (n) in synchronization with the clock signal clk. The third y delay buffer 103 is enabled by the buffer enable signal buf_load_en and temporarily stores the PCM data y (n-1) output from the fourth y delay buffer 104 in synchronization with the clock signal clk.

Here, the PCM data y (n) generated every time the calculation of the one-band equalizer is finished becomes the equalized PCM data of the past when the equalizer is operated on the PCM data of the next calculation. The third y delay buffer 103 and the fourth y delay buffer 104 are configured in two stages and stored up to the second past value.

The pre-multiplexer 105 outputs the current PCM data x (n) and the third PC delay data x (n-1) output in response to the mux selection signal pre_mux_sel output from the 1-band controller 100. ), The PCM data x (n-2) output through the fourth x delay buffer 102, the past equalized PCM data y (n-1) output through the fourth y delay buffer 104, and The past equalized PCM data y (n-2) output through the 3y delay buffer 103 is selected and output in order. Therefore, the pre-multiplexer 105 selects and outputs PCM data to be multiplied by the coefficient value of the filter in order.

The registers 106 and 107 store data output from the pre-multiplexer 105 in accordance with the register control signal mpy_reg_load applied from the one-band controller 100. The registers 108 and 109 sequentially store the coefficients of the filter applied from the memory device in accordance with the register control signal mpy_reg_load.

The multiplexer 110 alternately selects and outputs the output data of the register 106 or the output data of the register 107 according to the mux selection signal mpre_mux_sel applied from the one-band controller 100. The multiplexer 111 alternately selects and outputs the output data of the register 108 or the output data of the register 109 in accordance with the mux selection signal mpre_mux_sel applied from the one-band control unit 100.

The parallel n / 2 bit multiplier 112 multiplies the data output from the multiplexers 110 and 111.

In response to the mux control signal muxA_sel output from the 1-band controller 100, the multiplexer 113 performs an operation for removing PCM data excessively included in the equalized PCM data when the equalizer calculation of 1-band is completed. . To this end, the multiplexer 113 selectively outputs the current PCM data x (n) or the output data of the multiplier 112.

In response to the mux control signal muxB_sel output from the 1-band controller 100, the multiplexer 114 outputs "0" as an initial value upon equalization of the PCM data, or outputs a signal applied from the accumulator 1162, The signal applied from the temporary accumulator 117 is selectively output.

The adder / subtracter 115 adds or subtracts the output data of the multiplexer 113 and the previous cumulative value output from the multiplexer 114 in response to the control signal sub_en applied from the 1-band controller 100.

The accumulator 116 stores the output data of the adder / subtracter 115 and repeated filter coefficients in response to the accumulating control signal acc_load, so that PCM data y (equalized from the accumulator 116 when the equalizer calculation of one band is completed is obtained. n) is output. The temporary accumulator 117 temporarily stores an intermediate calculation process of the partial product output from the adder / subtracter 115 in response to the temporary accumulator control signal acc_temp_load and outputs the result to the multiplexer 114.

As described above, the present invention uses a method of executing the n × n bit multiplier 112 consecutively four times in a manner of reducing the area of the existing 2n × 2n bit multiplier.

This concept of the present invention will be described through Equation 3.

[Equation 3]

Here, A _H and A _L represent upper and lower half of A, and B _H and B _L represent upper and lower half of B.

That is, when the multiplexer 110 selects the output signal of the register 106 according to the mux selection signal mpre_mux_sel, the multiplexer 111 selects the count value applied from the register 108. In addition, when the multiplexer 110 selects the output signal of the register 106, the multiplexer 111 selects the count value applied from the register 109.

When the multiplexer 110 selects the output signal of the register 107 according to the mux selection signal mpre_mux_sel, the multiplexer 111 selects the count value applied from the register 108. In addition, when the multiplexer 110 selects the output signal of the register 107, the multiplexer 111 selects the count value applied from the register 109.

Thereafter, the n / 2-bit multiplier 112 multiplies the output signals of the multiplexers 110 and 11 according to the number of four cases and outputs them to the multiplexer 113. The multiplexer 114 selects the PCM data y (n) which is the output signal of the accumulator 116 and the output signal of the temporary accumulator 117, and outputs the output signal to the adder / subtracter 115.

The adder / subtractor 115 calculates the multiplication value by the number of four cases of the n / 2 bit multiplier 110 and the value of the intermediate calculation process of the 2 / n bit multiplier 110 as shown in the above-described equation. Calculate and output

Accordingly, the present invention implements a multiplier of 2n × 2n bits using an n × n bit multiplier with four multiplications and three additions as shown in Equation 3. Therefore, the area can be reduced by about 1/4 of the conventional method.

As described above, the present invention provides an effect of reducing the array area of a high bit equalizer using a half size multiplier.

Claims (6)

A delay buffer unit configured to temporarily store pulse code modulation data and equalized pulse code modulation data inputted sequentially according to the buffer enable signal; First selecting means for selectively outputting the input pulse code modulation data or output data of the delay buffer unit according to a first mux selection signal; First storage means for sequentially storing a plurality of output data having different logic values corresponding to the output data of the first selection means according to the register control signal; Second storage means for sequentially storing a plurality of data having different logic values corresponding to the plurality of filter coefficients input according to the register control signal; N / 2 bit multiplication means for multiplying the output data of the first storage means and the output data of the second storage means selected in accordance with a second mux selection signal; Addition / subtraction means for adding / subtracting the input pulse code modulation data, the output data of the n / 2 bit multiplication means, the equalized pulse code modulation data and the temporary accumulated output data selected according to a mux control signal; A temporary accumulator for temporarily storing output data of the addition / subtraction means in accordance with a temporary accumulation control signal and outputting the temporary accumulation output data; And And an accumulator for accumulating the output data of the addition / subtraction means in accordance with an accumulation control signal and outputting the equalized pulse code modulation data. The method of claim 1, wherein the first storage means A first register for storing first output data applied from said first selection means in accordance with said register control signal; And And a second register for storing second output data applied from said first selection means in accordance with said register control signal. The method of claim 1 or 2, wherein the second storage means A third register for storing a first filter coefficient input according to the register control signal; And And a fourth register for storing a second filter coefficient input according to the register control signal. 2. The apparatus of claim 1, wherein the n / 2 bit multiplication means A first multiplexer for selectively outputting output data of the first storage means according to the second mux selection signal; A second multiplexer for selectively outputting output data of the second storage means in accordance with the second mux selection signal; And And an n / 2 bit multiplier for multiplying the output data of the first multiplexer and the output data of the second multiplexer. The method of claim 1, wherein the addition / subtraction means A third multiplexer for selectively outputting the input pulse code modulation data or output data of the n / 2 bit multiplication means according to a first mux control signal; A fourth multiplexer for selectively outputting an initial value of equalization, the equalized pulse code modulation data or the temporary accumulation output data according to a second mux control signal; And And an adder / subtracter for adding / subtracting output data of the third multiplexer and output data of the fourth multiplexer. The method of claim 1, A band control unit generating the buffer enable signal, the first mux selection signal, the register control signal, the second mux selection signal, the mux control signal, the temporary accumulation control signal, and the accumulation control signal in synchronization with a clock signal Digital equalizer characterized in that it further comprises.