KR20040070994A - Apparatus and method for generating a direction sequence in the dab receiver - Google Patents

Abstract

PURPOSE: A direction sequence generator of a digital audio broadcast receiver and a method therefor are provided to generate a direction sequence at a high speed and de-rotate a received signal. CONSTITUTION: A phase calculator(400) calculates a phase from a phase error vector of a received signal and outputs the calculation result as a directional sequence of n bits. A phase accumulator(300) calculates a deformed phase value mapped to some of bits of the directional sequence value as inputted with the remaining bit values to convert it to a new deformed phase value of n bits, accumulates it during a symbol interval of a transmission mode, and outputs it. A P/D(Phase to DS) converter(200) calculates the direction sequence value mapped to some of the bits among the deformed phase value inputted from the phase accumulator(300) with the remaining bit values to generate a direction sequence value of n bits. If there is change in some bits of the direction sequence value mapped to some of the bits of the generated direction sequence, the P/D converter adds a correction value corresponding to the change to the generated direction sequence and outputs it.

Description

Directional sequence generator and method in digital audio broadcasting receiver {APPARATUS AND METHOD FOR GENERATING A DIRECTION SEQUENCE IN THE DAB RECEIVER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Derotator of a digital audio broadcasting (DAB) receiver, and more particularly, to a Direction Sequence generator and a method for generating the Derotating apparatus based on CORDIC. .

DAB (Digital Audio Broadcasting) is the third generation of radio following AM and FM. It is a next-generation radio broadcast that provides CD-quality sound, various data services and excellent mobile reception in the multimedia age. It can be broadly classified into an out-of-band method and an in-band method proposed by the United States.

The European DAB, or EUREKA-147, uses a new frequency band other than the FM band for analog broadcasting. It features the use of new frequency bands and wideband transmission, and the frequency bands from 30 MHz to 3 GHz, namely VHF / UHF and L. Because it can be operated in the / S band, terrestrial broadcasting through the current FM band and TV band and satellite broadcasting through the L / S band are possible, thereby improving reception performance and high-speed data transmission in a mobile vehicle due to broadband transmission. It is known to be the best digital audio broadcasting system developed to date because efficient use of frequency through a single frequency network configuration.

As described above, the European DAB is a digital audio broadcast to replace the analog radio broadcast and is transmitted through a coded orthogonal frequency division multiplexing (COFDM) scheme. The COFDM transmission scheme is very resistant to multipath padding and is advantageous for reception of portable and mobile receivers. In order to obtain an accurate signal from a distorted received signal due to multipath fading or Doppler effect due to the movement of a vehicle, a DAB receiver has a synchronization channel composed of a null symbol and a phase reference symbol (PRS). channel) to perform time and frequency synchronization.

Frequency synchronization is performed by determining how much the received signal has been rotated by frequency distortion and derotating the received signal by the rotated phase. This may be referred to as derotating, and the derotating schemes introduced so far are largely classified into a ROM-based scheme and a cordic-based scheme.

The ROM-based derotating method first obtains a phase value of a received signal to be derotated, and multiplies a sample of each signal by reading a sin value and a cos value corresponding to the obtained phase value from a lookup table (see FIG. a)). However, this method requires a very large ROM and multiple multipliers, which makes the hardware design complicated.

In order to solve this drawback, the derotating method based on CORDIC (Coordinate Rotation Digital Computer) is introduced. Derotating method based on CORDIC is also used to obtain the phase of the received signal to be derotated, and the direction sequence (DS) corresponding to the obtained phase is coded with each sample of the signal (see (b) of FIG. 1). Can be implemented.

CORDIC is an algorithm that can perform operations such as trigonometric functions, so it uses only shift and addition / subtraction. Therefore, CORDIC has the advantage of being able to be implemented in small hardware. The codec may rotate the input signal as much as desired by repeatedly rotating the input signals I and Q according to the obtained direction sequence. However, one of the disadvantages of implementing CORDIC in a high speed derotator or direct digital frequency synthesizer (DDFS) is a delay in computation processing time. Because the rotation angle and the corresponding direction sequence are not linear, the direction sequence DS for rotating the received signal from the calculation result (corresponding to the phase accumulation value) between phases is determined. In order to calculate, it is necessary to calculate computational results between phases as many times as iterations of Codic (when the repetitive phase calculator is implemented by the Codic algorithm) or use complex hardware such as a multiplier. There is a limit to the implementation.

Accordingly, an object of the present invention is to generate a direction sequence at high speed in a DAB receiver as well as a direction sequence in a DAB receiver capable of generating a direction sequence DS with a simple configuration and performing derotation of a received signal. DirectionSequence) generator, a method thereof, and a derotator including the direction sequence generator.

1 is a schematic diagram of a typical rerotator of a DAB receiver.

FIG. 2 is a graph showing the relationship between the direction sequence DS and the phase of CORDIC having an iteration number N; FIG.

FIG. 3 is an enlarged graph showing a monotonically increasing section in the graph shown in FIG.

4 is a graph illustrating the relationship between a modified phase and a direction sequence DS for the implementation of the present invention.

5 is a block diagram of a direction sequence (DS) generator according to an embodiment of the present invention.

6 is a configuration diagram of the phase accumulator 300 of FIG. 5.

FIG. 7 is a view for explaining a process of converting and outputting a direction sequence DS input to a phase accumulator 300 into a modified phase value according to an exemplary embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration of a phase to DS (P / D) converter 200 of FIG. 5.

9 is a view for explaining a process of outputting a modified phase value (Phase) input to the P / D converter 200 in the final direction sequence (DS) according to an embodiment of the present invention.

Direction sequence (DS) generator according to an embodiment of the present invention for achieving the above object,

A phase calculator for calculating a phase from a phase error vector of the received signal and outputting the calculated result as an n-bit direction sequence ds;

A phase accumulator for converting a transformed phase value mapped to some bits of the input direction sequence (ds) value with the remaining bit values, converting the transformed phase value into a new n-bit transformed phase value, and accumulating and outputting the transformed phase value during the symbol period of the transmission mode. ;

The direction sequence ds, which is mapped to some bits among the modified phase values input from the phase accumulator, is calculated with the remaining bit values to generate an n-bit direction sequence DS, and the generated direction sequence DS P / D (Phase to DS) that adds and outputs a correction value corresponding to the change in the generated direction sequence DS when there is a bit change between some bits of the bit) and some bits of the mapped output direction sequence ds. A converter;

Furthermore, the phase accumulator;

a ROM for outputting a modified phase value corresponding to the upper m bits of the direction sequence DS expressed in n bits;

And an adder configured to add a value corresponding to the remaining bits of the direction sequence DS except for m bits with a modified phase value corresponding to the upper m bits of the direction sequence and output the final modified phase value. ,

The P / D converter;

a ROM for outputting a direction sequence value corresponding to the upper m bits among the final modified phase values represented by n bits;

A first adder for adding a value corresponding to the remaining bits except the m bits among the modified phase values with a direction sequence value output from the ROM;

A correction value generator which compares the upper m bits of the first adder with the upper m bits of a direction sequence value output from the ROM and outputs different correction values according to positions where the upper bits change;

And a second adder for adding the output of the first adder and the output of the correction value generator and outputting the output to the codec rotator.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Before describing the technical configuration of the present invention, the characteristic between the direction sequence DS and the phase of the cordic is analyzed, and the direction sequence DS necessary for derotating the received signal from the analysis result is obtained between phases. A direction sequence (DS) generator and its method which can be directly derived from the following description will be described.

First, FIG. 2 graphically illustrates the relationship between the direction and the phase of the codec of N having a number of iterations. Referring to FIG. 2A, it can be seen that the phase does not increase monotonically with the increase in the direction sequence DS of the Codic. Referring to Fig. 2 (b), which enlarges a part of the graph shown in Fig. 2 (a), when the direction sequence DS increases one step from binary " 001111 " to " 010000 " in Decreases. On the other hand in In the case of increasing by one step, it can be seen that the direction sequence DS is increased from "001111" to "010101". Thus, the phase in In the case of increasing by one step, the correct direction sequence DS can be obtained by correcting the direction sequence DS by Δ. It can be seen that the same phenomenon is shown in FIG. 2 (c) in which another part of the graph shown in FIG. 2 (a) is enlarged. Therefore, the parts that can be commonly inferred in the graphs of (b) and (c) of FIG. 2 are used to correct the direction sequence DS by looking at a change in a specific position (eg, the upper second bit) of the direction sequence DS. Can be. As described above, it is possible to determine whether to correct the direction sequence DS only by the change of the upper order bits of the direction sequence DS. Therefore, how many bits of the upper bits should be used to convert the operation between phases into the direction sequence DS. You can decide. The analysis result may be used to design a direction sequence (DS) generator which will be described later.

Meanwhile, FIG. 3 is an enlarged graph of a monotonically increasing section in the graph shown in FIG. Referring to FIG. 3, since the phase value represented by the direction sequence DS of the codec is the sum of the arc tangent values of the bits of the direction sequence DS, the phase value of the codec is not linear within the entire monotonically increasing interval. Therefore, the inter-phase calculation in this nonlinear part also needs correction. For this correction, the number of "higher bits used to convert the operation between phases into the direction sequence DS" described in FIG. 2 is readjusted. The upper bits of the predetermined direction sequence DS serve as a reference for dividing the phase and the direction sequence DS into pieces that are linearly piecewise. When the calculation is performed by dividing the direction sequence DS into linearly divided sections, correction values to be added as a change of a specific upper bit may be different. For example, in FIG. 2B, the phase in The direction sequence DS should be corrected by 6 when increasing by one, but in FIG. In other words, when the upper 2nd bit of the direction sequence DS is changed, a correction value of 6 or 7 should be used, which means that another operation or table is required to obtain a more accurate correction value. Not suitable for angle) operation.

Therefore, in order to simplify the above-described method, as shown in FIGS. 4B and 4C, the inclination between the phase and the direction sequence DS is changed so that the correction value due to the same bit change in the direction sequence DS is fixed. It is to make it. In this case, by using the symmetry of the direction sequence (DS), it is possible to reduce the size of the ROM required by half. Meanwhile, the phase in which the slope is changed can be defined as follows. In the following formula, K is obtained through an experiment as the maximum value of the changed phase, an example of such an experimental value is shown in Table 1 below.

Modified phase = phase (rad) * K / π

For reference, FIG. 4 is a graph showing a relationship between a phase and a direction sequence (DS) changed for the implementation of the present invention, and (b) and (c) in FIG. 4 illustrate some sections of the graph shown in (a). It is enlarged.

N 13 14 15 16 17 K 3222 6440 12872 25744 61474

Hereinafter, a direction sequence generator and a method for directly deriving a direction sequence DS necessary for derotating a received signal from the above-described analysis result will be described.

5 is a block diagram of a direction sequence (DS) generator according to an embodiment of the present invention, FIG. 6 is a configuration of the phase accumulator 300 of FIG. 5, and FIG. 7 is a phase accumulator 300. FIG. 4 is a diagram illustrating a process in which the direction sequence DS inputted as is converted into a modified phase value and output. In addition, FIG. 8 illustrates a configuration of a phase to DS (P / D) converter 200 in FIG. 5, and FIG. 9 illustrates a direction in which a modified phase value input to the P / D converter 200 is final. FIG. 4 is a view for explaining a process output to (DS).

First, referring to FIG. 5, the phase calculator 400 calculates and outputs a phase from a phase error vector (X, Y) detected from a received signal of a digital audio broadcast signal, and outputs the calculated result of the n-bit direction sequence DS. Output as a) value. The phase calculator 400 may calculate the phase based on a CORDIC algorithm.

The phase accumulator 300 calculates a modified phase value mapped to some of the upper bits of the n-bit direction sequence DS input from the phase calculator 400 with the remaining bit values to generate a new n-bit. After converting to the modified phase value of, it is accumulated and outputted during the symbol period according to the transmission modes (TM1, TM2, ..).

The phase accumulator 300 may be implemented as a ROM 310 and an adder 320 as shown in FIG. 6. The ROM 310 stores modified phase values corresponding to the upper m bits DS MSB among the direction sequence DS values represented by n bits. Therefore, the ROM 310 outputs a modified phase value corresponding to the upper m bits of the direction sequence DS expressed in n bits. On the other hand, the adder 320 adds the value DS LSB corresponding to the remaining bits except the m bits of the direction sequence DS with the transformed phase value corresponding to the upper m bits of the direction sequence DS to finally transform. Output as phase value (Phase).

The above-described operation of the phase accumulator 300 will be supplemented with reference to FIG. 7. First, it may be assumed that the direction sequence DS input to the phase accumulator 300 has a 6-bit binary value. In this case, phase values corresponding to the change of the upper two bits are mapped and stored in the ROM 310 of the phase accumulator 300, respectively. As shown in FIG. 7, the upper two bits of the direction sequence DS are each "01." When "," 10, "11" corresponding modified phase (modified phase) has a value of ar0, ar1, ar2.

When the direction sequence ds is input to the phase accumulator 300 which stores the phase value of the point where the upper bit of the direction sequence DS is changed, the upper 2 bits of the direction sequence ds ("01") The phase value ar0 is output from the ROM 310, and the remaining value except for the upper two bits of the direction sequence ds is added to ar0 output from the ROM 310, so that the input direction sequence DS is modified phase as a result. It is converted to a value. Formulating this conversion process The value can be represented.

Meanwhile, the P / D converter 200 positioned at the rear end of the phase accumulator 300 may include a direction sequence value mapped to some upper bits of the modified phase values input from the phase accumulator 300. ds) is calculated with the remaining bit values to generate an n-bit direction sequence DS, wherein a bit change is performed between some bits of the generated direction sequence DS and some bits of the mapped direction sequence value ds. If is present, the correction value corresponding to the change is added to the generated direction sequence DS and output. As illustrated in FIG. 8, the P / D converter 200 may include two adders 220 and 240, a ROM 210, and a correction value generator 230.

In FIG. 8, the ROM 210 stores a direction sequence ds corresponding to the upper m bits of the modified phase values represented by n bits. Therefore, the direction sequence DS value corresponding to the upper m bits (for example, upper 2 bits) (Phase MSB) is output from the n-bit transformed phase value input from the phase accumulator 300.

In addition, the first adder 220 of the P / D converter 200 may store a value (Phase LSB) corresponding to the remaining bits except for m bits among the n-bit modified phase values input from the phase accumulator 300. In addition to the direction sequence value output from 210 and output.

On the other hand, the correction value generator 230 compares the upper m bits of the first adder 220 with the upper m bits of the direction sequence value output from the ROM 210, and the correction value Δ is different depending on the position where the upper bits are changed. Will output To this end, the correction value generator 230 should include at least comparison means for checking the change of each of the upper bits of the two input paths, and storage means for storing correction values for outputting different values according to positions where the upper bits are changed. do. For example, if the number of upper bits input to the correction value generator 230 is 2, two correction values may be stored in the storage means, and the comparing means may include a means for comparing the bit change at the second position with the bit at the first position. do.

Finally, the second adder 240 generates the final direction sequence DS for outputting to the codec rotator 100 by adding the output of the first adder 220 and the output of the correction value generator 230. For reference, the codec rotator 100 rotates the received digital audio broadcast signal according to the direction sequence DS output from the P / D converter 200.

Hereinafter, the above-described operation of the P / D converter 200 will be described with reference to FIG. 9. First, the upper two bits of the modified phase value ("00", "01") are included in the ROM 210 of the P / D converter 200. , "10", "11") are stored. Referring to FIG. 9, when the upper two bit value of the modified phase value is "01", the direction sequence value corresponding thereto is dr1, and when the upper two bit value is "10", the value of the corresponding direction sequence is dr2 Able to know.

When the 6-bit modified phase value, which is the output of the phase accumulator 300, is input to the P / D converter 200 that stores the direction sequence value of the point where the higher bit of the modified phase changes. The direction sequence value corresponding to the upper two bits of the modified phase value (“01”) is output from the ROM 210, and the remaining value (Phase LSB) except the upper two bits of the modified phase value is the ROM 210. The value is added to the output from and applied to the second adder 240 and the correction value generator 230. At this time, if there is a bit change for each position between the upper two bits output from the first adder 220 and the upper two bits of the direction sequence value output from the ROM 210, the correction value generator 230 corrects the correction value corresponding to the position of the bit change. Is output to be added to the output of the first adder 220, which corresponds to the direction sequence DS to rotate the received signal. If there is no bit change for each position between the upper two bits, the output of the first adder 220 is immediately output in the direction sequence DS which should rotate the received signal.

For reference, when the modified phase values a0, a1, and a2 shown in FIG. 9 are converted into the direction sequence DS as described above, the equations are as follows.

As described above, according to the present invention, the direction sequence DS generated by calculating the phase error vector detected from the received signal of the digital audio broadcasting signal is inputted to the phase accumulator 300 to define a predetermined phase change value. Soft calculation is performed to output a new strain phase value, and the transformed strain phase value is input back to the P / D converter 200 to softly process a new direction sequence (DS) value. This can be generated at a high speed and applied to the codec rotator 100.

As described above, the present invention can speed up the generation of the direction sequence DS for derotating the received signal by analyzing the characteristics of the direction sequence and the phase of the Codic to mutually convert the direction sequence DS and the phase. Has the advantage that

Furthermore, in generating the direction sequence DS at high speed, the direction sequence generator can be implemented with a simple hardware configuration.

On the other hand, the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be defined only by the appended claims.

Claims (5)

In the direction sequence (DS) generator in the digital audio broadcasting receiver having a coded rotator (CORDIC ROTATOR) for rotating the received signal in accordance with the input direction sequence (DS) value, A phase calculator for calculating a phase from the phase error vector of the received signal and outputting the calculated result as an n-bit direction sequence (ds); A phase accumulator for converting a transformed phase value mapped to some bits of the input direction sequence (ds) value with the remaining bit values, converting the transformed phase value into a new n-bit transformed phase value, and accumulating and outputting the transformed phase value during the symbol period of the transmission mode. ; The direction sequence ds, which is mapped to some bits among the modified phase values input from the phase accumulator, is calculated with the remaining bit values to generate an n-bit direction sequence DS, and the generated direction sequence DS P / D (Phase to DS) that adds and outputs a correction value corresponding to the change in the generated direction sequence DS when there is a bit change between some bits of the subcarrier and some bits of the mapped direction sequence ds. A direction sequence (DS) generator, comprising: a transducer. The method of claim 1, wherein the phase accumulator; a ROM for outputting a modified phase value corresponding to the upper m bits of the direction sequence DS expressed in n bits; And an adder configured to add a value corresponding to the remaining bits of the direction sequence DS except for m bits with a modified phase value corresponding to the upper m bits of the direction sequence DS and output the final modified phase value. Direction sequence (DS) generator, characterized in that. The apparatus of claim 2, wherein the P / D converter; a ROM for outputting a direction sequence (ds) value mapped to the upper m bits among the final modified phase values represented by n bits; A first adder for adding a value corresponding to the remaining bits of the modified phase value except for m bits with a direction sequence (ds) value output from the ROM; A correction value generator for comparing the upper m bits of the first adder output with the upper m bits of the direction sequence (ds) output from the ROM and outputting different correction values according to positions where the upper bits change; And a second adder for adding the output of the first adder and the output of the correction value generator and outputting the output to the codic rotator. The method of claim 2 or 3, wherein each of the ROM Direction sequence (DS) generator characterized by having a size. A method of generating a direction sequence in a digital audio broadcasting receiver, Calculating a phase error vector detected from a received signal of the digital audio broadcasting signal to generate a direction sequence (DS) value; The modified phase value corresponding to the upper m bits of the direction sequence DS expressed as n bits is read out from the memory and added to the value corresponding to the remaining bits except for m bits of the direction sequence DS to add the modified phase value. Generating a second step; And a third step of finally converting the transformed phase value accumulated for a predetermined time into a direction sequence DS to derotate the received signal. a) reading a direction sequence value corresponding to an upper m bit among the modified phase values represented by n bits in a memory and adding the same to a value corresponding to the remaining bits except m bits of the modified phase values; b) comparing the upper m bits of the addition result with the upper m bits of the direction sequence value read from the memory to generate different correction values according to positions where the upper bits change; and c) generating a final direction sequence (DS) by adding the addition result and the generated correction value.