KR20040065031A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20040065031A KR20040065031A KR1020030002150A KR20030002150A KR20040065031A KR 20040065031 A KR20040065031 A KR 20040065031A KR 1020030002150 A KR1020030002150 A KR 1020030002150A KR 20030002150 A KR20030002150 A KR 20030002150A KR 20040065031 A KR20040065031 A KR 20040065031A
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- oxide film
- gate line
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract 3
- 238000005530 etching Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 239000012159 carrier gas Substances 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000002019 doping agent Substances 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- -1 nitride nitride Chemical class 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게는 버퍼산화막을 PE-산화막으로 형성하여 실리콘기판과 게이트라인 상부의 산화막 두께를 게이트라인 측면의 산화막두께 보다 두껍게 증착하는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, a method of manufacturing a semiconductor device in which a buffer oxide film is formed of a PE-oxide film to deposit an oxide film on a silicon substrate and an upper portion of a gate line thicker than an oxide film thickness on a side of a gate line. It is about.
일반적으로 반도체소자의 디자인 룰이 감소할수록 반도체소자가 차지하는 면적이 줄어들고 따라서 노광공정은 점점 한계에 도달하여 플러그콘택 형성시 SAC(Self Alignment Contact)식각공정을 사용하고 있다.In general, as the design rule of the semiconductor device decreases, the area occupied by the semiconductor device decreases, and thus, the exposure process gradually reaches its limit, and thus, a SAC (Self Alignment Contact) etching process is used when forming a plug contact.
이러한 SAC식각공정은 식각선택비가 큰 산화막과 질화막스페이서를 이용하는데, 질화막스페이서는 강한 인장스트레스의 특성을 가지므로 실리콘기판과 직접 접촉을 하게 되면 실리콘기판에 스트레스를 가하여 반도체소자의 리프레쉬특성을 악화시킨다.The SAC etching process uses an oxide film and a nitride film spacer having a high etching selectivity. Since the nitride film spacer has a strong tensile stress characteristic, the silicon substrate is stressed on the silicon substrate when it comes into direct contact with the silicon substrate, thereby degrading the refresh characteristics of the semiconductor device. .
따라서, 반도체소자의 리프레쉬특성을 개선하고자 반도체소자의 제조공정 중 이온주입공정에 의해 소오스/드레인영역인 N-영역을 형성한 후 실리콘기판과 질화막스페이서 사이에 CVD(Chemical Vapor Deposition)방식에 의해 버퍼산화막을 형성한다.Therefore, in order to improve the refresh characteristics of the semiconductor device, an N-region, which is a source / drain region, is formed by an ion implantation process in a semiconductor device manufacturing process, and then buffered by a CVD (Chemical Vapor Deposition) method between the silicon substrate and the nitride film spacer. An oxide film is formed.
그 다음, LPC(Landing Plug Contact)식각시 SAC(Self Alignment Contact)식각공정으로 이용하는 질화막스페이서를 형성한다.Next, a nitride film spacer used in a Self Alignment Contact (SAC) etching process is formed during LPC (Landing Plug Contact) etching.
이러한 CVD방식에 의한 버퍼산화막을 이용하여 실리콘기판과 질화막스페이서 사이의 스트레스를 완화하는 노력을 기울이고 있다.Efforts have been made to alleviate the stress between the silicon substrate and the nitride film spacer using the buffer oxide film by the CVD method.
도 1은 종래기술에 따른 반도체소자의 제조방법을 도시한 공정 단면도이고, 도 2는 도 1에 의해 제작된 게이트라인을 도시한 사진이다.1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the prior art, and FIG. 2 is a photograph showing a gate line manufactured by FIG. 1.
도 1 및 도 2에 도시된 바와 같이, 종래에는 버퍼산화막(30)이게이트라인(20)을 따라 즉, 실리콘기판(10)과 게이트라인(20) 상부, 그리고 게이트라인(20) 측면에서 동일한 두께로 증착되어 그 두께차이가 없음을 알 수 있다.As shown in FIGS. 1 and 2, the buffer oxide film 30 is conventionally formed along the gate line 20, that is, the silicon substrate 10, the gate line 20, and the gate line 20. It can be seen that there is no difference in thickness by being deposited in thickness.
이러한 동일한 두께의 버퍼산화막(30)으로 인해, 게이트라인과 게이트라인사이의 공간이 버퍼산화막(30)의 두께 만큼 좁아져 플러그콘택의 면적과 플러그의 체적이 줄어들어 소자의 신호지연이 발생한다.Due to the buffer oxide film 30 having the same thickness, the space between the gate line and the gate line is narrowed by the thickness of the buffer oxide film 30 so that the area of the plug contact and the volume of the plug are reduced, resulting in signal delay of the device.
그러나, 상기 버퍼산화막은 장시간의 높은 증착온도에 노출되어 메모리셀의 소오스/드레인영역에 해당하는 N-영역의 5가 또는 6가의 원소들이 채널영역으로 열확산을 일으켜 셀 펀치를 일으키거나 GIDL(Gate induced drain leakage)을 증가시켜 리프레쉬를 감소시키는 문제점이 있다.However, the buffer oxide film is exposed to a high deposition temperature for a long time, so that the pentavalent or hexavalent elements of the N-region corresponding to the source / drain regions of the memory cell thermally diffuse into the channel region, causing cell punching or GIDL (Gate induced). There is a problem of reducing refresh by increasing drain leakage.
또한, 상기 버퍼산화막을 사용하면 그 증착 두께 만큼 질화막스페이서의 두께가 증가하여 후속의 랜딩플러그 형성시 플러그콘택의 면적은 작아지고 플러그의 체적이 작아지기 때문에 콘택저항이 커져 소자의 고속동작이 어렵다는 문제점이 있다.In addition, when the buffer oxide film is used, the thickness of the nitride film spacer increases as much as the deposition thickness thereof, so that the area of the plug contact becomes smaller and the volume of the plug becomes smaller when forming a subsequent landing plug. There is this.
이를 해결코자 상기 버퍼산화막의 두께를 얇게 하면, SAC공정에 이용되는 질화막스페이서와 실리콘기판와의 스트레스가 커져 소자의 리프레쉬 특성을 감소시킨다는 문제점이 있다.To solve this problem, if the thickness of the buffer oxide film is made thin, the stress between the nitride film spacer and the silicon substrate used in the SAC process increases, thereby reducing the refresh characteristics of the device.
따라서, 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 저온공정에 의한 도판트의 확산이동을 억제하여 소자의 트랜지스터 특성조절이 용이하고, 플러그콘택의 면적을 크게 하는 동시에 플러그의 체적을 크게 하여 콘택저항을 감소시킴으로써 고속의 동작속도를 이룰 수 있는 반도체소자의 제조방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above-mentioned problems of the prior art, it is possible to control the diffusion characteristics of the dopant by a low temperature process to easily control the transistor characteristics of the device, to increase the area of the plug contact and at the same time It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of achieving a high operating speed by increasing the volume and reducing the contact resistance.
도 1은 종래기술에 따른 반도체소자의 제조방법을 도시한 공정 단면도.1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.
도 2는 도 1에 의해 제작된 게이트라인을 도시한 사진.FIG. 2 is a photograph showing a gate line manufactured by FIG. 1. FIG.
도 3은 본 발명에 따른 반도체소자의 제조방법을 도시한 공정 단면도.3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 4는 도 3에 의해 제작된 게이트라인을 도시한 사진.4 is a photograph showing a gate line manufactured by FIG. 3.
(도면의 주요부분에 대한 부호설명)(Code description of main parts of drawing)
100 : 실리콘기판 110 : 절연막100 silicon substrate 110 insulating film
120 : 도전층 130 : 하드마스크120: conductive layer 130: hard mask
160 : 게이트라인 165 : 소오스/드레인영역160: gate line 165: source / drain region
170 : PE산화막 180 : 질화막170: PE oxide film 180: nitride film
190 : 층간절연막190: interlayer insulating film
상기 목적을 달성하기 위한 본 발명은, 반도체기판상에 절연막, 도전층 및 하드마스크를 순차적으로 적층한 후 이를 선택적으로 식각하여 게이트라인을 형성하는 단계; 상기 게이트라인사이의 반도체기판내에 소오스/드레인영역을 형성하는 단계; 상기 결과물의 상부 표면에 플라즈마를 이용한 산화막을 형성하는 단계; 상기 결과물의 상부에 스페이서용 질화막을 형성하는 단계; 및 상기 게이트라인을 포함한 결과물의 상부에 층간절연막을 형성하는 단계를 포함하여 구성됨을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a gate line by sequentially stacking an insulating film, a conductive layer, and a hard mask on a semiconductor substrate, and then selectively etching the same; Forming a source / drain region in the semiconductor substrate between the gate lines; Forming an oxide film using plasma on an upper surface of the resultant product; Forming a nitride film for a spacer on top of the resultant product; And forming an interlayer insulating film on the resultant product including the gate line.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 반도체소자의 제조방법을 도시한 공정 단면도이며, 도 4는 도 3에 의해 제작된 게이트라인을 도시한 사진이다.3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the present invention, and FIG. 4 is a photograph showing a gate line manufactured by FIG. 3.
도 3을 참조하여 본 발명에 다른 반도체소자의 제조방법을 설명하면 다음과 같다.Referring to Figure 3 describes a method for manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(100)상에 절연막(110), 도전층(120) 및 하드마스크(130)를 순차적으로 적층한 후 이를 선택적으로 식각하여 게이트라인(160)을 형성한다.First, the insulating layer 110, the conductive layer 120, and the hard mask 130 are sequentially stacked on the semiconductor substrate 100, and then selectively etched to form the gate line 160.
그 다음, 상기 게이트라인 식각공정에 의한 손상을 회복하기 위해 상기 게이트라인(160)을 포함한 결과물의 상부에 열산화공정을 수행한다.Then, a thermal oxidation process is performed on the upper part of the resultant including the gate line 160 to recover damage caused by the gate line etching process.
이어서, 이온주입공정에 의해 소오스/드레인영역(165)을 형성한다.Subsequently, the source / drain regions 165 are formed by an ion implantation process.
그 다음, 상기 결과물의 상부 표면에 직진성이 있는 플라즈마를 이용한 PE(Plasm Enhanced) 산화막(170)을 증착한다.Next, a PE (Plasm Enhanced) oxide film 170 using a plasma having a straightness is deposited on the upper surface of the resultant product.
이때, 상기 실리콘기판(100) 상부, 게이트라인(160) 상부 및 게이트라인(160) 측면에서 상기 PE산화막(170)은 각각 다른 두께(T1, T2, T3)로 증착된다.In this case, the PE oxide layer 170 is deposited on the silicon substrate 100, the gate line 160, and the gate line 160 at different thicknesses T1, T2, and T3, respectively.
즉, 상기 PE산화막(170)을 증착하는 경우 도 4에 도시된 바와 같이, 상기 실리콘기판(100)과 게이트라인(160) 상부의 산화막의 두께(T1, T2)는 게이트라인(160) 측면 두께(T3)에 비해 3배 이상 두껍다.That is, when the PE oxide film 170 is deposited, as illustrated in FIG. 4, the thicknesses T1 and T2 of the oxide film on the silicon substrate 100 and the gate line 160 are the thickness of the gate line 160. It is 3 times thicker than T3.
따라서, 종래의 CVD방식에 의해 형성된 버퍼산화막과 동일한 두께로 PE산화막(170)을 실리콘기판(100) 및 게이트라인(160)의 상부에 증착하는 경우, 종래의 CVD방식에 비해 게이트라인(160) 측면의 산화막(T3)은 매우 얇게 증착할 수 있다.Therefore, when the PE oxide film 170 is deposited on the silicon substrate 100 and the gate line 160 to the same thickness as the buffer oxide film formed by the conventional CVD method, the gate line 160 is compared with the conventional CVD method. The oxide film T3 on the side can be deposited very thinly.
즉, 상기 PE산화막(170)은 토폴로지가 있는 게이트라인(160)에 스텝 커버리지(게이트라인 윗쪽에 증착되는 두께(T2)에 대비되는 측면 두께(T3))가 60%이하이며 증착온도가 낮은 PECVD방식으로 증착한다.That is, the PE oxide film 170 has a step coverage (lateral thickness (T3) compared to the thickness (T2) deposited on the gate line) of the gate line 160 having a topology of 60% or less and a low deposition temperature. Deposition in a manner.
상기 증착온도는 600℃이하의 온도이며, TEOS가스를 분해시켜 형성하는 PETEOS(Plasma Enhanced TetraEthyl OrthoSilicate)막이나, SiH4을 분해시켜 형성하는 PE산화막으로 증착할 수 있다. 여기서, 소스가스는 TEOS(또는 SiH4)와 O2를 사용하고, N2, Ar, He등의 불활성가스를 캐리어가스로 사용하고, 두께는 300Å이하로 증착한다.The deposition temperature is 600 ° C. or less, and may be deposited using a PETEOS (Plasma Enhanced TetraEthyl OrthoSilicate) film formed by decomposing TEOS gas or a PE oxide film formed by decomposing SiH 4 . Here, as the source gas, TEOS (or SiH 4 ) and O 2 are used, and an inert gas such as N 2 , Ar, He, etc. is used as the carrier gas, and the thickness is deposited to 300 kPa or less.
이로써, 후속의 랜딩플러그 형성시 플러그콘택의 면적은 커지고 플러그의 체적이 커지기 때문에 콘택저항이 작아져 소자의 동작속도를 빠르게 할 수 있다.As a result, the area of the plug contact increases and the volume of the plug increases when the subsequent landing plug is formed, thereby reducing the contact resistance and speeding up the operation speed of the device.
이어서, 상기 게이트라인(160)을 포함한 결과물의 상부에 SAC식각공정에서 배리어층으로 이용하는 스페이서용 질화막(180)을 증착한다.Subsequently, a nitride nitride layer 180 for spacers, which is used as a barrier layer in the SAC etching process, is deposited on the resultant including the gate line 160.
그 다음, 상기 스페이서용 질화막의 상부에 층간절연막(190)을 형성한다.Next, an interlayer insulating film 190 is formed on the spacer nitride film.
상술한 바와 같이, 본 발명은 저온공정에 의한 도판트의 확산이동을 억제하여 소자의 트랜지스터 특성을 조절하기가 용이하며, 이로써 디자인 룰이 감소하여도 소자특성을 확보하는데 유리하다는 효과가 있다.As described above, the present invention is easy to control the transistor characteristics of the device by suppressing the diffusion movement of the dopant by the low temperature process, thereby having the effect of securing the device characteristics even if the design rule is reduced.
또한, 랜딩 플러그 콘택의 면적을 크게 형성함과 동시에 플러그의 체적을 크게 형성하여 콘택저항을 감소시킴으로써 소자의 동작속도를 빠르게 할 수 있다는 효과가 있다.In addition, there is an effect that the operating speed of the device can be increased by forming a large area of the landing plug contact and a large plug volume to reduce the contact resistance.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (8)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100723761B1 (en) * | 2006-05-10 | 2007-05-30 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
| US8471319B2 (en) | 2010-11-24 | 2013-06-25 | Kabushiki Kaisha Toshiba | Semiconductor device having multilayered interelectrode insulating film |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100723761B1 (en) * | 2006-05-10 | 2007-05-30 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
| US8471319B2 (en) | 2010-11-24 | 2013-06-25 | Kabushiki Kaisha Toshiba | Semiconductor device having multilayered interelectrode insulating film |
| KR101294495B1 (en) * | 2010-11-24 | 2013-08-07 | 가부시끼가이샤 도시바 | Semiconductor device and manufacturing method thereof |
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