KR20040061541A - The Manufacturing of Thin Film Transistors Array on Glass - Google Patents

Abstract

PURPOSE: A fabrication method of a TFT substrate is provided to form a poly silicon-type TFT array substrate by conducting mask processes 6 times with an etch stopper, thereby increasing a throughput and simplifying a fabrication process. CONSTITUTION: A gate electrode(33) is formed in a predetermined area of a substrate(31) where n-type and p-type element areas are defined. A gate insulating film(34), a semiconductor layer(35), and an etch stopper layer(36) are sequentially formed on a front side including the gate electrode(33). The first ion injection masks(37b-37c) and the second ion injection masks are formed on the etch stopper layer(36) to selectively remove the etch stopper layer(36). An n-type impurities area(35a) and a p-type impurities area are formed. The semiconductor layer(35) is selectively removed. Source/drain electrodes are formed in connection with the impurities areas(35a). A pixel electrode is connected to the drain electrode.

Description

The manufacturing method of thin film transistor array substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing a thin film transistor array substrate in which a polysilicon thin film transistor array substrate is formed in a six mask process using an etch stopper.

Recently, the development of the active matrix type thin film transistor (TFT) liquid crystal display device among the various forms of the liquid crystal display device is remarkable.

In an active matrix thin film transistor liquid crystal display (TFT LCD), an electrode of an individual pixel forming a screen of a display device is controlled using a transistor. In this case, the transistor is formed on a substrate using a semiconductor thin film.

The thin film transistor liquid crystal display (TFT LCD) may be roughly divided into an amorphous silicon type and a polysilicon type according to the characteristics of the semiconductor thin film used.

In both cases, efforts are being made to reduce the number of exposure steps in the process in order to reduce the process cost and increase the yield. In the case of amorphous silicon, it is formed by using chemical vapor deposition (CVD) at low temperature. In this case, there is an advantage in the characteristics of the liquid crystal display device using the glass substrate.

However, in the case of amorphous silicon, the carrier mobility is low, and therefore, it is not suitable for forming a transistor element of a driving circuit requiring fast operating characteristics. This fact means that the IC for driving the liquid crystal display device must be manufactured separately and attached to the periphery of the liquid crystal panel, and the manufacturing cost of the liquid crystal display device is increased by adding a process for the driving module.

On the other hand, since polysilicon has a much higher carrier mobility than amorphous silicon, it can be used to manufacture an IC for a driving circuit. Therefore, when polysilicon is used as a semiconductor thin film for forming a thin film transistor of a liquid crystal display device, a thin film transistor element for a pixel electrode and a transistor element for a driving circuit can be formed together on a same glass substrate through a series of processes.

This may reduce the cost of the module process in manufacturing the liquid crystal display and at the same time reduce the power consumption of the liquid crystal display.

However, in the case of using polysilicon, in order to form a polysilicon thin film on a substrate, an amorphous silicon thin film is first formed through a low temperature CVD process, and an additional process for crystallization such as irradiating a laser beam is required, and a carrier The leakage current flows excessively at the moment when the gate voltage is turned off in the transistor formed by the high mobility, thereby preventing a sufficient electric field from being maintained in the pixel portion. Such a method of suppressing the occurrence of leakage current may include a lightly doped drain (LDD) region in which the impurity concentration is ion-implanted at the junction between the source and drain regions of the thin film transistor and the channel, or an offset that is not impurity ion implantation. It is common to use a method in which a region is provided to act as a barrier against leakage current.

Hereinafter, a thin film transistor manufacturing method of a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1A and 1G are cross-sectional views illustrating a conventional thin film transistor manufacturing method.

In the liquid crystal display, various types of thin film transistors may be formed, and thus, the pixel portion n-type thin film transistor (LDD n-type TFT) having a lightly doped drain (LDD) structure (hereinafter, referred to as a pixel portion-LDD n-type TFT) and an nD thin film driver having a LDD structure The case where these thin film transistors are formed on the same substrate by dividing into transistors (hereinafter referred to as driver-LDD n-type TFT) and driver-type p-type thin film transistors (hereinafter referred to as driver-p-type TFT) will be described.

In this case, the regions in which the thin film transistors of each type are formed are first defined and then processed.

As shown in FIG. 1A, after the buffer layer 12 is deposited on the substrate 11, amorphous silicon (a-Si: H) is deposited.

The amorphous silicon (a-Si: H) is then dehydrogenated and crystallized into polysilicon via a laser. Then, the polysilicon is patterned using a first mask (not shown) defining a semiconductor layer formation region to form a semiconductor layer 13 which is an active layer of each TFT.

As shown in FIG. 1B, the gate insulating layer 14 is entirely deposited on the semiconductor layer 13, and the metal layer is entirely deposited on the gate insulating layer 14, and the gate insulating layer 14 is deposited through a gate forming second mask (not shown). It is selectively removed to form the gate electrode 15 of each TFT on a predetermined region above the semiconductor layer 13.

Thus, the same process is performed for each TFT formation region of each type until the gate electrode 15 is formed.

As illustrated in FIG. 1C, the first photoresist film is deposited on the entire surface, exposed and developed to form third masks 16a and 16b for high concentration n-type (n +) ion implantation, and then high concentration n-type (n +) ions are implanted. As a result, a high concentration n-type impurity region 13a is formed in the semiconductor layer 13 of the n-type TFT and the LDD n-type TFT formation region.

That is, the A-type third mask 16a masking the entire p-type TFT formation region in the p-type TFT formation region, and the B-type third mask 16b having a wider width than the gate electrode 15 in the LDD n-type TFT formation region. Is formed. The B-type third mask 16b is formed on the gate insulating layer 14 with a width of a length masking the gate electrode 15 and the LDD region formed thereafter. In this case, in the n-type TFT formation region, the gate electrode 15 serves as a mask, and a high concentration n-type impurity region 13a is formed in the semiconductor layer 13 on both sides of the gate electrode 15.

Here, PH ₃ is mainly used as the n-type ion implantation material.

As shown in FIG. 1D, the A-type and B-type third masks 16a and 16b are removed, and a second photosensitive film is deposited, exposed and developed on the entire surface to form a fourth mask 17 for implanting high concentration p-type (p +) ions. ), And then a high concentration of p-type (p +) ions are implanted to form the p-type impurity region 13b in the semiconductor layer 13 of the p-type TFT formation region.

The fourth mask 17 masks the entire surface of the n-type TFT forming region and the LDD n-type TFT forming region, and in the p-type TFT forming region, a high concentration p-type ion implantation is performed using the gate electrode 15 as a mask. Proceed with the process.

B ₂ H ₆ is mainly used as the p-type ion implantation material.

Next, as shown in FIG. 1E, the fourth mask 17 is removed, and ion implantation of low concentration n-type (n−) is performed using the gate electrode 15 of each TFT formation region as a mask. At this time, the low concentration n-type impurity region 13c is formed in the semiconductor layer 13 on both sides of the gate electrode 15 of the LDD n-type TFT formation region. In the n-type TFT formation region or the p-type TFT formation region, the low concentration n-type ion implantation into the region where the high concentration impurity region is formed through the high concentration ion implantation process previously performed does not significantly affect the impurity concentration.

The low concentration ion implantation process and the high concentration ion implantation process can be reversed in order. In any case, the low concentration ion implantation process proceeds using the gate electrode as a mask, and the high concentration ion implantation process uses a mask covering a portion where the LDD region is formed.

1F, after the interlayer insulating film 18 is deposited on the entire surface, the interlayer insulating film 18 is contacted to contact the high concentration impurity regions 13a and 13b of the semiconductor layer 13 through a fifth mask (not shown). 18 and the gate insulating film 14 are selectively removed.

Subsequently, a metal layer is entirely deposited on the interlayer insulating layer including the contact region, and patterned through a sixth mask (not shown) to form a source / drain electrode 19.

As illustrated in FIG. 1G, the protective film 20 is entirely deposited on the entire surface of the substrate including the source / drain electrodes 19, and then selectively removed through a seventh mask (not shown) to remove the drain electrode 19. Partial exposure.

Subsequently, after the transparent electrode is deposited on the entire surface, the pixel electrode 21 is formed by selectively removing the transparent electrode through an eighth mask (not shown). In this case, the pixel electrode 21 is formed to be connected to the drain electrode 19.

However, the conventional method of manufacturing the thin film transistor array substrate has the following problems.

When forming a polysilicon thin film transistor array substrate, the semiconductor layer formation, the gate electrode formation, the high concentration p-type impurity region definition, the high concentration n-type impurity region definition, the interlayer insulating film contact, the source / drain electrode formation, the protective film A total of eight mask processes are required, one for contact and one for forming a pixel electrode. The yield decreases with each mask process and is damaged by an etching solution or the like.

An object of the present invention is to provide a method for manufacturing a thin film transistor array substrate in which a polysilicon thin film transistor array substrate is formed in a six-mask process using an etch stopper.

1A to 1G are cross-sectional views illustrating a method of manufacturing a conventional thin film transistor array substrate.

2A to 2F are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

3A to 3H are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

31 substrate 32 buffer layer

33 gate electrode 34 gate insulating film

35 semiconductor layer 35a high concentration n-type impurity region

35b: LDD region 35c: high concentration p-type impurity region

36: etch stopper layer 37a, 37b, 37c: 1st ion implantation mask

38a, 38b: second ion implantation mask

39a, 39b: source / drain electrodes

40: pixel electrode

A method of manufacturing a thin film transistor array substrate of the present invention for achieving the above object comprises the steps of forming a gate electrode in a predetermined region on a substrate in which n-type and p-type device regions are defined, the gate on the front surface including the gate electrode Forming an insulating film, a semiconductor layer, and an etch stopper layer in sequence, and forming first and second ion implantation masks on the etch stopper layer, respectively, selectively removing the etch stopper layer, and then hardening the etch stopper layer. Forming n-type and p-type impurity regions as a mask, selectively removing the semiconductor layer so as to remain only on the gate electrode and a gate insulating film adjacent thereto, and forming a source / drain electrode connected to the impurity region And forming a pixel electrode connected to the drain electrode. It is characterized.

The forming of the n-type and p-type impurity regions may include forming a first ion implantation mask on the etch stopper layer, selectively removing the etch stopper layer by using the first ion implantation mask, and forming a front surface of the etch stopper layer. implanting n-type high concentration impurity ions to form an n-type high concentration impurity region, reducing a line width of the first ion implantation mask, and implanting n-type low concentration impurity ions onto the entire surface using the first ion implantation mask Forming an LDD region, removing the first ion implantation mask, forming a second ion implantation mask on the semiconductor layer including the etch stopper layer, and using the second ion implantation mask. To selectively remove the etch stopper layer and implant p-type high concentration impurity ions into the entire surface to form a p-type high concentration impurity region. This step is preferred and yirueojim including the step of removing the second ion implantation mask, and etch stopper layer.

The first ion implantation mask may be formed to cover the entire surface of the p-type device region and the channel and the LDD region of the n-type device region.

The second ion implantation mask may be formed to cover the entire area of the n-type device region and the channel region of the p-type device region.

The semiconductor layer is preferably formed by depositing amorphous silicon on a substrate and then dehydrogenating it.

After selectively removing the semiconductor layer, it is preferable to proceed with crystallization.

Crystallization of the semiconductor layer preferably proceeds simultaneously with activation.

It is preferable to further form a buffer layer on the substrate.

In addition, forming a gate electrode in a predetermined region on the substrate defined in the n-type and p-type device region of the method for manufacturing a thin film transistor array substrate of the present invention for achieving the same object, the gate on the front surface including the gate electrode Forming an insulating film, forming a source / drain electrode on the gate insulating film so as to overlap both ends of the gate electrode, sequentially forming a semiconductor layer and an etch stopper layer on the entire surface of the substrate, and the etch stopper Forming first and second ion implantation masks on the layer to selectively remove the etch stopper layer, and then form n-type and p-type impurity regions using the etch stopper layer as a hard mask; Selectively removing the semiconductor layer so as to remain only on an electrode and a gate insulating film adjacent thereto; In the yirueojim and forming a pixel electrode connected to the drain electrode has a further feature.

The forming of the n-type and p-type impurity regions may include forming a first ion implantation mask on the etch stopper layer, selectively removing the etch stopper layer by using the first ion implantation mask, and Implanting n-type high concentration impurity ions onto the entire surface to form n-type high concentration impurity regions, reducing the line width of the first ion implantation mask, and n-type low concentration impurity ions on the front surface using the first ion implantation mask Forming an LDD region by implanting the oxide, removing the first ion implantation mask, forming a second ion implantation mask on the semiconductor layer including the etch stopper layer, and forming the second ion implantation mask. Selectively remove the etch stopper layer and implant p-type high concentration impurity ions into the And forming the second ion implantation mask and the etch stopper layer.

The first ion implantation mask may be formed to cover the entire surface of the p-type device region and the channel and the LDD region of the n-type device region.

The second ion implantation mask may be formed to cover the entire area of the n-type device region and the channel region of the p-type device region.

The semiconductor layer is preferably formed by depositing amorphous silicon on a substrate and then dehydrogenating it.

After selectively removing the semiconductor layer, it is preferable to proceed with crystallization.

Crystallization of the semiconductor layer preferably proceeds simultaneously with activation.

It is preferable to further form a buffer layer on the substrate.

Hereinafter, a manufacturing method of a thin film transistor array substrate of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

In the liquid crystal display, various types of thin film transistors may be formed, and thus, n-type thin film transistors having a lightly doped drain (LDD) structure (hereinafter, referred to as a pixel portion and a driver LDD n-type TFT) and p-type thin film transistors (hereinafter, referred to as a driver p) The case where these thin film transistors are formed on the same substrate by dividing into a type TFT) will be described with an example.

As shown in FIG. 2A, after the substrate 31 is cleaned, the buffer layer 32 is entirely deposited. The buffer layer 32 serves to prevent alkali ions such as sodium ions (Na +), potassium (K +), and the like contained in the substrate 31 from penetrating into the subsequently formed semiconductor layer.

Subsequently, the gate forming metal layer is deposited on the entire surface, and then selectively removed through the first mask (not shown) to form the gate electrode 33.

As shown in FIG. 2B, after the first mask is removed, the gate insulating layer 34, the semiconductor layer 35, and the etch stopper layer 36 are sequentially deposited on the entire buffer layer 32 including the gate electrode 33.

Here, the semiconductor layer 35 is formed by first depositing amorphous silicon (a-Si: H) and dehydrogenating it.

The etch stopper layer 36 is formed of an insulating film such as an oxide film.

Subsequently, the p-type TFT formation region is masked entirely on the etch stopper layer 36, second masks 37a and 37b defining a high concentration n-type impurity region are formed, and second masks 37a and 37b are formed. After the etch stopper layer 36 is selectively removed, high concentration n-type ions are implanted to form a high concentration n-type impurity region 35a of the semiconductor layer 35.

Here, PH ₃ is mainly used as the n-type ion implantation material.

2C, a second mask having a width smaller than that of the second mask 37a by selectively removing the second mask 37a by an ashing process to define an LDD region among the LDD n-type TFT forming regions. After forming 37c, the etch stopper layer 36 is selectively removed using a mask, followed by implantation of low concentration n-type ions to form the LDD region 35b of the semiconductor layer 35. Next, the remaining second masks 37b and 37c are removed.

As shown in FIG. 2D, after masking the entire n-type TFT formation region and forming third masks 38a and 38b defining high concentration p-type impurity regions, the etch stopper layer 36 is selectively used as a mask. And the high concentration p-type ions are subsequently implanted to form the high concentration p-type impurity region 35c of the semiconductor layer 35.

Here, B ₂ H ₆ is mainly used as the p-type ion implantation material.

Subsequently, after the third masks 38a and 38b are removed, the remaining etching stopper layer 36 is removed.

After the etching stopper layer 36 is removed, the exposed semiconductor layer 35 proceeds to crystallization and activation simultaneously to polysiliconize.

As shown in FIG. 2E, the semiconductor layer 35 is selectively removed using a fourth mask (not shown), thereby leaving only the semiconductor layer 35 in the thin film transistor formation region.

Subsequently, a source / drain electrode forming metal layer is deposited on the entire surface of the gate insulating layer 34 including the semiconductor layer 35.

Subsequently, the source / drain electrode forming metal layer may be selectively removed through a fifth mask (not shown) to connect the source / drain electrodes 39a to the impurity regions 35a, 35b, and 35c of the semiconductor layer 35. 39b).

As shown in FIG. 2F, a transparent electrode is formed on the entire surface of the gate insulating layer 34 including the source / drain electrodes 39a and 39b, and then patterned through a sixth mask (not shown) to form the pixel electrode 40. Form.

As described above, in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention, the LDD region is formed by using the patterned etch stopper layer, and the source / drain electrodes are directly formed on the semiconductor layer. By forming the pixel electrode immediately adjacent to the drain electrode, the mask process can be formed on a six-circuit thin film transistor array substrate.

3A to 3H are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

As shown in FIG. 3A, after the substrate 41 is cleaned, the buffer layer 42 is deposited on the entire surface. The buffer layer 42 serves to prevent penetration of alkali ions such as sodium ions (Na +), potassium (K +), and the like contained in the substrate 41 into the semiconductor layer 46 formed later.

Subsequently, the gate forming metal layer is deposited on the entire surface, and then selectively removed through the first mask (not shown) to form the gate electrode 43.

As shown in FIG. 3B, after the first mask is removed, the gate insulating layer 44 is deposited on the entire buffer layer 42 including the gate electrode 43.

Subsequently, a source / drain electrode forming metal layer is entirely deposited on the gate insulating layer 44, and then selectively removed through a second mask (not shown) to form source / drain electrodes 45a and 45b.

As illustrated in FIG. 3C, the semiconductor layer 46 and the etching stopper layer 47 are sequentially deposited on the entire surface of the substrate including the source / drain electrodes 45a and 45b.

Here, the semiconductor layer 46 is formed by first depositing amorphous silicon (a-Si: H) and then dehydrogenating it.

The etch stopper layer 47 is formed of an insulating film such as an oxide film.

As shown in FIG. 3D, after covering the entire p-type TFT formation region on the etch stopper layer 47 and forming the third masks 48a and 48b defining the high concentration n-type impurity regions, high concentration n-type ions are implanted. As a result, a high concentration n-type impurity region 46a of the semiconductor layer is formed.

Here, PH ₃ is mainly used as the n-type ion implantation material.

As shown in FIG. 3E, the third mask 48a is removed by a process such as ashing to define an LDD region among the LDD n-type TFT forming regions, and then a low concentration n-type ion is implanted to inject the LDD region of the semiconductor layer. It forms 46b. Next, the remaining third masks 48b and 48c are removed.

As shown in FIG. 3F, after forming the fourth masks 49a and 49b which cover the entire n-type TFT formation region and define the high concentration p-type impurity regions, the high concentration p-type impurities of the semiconductor layer are implanted by implanting high concentration p-type ions. The region 46c is formed.

Here, B ₂ H ₆ is mainly used as the p-type ion implantation material.

Subsequently, after the fourth masks 49a and 49b are removed, the remaining etching stopper layer 47 is removed.

The semiconductor layer 46 exposed by the removal of the etching stopper 47 is simultaneously polycrystallized by crystallization and activation.

As shown in FIG. 3G, the semiconductor layer 46 is selectively removed using a fifth mask (not shown), thereby leaving only the semiconductor layers 50a and 50b of the thin film transistor formation region.

As shown in FIG. 3H, a transparent electrode is formed on the entire surface of the gate insulating layer 44 including the semiconductor layers 50a and 50b and then patterned through a sixth mask (not shown) to form the pixel electrode 51. .

As described above, in the method of manufacturing the thin film transistor array substrate according to the second embodiment of the present invention, the LDD region is formed using a patterned etch stopper layer, and a semiconductor layer is directly formed on the source / drain electrodes. By forming the pixel electrode immediately adjacent to the drain electrode, the mask process can be formed on a six-circuit thin film transistor array substrate.

In addition, since the thin film transistor array substrate formed in accordance with the first and second embodiments can proceed with crystallization and activation at the same time after the semiconductor layer is doped, the process is simplified and the tact time is reduced. .

In addition, since the activation proceeds in the energy band of the crystallization region, the overall activation efficiency is improved, and the device characteristics can be improved by increasing the activation efficiency at the junction region.

The method of manufacturing the thin film transistor array substrate of the present invention as described above has the following effects.

First, the present invention is a thin film in six mask processes for forming a gate electrode, forming a p-type impurity region, forming an n-type impurity region, defining a semiconductor layer of a thin film transistor, forming a source / drain electrode, and forming a pixel electrode. Fabrication of the transistor array substrate is complete.

Therefore, as compared with eight mask processes required in a conventional thin film transistor array substrate manufacturing process, yield reduction can be expected by reducing two mask processes, and the process can be simplified.

Secondly, since the crystallization process and the activation process are simultaneously performed after the semiconductor layer is doped, no additional activation process is required after or before crystallization, and the doping damage is compensated by activation at the same time as crystallization, thereby improving device characteristics. You can expect an improvement.

Claims (16)

forming a gate electrode in a predetermined region on the substrate where n-type and p-type device regions are defined; Sequentially forming a gate insulating film, a semiconductor layer, and an etch stopper layer on the entire surface including the gate electrode; Forming first and second ion implantation masks on the etch stopper layer, respectively, selectively removing the etch stopper layer, and then forming n-type and p-type impurity regions using the etch stopper layer as a hard mask; Selectively removing the semiconductor layer so as to remain only on the gate electrode and a gate insulating film adjacent thereto; Forming a source / drain electrode connected to the impurity region; And forming a pixel electrode connected to the drain electrode. The method of claim 1, Forming the n-type and p-type impurity regions Forming a first ion implantation mask on the etch stopper layer; Selectively removing the etch stopper layer using the first ion implantation mask and implanting n-type high concentration impurity ions into the entire surface to form an n-type high concentration impurity region; Reducing the line width of the first ion implantation mask; Forming an LDD region by implanting n-type low concentration impurity ions onto the entire surface using the first ion implantation mask; Removing the first ion implantation mask; Forming a second ion implantation mask on the semiconductor layer including the etch stopper layer; Selectively removing the etch stopper layer using the second ion implantation mask and implanting p-type high concentration impurity ions into a front surface to form a p-type high concentration impurity region; And And removing the second ion implantation mask and the etch stopper layer. The method of claim 2, The first ion implantation mask is formed to cover the entire surface of the p-type device region, the channel and the LDD region of the n-type device region, the method of forming a thin film transistor array substrate. The method of claim 2, And the second ion implantation mask is formed to cover the entire n-type device region and the channel region of the p-type device region. The method of claim 1, The semiconductor layer is a method of manufacturing a thin film transistor array substrate, characterized in that formed by depositing amorphous silicon on the substrate, and then dehydrogenated it. The method of claim 1, And selectively crystallizing the semiconductor layer and then crystallizing the thin film transistor array substrate. The method of claim 6, And crystallization of the semiconductor layer proceeds simultaneously with activation. The method of claim 1, A method of manufacturing a thin film transistor array substrate, further comprising forming a buffer layer on the substrate. forming a gate electrode in a predetermined region on the substrate where n-type and p-type device regions are defined; Forming a gate insulating film on the entire surface including the gate electrode; Forming a source / drain electrode on the gate insulating layer so as to overlap both ends of the gate electrode; Sequentially forming a semiconductor layer and an etch stopper layer on the entire surface of the substrate; Forming first and second ion implantation masks on the etch stopper layer, respectively, selectively removing the etch stopper layer, and then forming n-type and p-type impurity regions using the etch stopper layer as a hard mask; Selectively removing the semiconductor layer so as to remain only on the gate electrode and a gate insulating film adjacent thereto; And forming a pixel electrode connected to the drain electrode. The method of claim 9, Forming the n-type and p-type impurity regions Forming a first ion implantation mask on the etch stopper layer; Selectively removing the etch stopper layer using the first ion implantation mask and implanting n-type high concentration impurity ions into the entire surface to form an n-type high concentration impurity region; Reducing the line width of the first ion implantation mask; Forming an LDD region by implanting n-type low concentration impurity ions onto the entire surface using the first ion implantation mask; Removing the first ion implantation mask; Forming a second ion implantation mask on the semiconductor layer including the etch stopper layer; Selectively removing the etch stopper layer using the second ion implantation mask and implanting p-type high concentration impurity ions into a front surface to form a p-type high concentration impurity region; And And removing the second ion implantation mask and the etch stopper layer. The method of claim 10, The first ion implantation mask is formed to cover the entire surface of the p-type device region, the channel and the LDD region of the n-type device region, the method of forming a thin film transistor array substrate. The method of claim 10, And the second ion implantation mask is formed to cover the entire n-type device region and the channel region of the p-type device region. The method of claim 9, The semiconductor layer is a method of manufacturing a thin film transistor array substrate, characterized in that formed by depositing amorphous silicon on the substrate, and then dehydrogenated it. The method of claim 9, And selectively crystallizing the semiconductor layer and then crystallizing the thin film transistor array substrate. The method of claim 14, And crystallization of the semiconductor layer proceeds simultaneously with activation. The method of claim 9, A method of manufacturing a thin film transistor array substrate, further comprising forming a buffer layer on the substrate.