KR20040061505A - liquid crystal display device including common voltage generating device - Google Patents

Abstract

PURPOSE: An LCD having a common voltage generator is provided to prevent flickering and an afterimage by setting up automatically a common voltage without using a variable resistor. CONSTITUTION: A pixel region is defined by a gate line and a data line arranged on an active region. A plurality of dummy pixel regions(33a,33b,33c) are formed on a dummy region of a left side and a right side of the active region. A first and a second dummy data line are arranged to one direction on the dummy region of the left side and the right side of the active region. A plurality of feedback data pads(32a,32b,32c) are formed on a pad region in order to output pixel feedback voltages. A common voltage generator(60) is used for receiving the pixel feedback voltages and generating common voltages. A source driver IC(40) includes a plurality of first pads for applying voltages to a first and a second dummy data line, a plurality of second pads connected to the feedback data pads, and a plurality of third pads for applying common voltages to the common electrodes. A gate driver IC(50) includes a plurality of fourth pads connected to feedback data pads and a plurality of fifth pads for applying the common voltages to the common electrodes.

Description

Liquid crystal display device including common voltage generating device

The present invention relates to a display device, and more particularly, to a liquid crystal display device having a common voltage generator capable of automatically adjusting the common voltage.

One of the display devices, Cathode Ray Tube (CRT) has been used mainly for monitors such as TVs, measuring devices, information terminal devices, etc., but the size and weight of CRT itself make it necessary for the miniaturization and weight reduction of electronic products. Couldn't respond positively.

In order to replace the CRT, Liquid Crystal Dispaly (LCD), which has the advantages of light and thin, has been actively developed, and recently, the liquid crystal display (LCD) has been developed enough to perform a role as a flat panel display device. Demand is on the rise.

In general, a low cost and high performance thin film transistor liquid crystal display (TFT-LCD) uses an amorphous silicon thin film transistor as a switching device. Currently, the liquid crystal display device is a VGA (Video Graphic Array; maximum resolution is 640 x 480 pixels). It aims at high resolution with SVGA (800 × 600) and XVGA (1024 × 768).

The development of the TFT-LCD industry and its application has been accelerated by the increase in size and the increase in resolution, and much effort has been made in terms of simplification of the manufacturing process and improvement of yield for the purpose of increasing productivity and low cost.

Such a TFT-LCD is a display device that obtains a desired image by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field. .

A plurality of gate lines parallel to each other and a plurality of data lines insulated from and intersecting the gate lines are formed on the substrate of such a TFT-LCD, and an area surrounded by these gate lines and the data lines defines one pixel. A TFT is formed at a portion where the gate line and the data line of each pixel cross each other.

1 shows an equivalent circuit for a unit pixel in a typical TFT-LCD.

As shown in FIG. 1, the gate electrode g, the source electrode s, and the drain electrode d of the TFT 10 are connected to the gate line Gn, the data line Dm, and the pixel electrode P, respectively. Connected.

A liquid crystal material is formed between the pixel electrode P and the common electrode Vcom, and parasitic capacitance Cgd is generated between the gate electrode g and the drain electrode d due to misalignment. The liquid crystal capacitor Clc and the storage capacitor Cst act as loads that the TFT-LCD should drive.

The operation of the TFT-LCD will be described as follows.

First, the TFT 10 is turned on by applying a gate on voltage to a gate electrode connected to the gate line Gn to be displayed, and then a data voltage representing an image signal is applied to the source electrode s. The voltage is applied to the drain electrode d.

Accordingly, the data voltage is applied to the liquid crystal capacitor Clc and the storage capacitor Cst through the pixel electrode P, respectively, and an electric field is formed by the potential difference between the pixel electrode and the common electrode Vcom.

At this time, since the liquid crystal deteriorates when an electric field in the same direction is continuously applied to the liquid crystal material, the LCD panel drives the image signal to repeat the positive and negative polarities with respect to the common electrode to prevent deterioration of the liquid crystal. do.

On the other hand, the effective value of the voltage applied to the liquid crystal is determined by the degree of the voltage applied to the pixel electrode and the voltage applied to the common electrode. When driving the liquid crystal display device by the inversion driving method, the pixel voltage centered on the common voltage is It is necessary to adjust the level of the common voltage so as to be symmetrical. For this purpose, a constant common voltage to which the pixel voltage is symmetrical must be applied to the common electrode.

When the voltage of the pixel electrode centered on the common voltage is not symmetrical, the amount of pixel voltage charged in each pixel is different from frame to frame and flickers when the pixel voltage is reversed. ) Phenomenon occurs.

Hereinafter, a common voltage generator for applying a common voltage to the common electrode will be described.

2A to 2C are circuit diagrams of a common voltage generator of a liquid crystal display device according to the prior art.

First, the conventional common voltage generator shown in FIG. 2A includes first, second, and third resistors R11, VR1, and R21 connected in series between a power supply voltage terminal VDD serving as a reference voltage and a ground voltage terminal. And amplifying means for receiving and amplifying the voltage terminal VDD as an enable signal.

Here, the first and third resistors R11 and R21 are fixed resistors, the second resistor VR2 is a variable resistor, and the amplifying means uses an operational amplifier.

Therefore, the voltage divided by the resistors is output to the common voltage through the amplifying means.

In addition, the conventional common voltage generator illustrated in FIG. 2B may include the fourth, fifth, and sixth resistors R12, VR2, and R22 connected in series between the power supply voltage terminal VDD and the ground voltage terminal. The first and second switching means BP1 and BP2 are disposed between the driving voltage terminal and the ground voltage terminal to be switched to generate a common voltage.

The fourth and sixth resistors R12 and R22 are fixed resistors, the fifth resistor VR2 is a variable resistor, and the first and second switching means use bipolar transistors.

Therefore, the voltage divided by the resistors is output to the common voltage through the first and second switching means.

Next, in the conventional common voltage generator illustrated in FIG. 2C, seventh, eighth, and ninth resistors R13, VR3, and R23 are connected in series between a power supply voltage terminal VDD and a ground voltage terminal. The output terminal Vcom is connected between the resistor R13 and the eighth resistor VR3.

Therefore, the voltage divided by the resistors is output to the common voltage. At this time, the common voltage is adjusted according to the change in the resistance value of the eighth resistor VR3.

Here, the seventh and ninth resistors R13 and R23 are fixed resistors, and the eighth resistor VR3 is a variable resistor.

That is, when the resistance value of the eighth resistor VR3, which is the variable resistor, is the smallest, the least common voltage Vcom is output, and when the variable resistor is increased, the common voltage is relatively increased.

The common voltage generator of the conventional liquid crystal display device manually adjusts the variable resistors VR1, VR2, and VR3 to adjust the common voltage applied to the common electrode.

That is, when the common voltage is not constant, as described above, the flicker phenomenon of flickering of the screen occurs when the pixel voltage is reversed, so the operator must directly adjust the variable resistance value by looking at the displayed image.

Although the circuit configuration of the common voltage generator is simple as described above, manual adjustment of human beings is inevitable in delivering accurate common voltage to the panel.

Such a method of manually adjusting the variable resistor is not very reasonable to apply the optimum common voltage (Vcom) on the panel.

If the common voltage is not constant, the voltage is not maintained as the center value of the pixel voltage, and thus the value of the voltage charged to the pixel electrode in the frame unit is changed to cause the flicker phenomenon. This phenomenon becomes a bigger problem as the screen of the liquid crystal display becomes larger.

As described above, the common voltage generator of the conventional liquid crystal display device has the following problems.

First, since the operator manually adjusts the variable resistance to adjust the common voltage, the control reliability of the common voltage is lowered due to the degree of control mastery and sensitivity of the operator, and there is a limit to fine adjustment.

That is, since the degree of flicker causes a lot of changes in the minute change of the common voltage, even if the variable resistor is adjusted, fine adjustment is impossible, and thus the flicker cannot be completely removed.

Second, the adjustment of the variable resistor is difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device having a common voltage generator which can automatically use a common voltage without using a variable resistor. It is.

1 is an equivalent circuit diagram of a unit pixel of a general liquid crystal display device.

2a to 2c is a circuit diagram of a common voltage generator according to the prior art

3 is a block diagram illustrating a liquid crystal display device having a common voltage generator according to an exemplary embodiment of the present invention.

4 is a configuration diagram of a source driver according to an exemplary embodiment of the present invention.

5 is a configuration diagram of a gate driver according to an exemplary embodiment of the present invention.

6 illustrates driving examples of first and second dummy data lines according to an exemplary embodiment of the present invention.

7 is a circuit diagram of a common voltage generator according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

30: active area 31: dummy area

32a, 32b, 32c: first, second, third feedback data pad

33a, 33b, 33c: first, second and third dummy pixel areas

34: pad area 40: source driver IC

41: first chip 50: gate driver IC

51: second chip 60: common voltage generator

70: amplification means 71: switch control unit

The liquid crystal display device having the common voltage generator of the present invention for achieving the above object is for applying a common voltage to the common electrode of the liquid crystal panel having a lower substrate in which an active region, a dummy region and a pad region are defined. A liquid crystal display device comprising: a pixel region defined by a gate line and a data line intersected in the active region; A dummy pixel area formed in a plurality of dummy areas on the left and right sides of the active area; First and second dummy data lines arranged in one direction in the dummy areas on the left and right sides of the active area to drive the dummy pixel area; A plurality of feedback data pads for outputting respective pixel feedback voltages to be output through the dummy pixel areas to the pad area; A common voltage generator receiving the pixel feedback voltages to generate a common voltage; First pads applying voltages to the first and second dummy data lines, second pads connected to the feedback data pads, and third pads applying the common voltage to the common electrode of the liquid crystal panel. A source driver IC composed of pads; And a gate driver IC including fourth pads connected to the feedback data pads and fifth pads for applying the common voltage to the common electrode.

The dummy pixel regions may include a first dummy pixel region disposed before (left) the last pixel region of the line where the first pixel region of the active region is disposed, and the first pixel of the line where the last pixel region of the active region is disposed. And a second dummy pixel region disposed after the region (right side) and a third dummy pixel region disposed before the first pixel region (left side) of the line in which the first effective pixel region of the active region is disposed. do.

In the common voltage generator, one input terminal is connected to a ground line having a first resistance value, the pixel feedback voltages are selectively connected to a type force terminal, and a power line having a second resistance value is connected to one input terminal and an output terminal. Amplification means; And a switch control unit for controlling the pixel feedback voltages to be selectively connected to the type force terminal of the amplifying means.

The second resistance value is '0?'.

A thin film formed on a plurality of gate lines, a plurality of data lines D1 to Dn that are insulated from and intersect the gate lines, and a portion where the gate lines and the data lines cross each other in the pixel area of the active region. And a storage capacitor formed between the transistor TFT, the front gate line and the drain electrode of the thin film transistor, and a capacitor for accumulating the liquid crystal capacitor Clc between the drain electrode and the common electrode of the thin film transistor.

Hereinafter, a liquid crystal display device having a common voltage generator according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of a liquid crystal display device having a common voltage generator according to an exemplary embodiment of the present invention.

4 is a configuration diagram of a source driver according to an embodiment of the present invention, and FIG. 5 is a configuration diagram of a gate driver according to an embodiment of the present invention.

6 is a driving example of the first and second dummy data lines according to an exemplary embodiment of the present invention.

7 is a circuit diagram illustrating a common voltage generator according to an embodiment of the present invention.

First, the liquid crystal display of the present invention applies an electric field to a liquid crystal material having an anisotropic dielectric constant injected between opposite upper and lower substrates, and adjusts the intensity of the electric field to adjust the amount of light transmitted through the substrate. As a display device for obtaining an image, as shown in FIG. 3, the display device includes an upper and lower substrate, a source driver IC 40, a gate driver IC 50, and a common voltage generator 60. As shown in FIG.

The lower substrate is defined as an active region 30, a dummy region 31, and a pad region 34. The active region 30 is an area in which an actual liquid crystal is driven and displayed on a screen.

As shown in FIG. 3, a plurality of gate lines parallel to each other and a plurality of data lines insulated from and intersecting the gate lines are formed on the active region 30 of the lower substrate (TFT array substrate) according to the present invention. D1 to Dn are formed, and the gate lines and the data lines are alternately arranged to define a plurality of pixel regions 'P'.

In this case, a thin film transistor TFT is formed at a portion where the gate line and the data line cross each other, and a storage capacitor having a storage capacitance Cst is formed between the front gate line and the drain electrode. A capacitor, which is a liquid crystal capacitor Clc, is formed between the pixel electrode connected to the drain electrode and the common electrode.

The pixel area 'P' defined in the active area is an effective pixel area that is actually driven and displayed.

In addition, the first, second and third dummy pixel areas 33a, 33b, and 33c having the same configuration as the pixel area of the active area 30 are formed in the outermost dummy area 31 of the active area 30 of the lower substrate. Is placed.

In this case, the dummy pixel area may be formed by selecting one or two of the first, second, and third dummy pixel areas 33a, 33b, and 33c, or may form a plurality of other dummy pixel areas in the dummy area. have.

Each of the first, second, and third dummy pixel areas 33a, 33b, and 33c includes a dummy thin film transistor, a dummy storage capacitor as the storage capacitor Cst, a dummy capacitor as the liquid crystal capacitor Clc, and a dummy gate line. And a dummy data line is disposed.

In this case, the dummy data lines of the first and third dummy pixel areas 33a and 33c are disposed before the first effective pixel area of the active area (left side) and are called the first dummy data line DFL, and the second dummy data line is referred to as a second dummy data line. The dummy data line of the pixel region 33b is disposed after the effective pixel region (right side) of the active region and is called a second dummy data line DFR.

In this case, the first dummy pixel area 33a is disposed before (left) the last pixel area of the line where the first effective pixel area of the active area is disposed, and the second dummy pixel area 33b is the last effective pixel area of the active area. The third dummy pixel region 33c is disposed after the first pixel region (right side) of the arranged line, and the third dummy pixel region 33c is disposed before the first pixel region (left) of the line where the first effective pixel region of the active region is disposed. .

In this case, the first, second, and third dummy pixel areas 33a, 33b, and 33c may be disposed anywhere in the dummy area 31 before / after the effective pixel area of the active area 30.

Also, the first, second, and third pixel feedback voltages V1, V2, and V3 are output to the common voltage generator 60 in the first, second, and third dummy pixel areas 33a, 33b, and 33c. Delivered.

The first, second, and third pixel feedback voltages V1, V2, and V3 output through the first, second, and third dummy pixel areas 33a, 33b, and 33c are respectively disposed in the pad region 34 of the lower substrate. The first, second, and third feedback data pads 32a, 32b, and 32c which are received and output to the source driver IC 40 and the gate driver IC 50 are configured.

As illustrated in FIG. 4, the source driver IC 40 includes a second chip 41, pads attached to a panel, and pads attached to a printed circuit board (PCB).

At this time, the pads attached to the panel are pads for receiving a signal from the first chip 41 and outputting them to the first and second dummy data lines DFL and DFR, and the pads formed in the pad region 34 of the lower substrate. 2, pads attached to the third feedback data pads 32b and 32c to transfer the second and third pixel feedback voltages V2 and V3, and the common voltage Vcom output from the common voltage generator 60. Pads for delivery.

The pads attached to the PCB include pads connected to the pads to be attached to the second and third feedback data pads 32b and 32c formed on the pad region 34 of the lower substrate, and the common voltage Vcom. It is composed of pads for delivering.

In this case, the pads for outputting data signals to the first and second dummy data lines DFL and DFR do not actually drive the active region, but the thin film transistor TFT disposed in the pixel region of the active region 30 is turned off. After OFF), in order to accurately detect the potential variation of the pixel region due to ΔVp and leakage current for each voltage of the pixel region, it should be designed to determine the range of the applied voltage.

For example, when the driving voltage of the liquid crystal is 5V and the power supply voltage Vdd is 10V, the variable range of the first and second dummy data lines DFL and DFR is 0 to 10V.

At this time, the polarity of the first and second dummy data lines DFL and DFR should be output with the opposite polarity based on the common voltage Vcom as shown in FIG. 6, and the polarity should be inverted every one frame period. This is for driving under the same conditions as the pixel region of the active region.

The second and third pixel feedback voltages (pixel voltages) receiving the first and second dummy data lines DFL and DFR are second and third feedback data pads connected to the second and third dummy pixel areas. It is transferred onto the printed circuit board (PCB) through 32b and 32c.

Next, as shown in FIG. 5, the gate driver IC 50 includes a second chip 51, pads attached to the panel, and pads attached to the printed circuit board (PCB).

In this case, the pads attached to the panel are pads to be attached to the first feedback data pad 32a of the pad region 34 of the lower substrate, and pads for applying the common voltage Vcom output from the common voltage generator 60. It consists of

A plurality of pads to be attached to the first feedback data pad 32a may be disposed depending on the number of pads to be attached to the left side of the active area among the pad areas 34 of the lower substrate.

The pads attached to the PCB include pads connected to the pad to be attached to the first feedback data pad 32a formed in the pad region 34 of the lower substrate, and pads to which the common voltage Vcom is applied. It is composed.

The gate driver IC 50 receives the first pixel feedback voltage V1 transmitted through the first dummy pixel region 33a through the first feedback data pad 32a and feeds it back to the printed circuit board PCB. do.

As described above, the first, second, and third pixel feedback voltages V1, V2, and V3 output through the first, second, and third dummy pixel areas 33a, 33b, and 33c of the lower substrate are applied to the common substrate. As shown in FIG. 7, the voltage generator outputs the common voltage Vcom through the amplifying means 70, and the common voltage of the gate driver IC 50 and the source driver IC 40 is applied to the output common voltage. The pads are input to the common electrode of the upper panel of the liquid crystal panel.

In this case, a ground line having a first resistance value R1 is connected to one input terminal of the amplifying means 70, and first, second, and third pixel feedback voltages V1, V2, and V3 are selectively connected to a type force terminal. In addition, a power line having a resistance value R2 of '0?' Is connected to one input terminal and the output terminal of the amplifying unit 70.

In consideration of the delay of the gate line and the data line, the first, second, and third pixel feedback voltages V1, V2, and V3 are selectively added to the type force stage of the amplifying means 70 so that an optimum common voltage can be output. A switch control unit 71 that can be connected is provided.

In this case, when the first and second pixel feedback voltages V1 and V2 are selected, the common voltage Vcom is a value obtained by averaging the first and second pixel feedback voltages V1 and V2, and the second and third pixel feedback voltages. When V2 and V3 are selected, the common voltage Vcom is a value obtained by averaging the second and third pixel feedback voltages V2 and V3.

As described above, the first and second dummy data lines are disposed in the left and right dummy areas of the active area of the lower substrate, and the first, second and third dummy are located in the dummy area located at the outermost part of the active area of the lower substrate. A pixel region, and applying the first, second, and third pixel feedback voltages outputted through the pixel region to the common voltage generator through feedback data pads of the gate driver IC and / or the source driver IC. Since the output common voltage is applied to the common electrode of the upper panel of the liquid crystal panel through the common voltage output pads of the source driver IC and the gate driver IC, an optimum common voltage can be applied to the liquid crystal panel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the above embodiments, but should be defined by the claims.

The liquid crystal display device having the common voltage generator of the present invention as described above has the following effects.

Since the common voltage can be automatically set without the need for a variable resistor, the common voltage can be easily set, and an optimum common voltage can be generated at each time, thereby preventing flicker and afterimage phenomenon.

Claims (5)

A liquid crystal display for applying a common voltage to a common electrode of a liquid crystal panel having a lower substrate having an active region, a dummy region, and a pad region defined therein, A pixel region defined by a gate line and a data line intersecting the active region; A dummy pixel area formed in a plurality of dummy areas on the left and right sides of the active area; First and second dummy data lines arranged in one direction in the dummy areas on the left and right sides of the active area to drive the dummy pixel area; A plurality of feedback data pads for outputting respective pixel feedback voltages to be output through the dummy pixel areas to the pad area; A common voltage generator receiving the pixel feedback voltages to generate a common voltage; First pads for applying voltage to the first and second dummy data lines, second pads connected with the feedback data pads, and third for applying the common voltage to the common electrode of the liquid crystal panel. A source driver IC composed of pads; And a gate driver IC comprising fourth pads connected to the feedback data pads and fifth pads for applying the common voltage to the common electrode. . The method of claim 1, The dummy pixel areas are A first dummy pixel region disposed before (left) the last pixel region of the line where the first pixel region of the active region is disposed; A second dummy pixel area disposed after (right) the first pixel area of the line where the last pixel area of the active area is disposed; And a third dummy pixel area disposed before (left) the first pixel area of the line in which the first effective pixel area of the active area is disposed. The method of claim 1, In the common voltage generator, one input terminal is connected to a ground line having a first resistance value, the pixel feedback voltages are selectively connected to a type force terminal, and a power line having a second resistance value is connected to one input terminal and an output terminal. Amplification means; And a switch control unit for controlling the pixel feedback voltages to be selectively connected to the type force terminal of the amplifying means. The method of claim 3, wherein The second resistance value is '0Ω' liquid crystal display device having a common voltage generator, characterized in that. The method of claim 1, A plurality of gate lines in the pixel region of the active region; A plurality of data lines D1 to Dn insulated from and intersecting the gate lines; A thin film transistor (TFT) formed at a portion where the gate line and the data line cross each other; A storage capacitor formed between a front gate line and a drain electrode of the thin film transistor; And a capacitor for accumulating liquid crystal capacitance (Clc) between the drain electrode and the common electrode of the thin film transistor.