KR20040060129A - Method for fabricating capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to prevent collapse of a storage node electrode by removing a lower oxide layer using second wet-etching without using an additional mask. CONSTITUTION: An interlayer dielectric(42) is formed on a substrate(40). The first oxide layer(48) having the capacitor height of 50-90% is formed on the resultant structure. An etch barrier layer(50) made of a nitride layer is formed on the first oxide layer. The second oxide layer(52) is formed on the etch barrier layer. A storage node contact hole is formed by etching the second oxide layer, the nitride layer and the first oxide layer. A storage node electrode(58) is formed in the storage node contact hole. The second oxide layer of a cell region is removed by first wet-etching. The etch barrier layer and the first oxide layer of the cell region are removed by second wet-etching.

Description

METHODS FOR FABRICATING CAPACITOR OF SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device. In particular, a cylindrical capacitor prevents defects such as collapse of the charge storage electrode during the removal process of the insulation film pattern by interposing an etch stop film in the middle of the insulation film used to form the charge storage electrode. A method of manufacturing a capacitor of a semiconductor device that can be prevented.

Generally, capacitors in DRAMs store a certain amount of charge to store and read information. Therefore, the capacitor should have sufficient capacitance, have the insulating property of the dielectric film with low leakage current, and have the reliability for repeated use for a long time.

The capacitance of the capacitor is proportional to the surface area and inversely proportional to the thickness of the dielectric film. As the device becomes more integrated, the allocation area of the unit element decreases, making it difficult to secure the capacitance of the capacitor. For this purpose, the height of the capacitor increases. As a result, process margins with adjacent cells are also decreasing.

1A to 1E are diagrams illustrating a capacitor manufacturing process of a semiconductor device according to the related art.

First, an interlayer insulating film 12 including a charge storage electrode contact plug 14 is formed on a semiconductor substrate 10, and an nitride film 16 as an etch barrier and an oxide film as a sacrificial film are formed on the interlayer insulating film 12. 18) and the hard mask layer 20 are sequentially formed.

Next, the first photoresist layer pattern 22, which is a charge storage electrode etch mask, is formed on the hard mask layer 20. (See FIG. 1A).

Thereafter, the hard mask layer 20, the oxide layer 18, and the nitride layer 16 are sequentially etched using the first photoresist layer pattern 22 as a mask to form a contact hole for a charge storage electrode exposing the contact plug 14. And the first photoresist pattern 22 is removed. At this time, the hard mask layer 20 is also removed.

Then, a conductive layer serving as a charge storage electrode is coated on the entire surface of the structure, and the conductive layer on the oxide film 18 is removed and separated to form a charge storage electrode 24. (See FIG. 1B).

Thereafter, in order to use both surfaces of the charge storage electrode 24, all the remaining portions of the oxide film 18 must be removed, thereby forming the second photoresist layer pattern 26 that protects the peripheral circuit region. (See FIG. 1C).

Then, the oxide film 18 exposed by the second photoresist layer pattern 26 is removed by a wet etching method, and the second photoresist layer pattern 26 is removed. (See FIG. 1D).

After that, the dielectric film 28 and the plate electrode 30 are formed on the surface of the charge storage electrode 24 to complete the capacitor. (See FIG. 1E).

In the method of manufacturing a capacitor of a semiconductor device according to the prior art as described above, the thickness of the oxide layer is increased to secure the capacitance of the capacitor, making it difficult to pattern one etching process, and both sides of the charge storage electrode In order to use the wet etching process to remove the oxide layer pattern,

At this time, the surface tension of the etching solution or the cleaning solution is also affected, and the capacitor is bent by the surface tension of the cleaning solution for removing the photoresist pattern. As shown in FIG. 2, the charge storage electrodes are written and short-circuited or separated from each other. Discarded defects are generated, and as the spacing between capacitors decreases, the probability of occurrence of the defects increases, and there are problems such as defects caused by photoresist residue.

In addition, if the peripheral circuit region is exposed due to misalignment or poor adhesion during the photoresist pattern process, there is a problem such as a pattern defect as shown in FIG. 3.

In addition, there is another problem that the step between the cell region and the peripheral circuit region is increased to make the subsequent process more difficult.

The present invention is to solve the above problems, the object of the present invention is

In the manufacture of capacitors using the oxide pattern for the formation of the charge storage electrode, the etching process is performed by interposing an etch barrier layer in the middle of the oxide layer to solve the etching process difficulties, and to prevent the charge storage electrode from falling or losing in the oxide removal process. In addition, the present invention provides a method of manufacturing a capacitor of a semiconductor device capable of preventing etching defects in a peripheral circuit area and improving process yield and device operation reliability.

1A to 1E are views illustrating a capacitor manufacturing process of a semiconductor device according to the prior art.

2 is a SEM photograph of a semiconductor device in which charge storage electrode collapse occurs.

3 is a SEM photograph of a semiconductor device in which a pattern defect occurs due to a poor adhesion of a photosensitive film pattern.

4A to 4F are capacitor manufacturing process diagrams of a semiconductor device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10, 40: semiconductor substrate 12, 42: interlayer insulating film

14, 44: contact plug 16, 46, 50: nitride film

18, 48, 52: oxide film 20, 54: hard mask layer

22, 26, 56, and 60: photoresist pattern 24, 58: charge storage electrode

28, 62: dielectric film 30, 64: plate electrode

The present invention is to achieve the above object, the characteristics of the capacitor manufacturing method of a semiconductor device according to the present invention,

Forming an interlayer insulating film on the semiconductor substrate having a cell region and a peripheral circuit region;

Forming a first oxide film having a height of 50 to 90% of a height necessary for securing a capacitor capacitance on the entire surface of the structure;

Forming an etch barrier layer on the first oxide film;

Forming a second oxide film having a remaining thickness on the etching barrier layer to secure capacitance;

Forming a contact hole for the charge storage electrode by selectively etching the second oxide film from the second oxide film using a charge storage electrode etching mask;

Applying and separating a conductive material layer over the entire surface of the structure to form a charge storage electrode in contact with the contact plug on the inner wall of the contact hole;

Forming a photoresist pattern that exposes the cell region and performing a first wet etching process using a mask to remove the second oxide layer of the cell region and to remove the photoresist pattern;

And removing the etch barrier layer and the first oxide layer under the cell region to expose the charge storage electrode.

In addition, the etching barrier layer is formed of a nitride film, it characterized in that it is formed to a thickness of 100 ~ 1000Å.

Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

4A to 4F are capacitor manufacturing process diagrams of a semiconductor device according to the present invention.

First, an interlayer insulating film 42 having a contact plug 44 for a charge storage electrode is formed on the semiconductor substrate 40, and the first nitride film 46 and the sacrificial film, which are etch barriers, are formed on the interlayer insulating film 42. The first oxide film 48, the second nitride film 50 as an etching barrier, the second oxide film 52, and the hard mask layer 54 are sequentially formed. At this time, the first oxide film 48 is formed to a height of 50 to 90% of the height required to secure the capacitance, the second nitride film 50 is formed to a thickness of 100 ~ 1000Å and the second oxide film 52 is The remaining 10 to 50% of the thickness is formed. The first nitride film 46 may not be formed above.

Thereafter, a first photoresist pattern 56 as a charge storage electrode etch mask is formed on the hard mask layer 54. (See FIG. 4A).

Subsequently, the hard mask layer 54, the second oxide film 52, the second nitride film 50, the first oxide film 48, and the first nitride film 46 are formed by using the first photoresist pattern 56 as a mask. Are sequentially removed to form a contact hole for the charge storage electrode, and the first photoresist pattern 56 is removed. At this time, the hard mask layer 54 is also removed.

Then, the conductive material layer for the charge storage electrode is applied to the entire surface of the structure, and the conductive material layer on the second oxide film 52 is removed to separate the charge storage electrode 58 connected to the contact plug 44. . (See FIG. 4B).

Thereafter, in order to use both surfaces of the charge storage electrode 58, all the remaining portions of the second oxide film 52, the second nitride film 50, and the first oxide film 48 should be removed, thereby protecting the peripheral circuit area. The second photosensitive film pattern 60 is formed. (See FIG. 4C).

Next, the second oxide film 52 of the cell region exposed by the second photoresist layer pattern 60 is removed by a first wet etching method, and the second photoresist layer pattern 60 is removed. At this time, the removed thickness is not so large that the defect of the charge storage electrode 58 does not occur. (See FIG. 4D).

Thereafter, a second wet etching process is performed without a separate mask to remove the exposed second nitride layer 46 of the cell region, remove the first oxide layer 48, and remove the second oxide layer 52 of the peripheral circuit region. ) Are also removed. At this time, since a separate photoresist pattern is not used, defects caused by surface tension of solutions due to the removal and cleaning of the photoresist layer are also prevented. In addition, since there is no separate mask, a process having a high etching selectivity between the nitride film and the oxide film may be used to prevent oxide loss in the peripheral circuit region. (See FIG. 4E).

Then, the dielectric film 62 and the plate electrode 64 are formed on the surface of the charge storage electrode 58 to complete the capacitor. (See FIG. 4F).

The nitride film interposed between the oxide films may be an oxynitride film or the like as a material having a difference in etching selectivity from the oxide film.

As described above, in the capacitor manufacturing method of the semiconductor device according to the present invention, the charge storage electrode is formed after the etching barrier layer is interposed in the middle of the oxide film for forming the charge storage electrode, and the upper oxide film is removed during the first wet process. Since the lower oxide film was removed by the second wet etching process without a separate mask, defects such as collapse or loss of the charge storage electrode due to the cleaning of the photoresist film are prevented, and pattern defects in the peripheral circuit area due to insufficient adhesion of the photoresist pattern Also, the step difference between the peripheral circuit region and the cell region is minimized, thereby facilitating subsequent processes, thereby improving process yield and reliability of device operation.

Claims (2)

Forming an interlayer insulating film on the semiconductor substrate having a cell region and a peripheral circuit region; Forming a first oxide film having a height of 50 to 90% of a height necessary for securing a capacitor capacitance on the entire surface of the structure; Forming an etch barrier layer on the first oxide film; Forming a second oxide film having a remaining thickness on the etching barrier layer to secure capacitance; Forming a contact hole for the charge storage electrode by selectively etching the second oxide film from the second oxide film using a charge storage electrode etching mask; Applying and separating a conductive material layer over the entire surface of the structure to form a charge storage electrode in contact with the contact plug on the inner wall of the contact hole; Forming a photoresist pattern that exposes the cell region and performing a first wet etching process using a mask to remove the second oxide layer of the cell region and to remove the photoresist pattern; And removing the etch barrier layer and the first oxide layer under the cell region to expose the charge storage electrode. The method of claim 1, The etching barrier layer is formed of a nitride film, the method of manufacturing a capacitor of a semiconductor device, characterized in that formed in a thickness of 100 ~ 1000Å.