KR20040059788A - Method for fabricating capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to fabricate a capacitor of a reliable high-integrated semiconductor device by fabricating uniform crystallinity of a dielectric thin film of the capacitor. CONSTITUTION: A metal layer for a lower electrode is formed on a substrate(20). A dielectric thin film is formed on the metal layer for the lower electrode. A buffer metal layer is formed on the dielectric thin film. A heat treatment is performed to crystallize the dielectric thin film. The conductive layer for the lower electrode, the dielectric thin film and the buffer metal layer are simultaneously patterned to for the lower electrode, a patterned dielectric thin film and a patterned buffer metal layer. An interlayer dielectric(22) is formed on the resultant structure including the patterned buffer metal layer. The interlayer dielectric is polished to expose the patterned buffer metal layer by a CMP(chemical mechanical polishing) process. An upper electrode(28) is formed on the patterned buffer metal layer.

Description

Method for fabricating capacitor in semiconductor device

The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a capacitor of a semiconductor device.

As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.

Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.

The capacitance C of the capacitor is defined as in Equation 1 below.

C = ε · As / d

Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.

Therefore, in order to increase the capacitance of the capacitor, the surface area of the electrode, the thickness of the dielectric thin film, or the dielectric constant must be increased.

Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures, such as concave structures, cylinder structures, multilayer fin structures, and the like, are all proposed to increase the effective surface area of electrodes in a limited layout area. However, this method has a limitation in increasing the effective surface area of the electrode as the semiconductor device is very high integration.

In addition, the method of reducing the thickness of the dielectric thin film in order to minimize the distance between electrodes (d) also faces the limitation due to the problem that the leakage current increases as the thickness of the dielectric thin film is reduced.

Therefore, in recent years, research and development have been focused on securing capacitance of a capacitor mainly by increasing the dielectric constant of a dielectric thin film. Traditionally, so-called NO (Nitride-Oxide) capacitors using silicon oxide or silicon nitride as the dielectric thin film have become mainstream, but recently, Ta ₂ O ₅ , (Ba, Sr) TiO ₃ (hereinafter referred to as BST) High dielectric materials such as (Pb, Zr) TiO ₃ (hereinafter referred to as PZT), (Pb, La) (Zr, Ti) O ₃ (hereinafter referred to as PLZT), SrBi ₂ Ta ₂ O ₉ (hereinafter referred to as SBT) SrBi ₂ (Ta _1-x , Nbx) ₂ O ₉ (hereinafter referred to as SBTN), Bi _4-x La _x Ti ₃ O ₁₂ (hereinafter referred to as BLT), Bi ₄ Ti ₃ O ₁₂ (hereinafter referred to as BIT Ferroelectric materials are applied as dielectric thin film materials.

In the manufacture of high dielectric capacitors or ferroelectric capacitors using such high dielectric materials or ferroelectric materials as dielectric thin film materials, proper control of dielectric surrounding materials and processes must be accompanied to realize dielectric properties specific to the high dielectric materials or ferroelectric materials. do.

In general, a noble metal or a compound thereof, such as Pt, Ir, Ru, RuO ₂ , IrO _2, or the like is used as the upper and lower electrode materials of the high dielectric capacitor and the ferroelectric capacitor.

1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.

First, as shown in FIG. 1A, the interlayer insulating film 12 is formed on the semiconductor substrate 10 on which the active region 11 is formed, and then penetrates the interlayer insulating film 12 to form an active region ( A contact hole connected to 11) is formed. Subsequently, the contact hole is filled with a conductive material to form the contact plug 13.

Subsequently, the lower electrode 14 is formed of a metal film such as Pt connected to the contact plug 13.

Subsequently, as shown in FIG. 1B, a capacitor insulating film 15 is formed to cover the lower electrode 14.

Subsequently, as shown in FIG. 1C, the capacitor insulating film 15 is removed using a chemical mechanical polishing process or the like so that the lower electrode 14 is exposed. Subsequently, a dielectric thin film 16 is formed thereon, and an upper electrode conductive film 17 is formed thereon. When the capacitor is formed as described above, it is not necessary to planarize before forming the upper electrode, thereby solving various problems caused by the step due to the capacitor structure.

Subsequently, as shown in FIG. 1D, the upper electrode conductive film 17 is patterned to form the upper electrode 17 '.

Since dielectric thin films are made of ferroelectric materials such as SBT, SBTN, BIL, and PZT, or high-dielectric materials such as STO and BST, a heat treatment process is necessary to improve the dielectric constant after forming a dielectric thin film. Was done.

However, as described above, when the dielectric thin film is formed and then subjected to heat treatment, the capacitor insulating film is formed around the lower electrode. Therefore, the crystallinity of the dielectric thin film is changed due to the nucleation site and the difference in distribution and crystallinity during the heat treatment process. It will have a deteriorating characteristic. The diffusion of P, B, Si, etc. from the insulating film 15 adjacent to the dielectric thin film into the dielectric thin film causes a large difference in crystallinity of the dielectric thin film.

As a result, the uniformity of the dielectric thin film becomes extremely poor depending on the unit cell of the memory device, thereby deteriorating operational reliability of the memory device.

It is an object of the present invention to provide a capacitor manufacturing method in which the dielectric thin film of a capacitor of a highly integrated semiconductor device has uniform crystallinity in a manufacturing process, thereby improving operational reliability of the semiconductor device.

1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

20: substrate

21: active area

22: interlayer insulating film

23: Contact Plug

24: conductive film for lower electrode

25: dielectric thin film

26: buffer metal film

27: capacitor insulating film

28: upper electrode

Forming a lower electrode metal film on the substrate to achieve the above object; forming a dielectric thin film on the lower electrode metal film; Forming a buffer metal film on the dielectric thin film; Performing a thermal process for crystallizing the dielectric thin film; Simultaneously patterning the conductive film for the lower electrode and the dielectric thin film and the buffer metal film to form a lower electrode and the patterned dielectric thin film and the patterned buffer metal film; Forming an interlayer insulating film on the entire structure including the patterned buffer metal film; Polishing the interlayer dielectric layer by a chemical mechanical polishing process to expose the patterned buffer metal layer; And forming an upper electrode on the patterned metal film for the buffer.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2E are views showing a capacitor manufacturing method of a semiconductor device according to a preferred embodiment of the present invention.

First, as shown in FIG. 2A, the interlayer insulating film 22 is formed on the semiconductor substrate 20 on which the active region 21 is formed, and then penetrates the interlayer insulating film 22 to form the active region of the semiconductor substrate 20 ( A contact hole connected to 21 is formed. Subsequently, the contact hole is filled with a conductive material to form the contact plug 23. The interlayer insulating film 22 may be made of undoped-silicate glass (USG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), high density plasma (HDP) oxide, spin on glass (SOG) film, and TEOS ( Tetra Ethyl Ortho Silicate (HDT) or oxide film using HDP (high densigy plasma) can be used or thermal oxide (Thermal Oxide) can be formed by oxidizing a silicon substrate at a high temperature between 600 and 1100 ℃ in the furnace .

Although not shown, when the conductive material forming the contact plug is conductive polysilicon, an ohmic contact layer is formed on the contact plug 23 to form an ohmic contact between the metal lower electrodes to be formed in a subsequent step, and the ohmic contact layer is formed. Forms a barrier metal. Barrier metal is a film for preventing interdiffusion between neighboring silicon films and metal films and preventing oxygen penetration into the substructure during the high temperature heat process.

When the contact plug is formed of a metal film such as tungsten, an ohmic contact layer is formed on the contact surface with the active region, and a barrier metal is formed on the contact plug. The ohmic contact layer is formed of titanium silicide or the like, and the barrier metal is formed of titanium nitride.

Subsequently, a lower electrode conductive film 24 is formed on the front surface of the substrate. Pt, Ir, W, Ru films are used as the lower electrode conductive film 24.

Subsequently, as shown in FIG. 2B, a dielectric thin film 25 is formed on the conductive film 24 for the lower electrode. Here, the nucleation of the dielectric thin film 25 is performed in the range of 400 ~ 900 ℃ by the RTA (rpaid thermal anneal) method.

Subsequently, a buffer metal layer 26 is formed on the dielectric thin film 25. The buffer metal film 26 is a thin film for preventing impurities from infiltrating from surroundings and inhibiting the crystallization of the dielectric thin film during the high temperature thermal process of the dielectric thin film. The buffer metal film 25 is chemical vapor deposition, physical vapor deposition, spin coating using an iridium, an iridium oxide film, or an iridium / iridium oxide film thereof. (spin coating), etc. to form.

Subsequently, a thermal process for grain growth that enlarges the permsky nucleus of the dielectric thin film is followed by O ₂ , N ₂ O, N ₂ + O ₂ , N ₂ , Ar, Ne, Kr in the range of 500-800 ° C. in the furnace. The process is performed using gases such as Xe, He, H ₂ O, and H ₂ O ₂ .

In this case, since the lower electrode conductive film 24 and the buffer metal film are formed on the upper and lower portions of the dielectric thin film 25, a conventional P, B, Si, or the like material does not penetrate into the dielectric thin film 25, and thus, during thermal processing. The crystallization of the dielectric thin film is not disturbed.

As the dielectric thin film 25, ferroelectric such as SBT, SBTN, BIT, BLT or PZT is used, or a high dielectric material such as Ta ₂ O ₅ , HfO ₂ , Al ₂ O ₃ , SrTiO ₃ , BST is used. Form a thickness in the range of ~ 3000Å. The dielectric thin film 25 uses atomic layer deposition, chemical vapor deposition, physical vapor deposition, spin coating, liquid source mixed deposition, or the like.

Subsequently, as shown in FIG. 2C, the lower electrode conductive film 24, the dielectric thin film 25, and the buffer metal film 26 are simultaneously patterned to form the lower electrode 24 ′ and the patterned dielectric thin film 25 ′. A buffer metal film 26 is formed. In order to simultaneously pattern the lower electrode conductive film 24, the dielectric thin film 25, and the buffer metal film 26, TiN, TiAlN, polysilicon film, oxide film, etc. may be used in the range of 300 to 2000 microseconds as a hard mask. In order to remove these hard masks, SC-1 cleaning process using NH ₄ OH + H ₂ O ₂ + H ₂ O mixture, Pyranha washing using H ₂ SO ₄ + H ₂ O ₂ + H ₂ O mixture Use the process.

When the conductive film 24 and the dielectric thin film 25 for the lower electrode are simultaneously patterned, plasma activation energy is used and Cl, Ar, and N ₂ are used as etching gases. The plasma power is in the range of 500 to 3000 watts, and the pressure is 0.5 mtorr. Process in the range of ~ 30 torr.

Here, the lower electrode may be formed of Pt / IrO ₂ / Ir laminated with platinum used as an electrode material, iridium for preventing oxygen infiltration during thermal processing, and iridium oxide for preventing interdiffusion of platinum and iridium, in which case platinum Is formed in the range of 500 to 3000 mV, IrO ₂ is formed in the range of 50 to 1000 mV and Ir is formed in the range of 50 to 3000 mV.

Subsequently, as shown in FIG. 2D, a capacitor insulating film 27 is formed in a range of 1000 to 10000 占 to cover the lower electrode 24 ′ and the patterned dielectric thin film 25 ′ / buffer metal film 26 ′. The capacitor insulating film 27 is removed using a chemical mechanical polishing process so that the patterned buffer metal film 26 'is exposed. At this time, the buffer metal film 26 'acts as a buffer layer in the chemical mechanical polishing process.

Here, the capacitor insulating film 27 may be made of Undoped-Silicate Glass (USG), Phospho-Silicate Glass (PSG), Boro-Phospho-Silicate Glass (BPSG), High Density Plasma (HDP) oxide, Spin On Glass (SOG) film, and TEOS. (Tetra Ethyl Ortho Silicate) or an oxide film using HDP (high densigy plasma), or a thermal oxide film (Thermal Oxide) can be formed into a film formed by oxidizing a silicon substrate at a high temperature of 600 ~ 1,100 ℃ in the furnace. have.

Next, as shown in FIG. 2E, an upper electrode 28 is formed on the patterned dielectric thin film 25 ′ with a thickness in the range of 500 to 3000 μs. Pt, Ir, Ru, RuO ₂ , IrO ₂ , W, WN, TiN, and polysilicon films may be used as the upper electrode. Since the buffer metal film formed under the upper electrode is conductive, a separate process is not necessary.

As described above, the crystallization of the dielectric thin film 25 can be made uniform by performing the thermal process for crystallization with the dielectric thin film 25 between the lower electrode conductive film 24 and the buffer metal film 26. Thus, the capacitor can be manufactured more reliably.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the dielectric thin film crystallinity of the capacitor can be produced uniformly, and thus the capacitor of the highly reliable semiconductor device can be manufactured.

Claims (7)

Forming a metal film for the lower electrode on the substrate; Forming a dielectric thin film on the lower electrode metal film; Forming a buffer metal film on the dielectric thin film; Performing a thermal process for crystallizing the dielectric thin film; Simultaneously patterning the conductive film for the lower electrode and the dielectric thin film and the buffer metal film to form a lower electrode and the patterned dielectric thin film and the patterned buffer metal film; Forming an interlayer insulating film on the entire structure including the patterned buffer metal film; Polishing the interlayer dielectric layer by a chemical mechanical polishing process to expose the patterned buffer metal layer; And Forming an upper electrode on the patterned buffer metal film Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1, The buffer metal film is a iridium, ruthenium, iridium oxide film, ruthenium oxide film or a film manufacturing method of a capacitor of a semiconductor device, characterized in that a stacked film thereof. The method of claim 1, The buffer metal film is a capacitor manufacturing method of the semiconductor device, characterized in that the thickness in the range of 100 ~ 3000Å. The method of claim 1, The dielectric thin film is a capacitor manufacturing method of a semiconductor device, characterized in that formed using a rapid heat treatment method at a temperature in the range of 400 ~ 800 ℃. The method of claim 1, The thermal process is characterized in that the process using the at least one gas selected from O ₂ , N ₂ O, N ₂ , Ar, Ne, Kr, Xe or He in the range of 500 ~ 800 ℃ in the furnace (furnace) A method for manufacturing a capacitor of a semiconductor device. The method of claim 1, And the dielectric thin film is one selected from SBT, SBTN, BIT, BLT, and PZT. The method of claim 6. The dielectric thin film is a capacitor manufacturing method of the semiconductor device, characterized in that to form a thickness in the range of 50 ~ 3000Å.