KR20040059343A - Modular computation apparatus of mobile communication system - Google Patents

Abstract

PURPOSE: A modular operation unit of a mobile communication system is provided to process rapidly a modular operation by using an initial modular operation value in the modular operation process. CONSTITUTION: A first modular operation unit(100) is formed with a plurality of operators to output modular operation output signals and MUX control signals. A first MUX(200) is used for selecting the modular operation output signals by the MUX control signals of the first modular operation unit. A register(300) is used for storing output signals of the first MUX or output signals of a second MUX(500). An adder(600) is used for adding the stored value of the register to a row variable value of an interleaver. A second modular operation unit(400) is formed with a plurality of operators to output modular operation output signals and MUX control signals. The second MUX is used for selecting the modular operation output signals by the MUX control signals of the second modular operation unit.

Description

MODULAR COMPUTATION APPARATUS OF MOBILE COMMUNICATION SYSTEM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleaver in a mobile communication system, and more particularly, to a modular computing device for a mobile communication system which processes the encoding processing speed of a turbo encoder in real time.

In general, a turbo code is a code generated by connecting two Recursive Systematic Convolutional Codes (RSC codes) in parallel through an interleaver, and used to transmit high data rates in a next generation mobile communication standard. It is used as a coding scheme.

These turbo codes are processed in block units for the generated information bit streams. In particular, when encoding a large information bit stream, the turbo code has a very good coding gain for the convolutional code. It is known to have an error correction capability at which the bit error rate reaches 10 ^-5 at 0.7 dB.

However, when the block unit for the generated information bit stream is smaller than the block length required by the communication system, the redundant bits should be inserted and channel coded. In this case, coding using a convolutional code method having the same complexity The performance is relatively slow compared to the method.

Therefore, while conventionally, convolutional codes are applied to small blocks and turbo codes are applied to large blocks, it is reasonable in terms of performance. However, in the next-generation mobile communication standard, smaller blocks are used not only for convolutional codes but also for turbo codes. It requires a definition of

Therefore, in the conventional next generation mobile communication rule, the size of the minimum block to be encoded is determined, and the encoding of the information block smaller than the size is filled with 0 and encoded.

1 is a view showing the structure of a general turbo encoder.

Referring to FIG. 1, a parallel concatenated turbo encoder, which is an encoder of a turbo code, includes two constituent encoders 10 and 11 connected in parallel and an interleaver inserted therebetween ( 12).

In the first component encoder 10, a parity bit (y _0k ) is inserted into the information bit (z _k ), and in the second component encoder (11), an error detection bit (for the interleaved information bit (z _k ') y _1k ') is inserted.

The parallel coupled turbo encoder according to the related art outputs the information bits and the error detection bits in the order of (z _k y _0k y _1k ').

Therefore, the original information bit string is composed of N bit strings such as {x ₁ , x ₂ , x ₃ , .., x _k , ..., x _N }, and the number of information bit strings is the next generation communication. In the prior art, the information bit streams are first described by {z ₁ = x ₁ , z ₂ = x ₂ , z ₃ = x ₃ , ..., z. _N = x _N , z _{N + 1} = 0, z _{N + 2} = 0, ..., z _NL-1 = 0z _NL = 0} and converts into bit strings followed by {z ₁ , z ₂ , z ₃ , ..., z _NL } is turbo encoded.

In the case of using a component coder having a 1/3 coding rate as shown in FIG. 1, the coding bit string generated by converting to {z ₁ , z ₂ , z ₃ ,..., Z _NL } and performing turbo encoding is as follows. Same as

Cystetic bit string = {z ₁ , z ₂ , z ₃ , .., z _k , .., z _N , z _{N + 1} , .... z _NL , z _T1 , z _T2 , z _T3 , z _T1 ' _, z _T2 ' _, z _T3 '}

First parity bit string = (y ₀₁ , y ₀₂ , y ₀₃ ,., Y _0k , ..., y _0N , y _{0 (N + 1)} , y _{0 (N + 2)} , ...., y _0NL, y _0T1 , y _0T2 , y _0T3 }

Second parity bit string = {y ₁₁ ', y ₁₂ ', y ₁₃ ', .. y _1k ' .., y _1N ', y _{1 (N + 1)} ', y _{1 (N + 2)} ',. ..., y _1NL ', y _1T1 ', y _1T2 ', y _1T3 '}

The {z _{N + 1} , .... z _NL } is a bit with 0 bits redundantly inserted into the information bit string, and the {y _{N + 1} , y _{N + 2} , ...., y _NL } and The portion of {y _{1 (N + 1)} ', y _{1 (N + 2)} ', ...., y _1NL '} is inserted with a value of 0 to fit the minimum block size in the information bit stream. The part is a part that is output in a repetitive bit pattern with a constant period in the first parity bit stream and the second parity bit stream in the encoding process, respectively, and the {z _T1 , z _T2 , z _T3 , z _T1 ' _, z _T2 ' _, z _T3 '}, the {y _0T1 , y _0T2 , y _0T3 } and {y _1T1 ', y _1T2 ', y _1T3 '} mean termination bits.

2 is a block diagram showing the configuration of the modular arithmetic unit of the interleaver, and is composed of a subtractor 1 and a comparator 2 in hardware.

Referring to the modular calculation process, first, the modular equation is the same as the following equation.

[Equation]

K = (jxr _i ) mod (p -1) j = 0, 1, ... ( p -2)

At this time, the input value of the turbo interleaver is the prime number 'p' determined by the size of the input code block of the turbo interleaver as shown in FIG. 3 and the row variable 'ri' as shown in FIG. 4.

For example, as a result of the subtraction operation A-B = C, if C and B are larger than B and continuously compared to C-B => C, C value when C is smaller than B becomes the output value of the modular.

Where A is (jxr _i ) and B is (p-1).

If r _{i =} 79 p = 257 and j = 255,

(79 x 255) modular (257-1) = (20145) modular (256)

. Step 1: 20145 -256 = 19889, 19889> 256

Step 2: 19889 -256 = 19633, 19633> 256

Step 3: 19633-256 = 19377, 19377> 256

4 steps: 19377-256 = 19121, 19121> 256

Step 5: 19121-256 = 18865, 18865> 256

Step 6: 18865 -256 = 18609, 18609> 256 ...

In the above modular operation, the j value is the maximum (257-1) and the ri value is the maximum 79. Therefore, the value of the maximum is 19889. Occurs.

However, due to such a repetitive operation of the modular operation is caused a large time delay in hardware, this time delay has a problem of delaying the processing speed of the turbo interleaver proceeds sequentially.

The present invention has been made to solve the above problems, in the case of modular operation, the initial modular operation value when the column variable is 1 is calculated and stored in some cases, and then the modular operation by using the stored value in the modular operation It is an object of the present invention to provide a modular computing device of a mobile communication system that allows for rapid processing of modular operations by reducing the steps.

1 is a view showing the structure of a typical turbo encoder.

FIG. 2 is a block diagram showing the configuration of a modular computing device of an interleaver in FIG.

3 shows a prime number determined by the size of an input code block of a turbo interleaver.

4 shows a low variable of a turbo interleaver.

Figure 5 is a block diagram showing the configuration of a modular computing device of the mobile communication system of the present invention.

FIG. 6 is a block diagram showing the configuration of a calculator in FIG.

***** Description of the symbols for the main parts of the drawings *****

100,400: Modular operation unit 101 ~ 104,401,402: Operator

200,500: Mum 300: Adder

The present invention for achieving the above object, the predetermined number of row variable value of the interleaver and the multiplication of the sequentially increasing column variable and the prime number, and a plurality of output the modular operation output signal and mux control signal accordingly A first modular calculator comprising an operator of; A first mux for selecting a modular arithmetic output signal output from the plurality of arithmetic units by a mux control signal of the first modular arithmetic unit; A register configured to store a signal output from the first mux or an output signal output from the second mux; An adder for adding a value stored in the register with a row variable value of an interleaver; A second modular operation unit comprising a plurality of arithmetic units configured to perform predetermined processing with output values of the adder, multiplying the column variable and the prime number, and outputting the modular output signal and the mux control signal accordingly; And a second mux for selecting a modular output signal output from the plurality of calculators by the mux control signal of the second modular calculation unit.

Hereinafter, with reference to the accompanying drawings, the operation and effects of the modular computing device of the mobile communication system according to the present invention will be described in detail.

5 is a block diagram showing a configuration of a modular computing device of a mobile communication system according to an embodiment of the present invention.

As shown in Fig. 5, the row variable value ri of the interleaver is subjected to predetermined processing with the multiplication of the sequentially increasing column variable j and the prime number p-1, and accordingly the modulated output signal A first modular calculating unit (100) comprising a plurality of calculating units (101 to 104) for outputting a mux control signal; A first mux 200 for selecting a modular arithmetic output signal output from the arithmetic units 101 to 104 by a mux control signal of the first modular arithmetic unit 100; A register 300 for storing a signal output from the first mux 200 or an output signal output from the second mux 500; An adder (600) for adding a value stored in the register (300) and a row variable value (ri) of an interleaver; Arithmetic operators 401 and 402 that process the output signal of the adder 600 and the multiplication values of the column variable j and the prime number p-1 which sequentially increase, and output a modular output signal and a mux control signal accordingly. A second modular operation unit 400 formed of; The second mux 500 selects a modular output signal output from the calculators 401 and 402 by the mux control signal of the second modular calculation unit 400.

Fig. 6 is a block diagram showing the configuration of the operator 101. A comparator 1 for comparing a multiplied previous column variable with a prime number, a multiplied current column variable with a prime number, and a row variable; It consists of a subtractor 2 which subtracts the previous column variable from any row variable, and this operation of the present invention will be described.

First, the modular operation of the interleaver performs (jxr _i ) mod (p-1), where p is a prime number determined by the size of the input code block of the turbo interleaver, j is a column variable of the interleaver, ri is a low variable.

Here, the operation of the present invention will be described assuming that the row variable value is '5'.

First, the calculators 101 to 104 of the first modular calculator 100 process the multiplied values of the column variable j and the prime number p-1, and output a modular operation output signal and a mux control signal accordingly. The comparator 1 of the calculators 101 to 104 multiplies the previous column variable j with the prime number p-1, the current column variable j with the prime number p-1, and Compare the row variable (ri), output the mux control signal accordingly, and the subtractor (2) subtracts the product of the current column variable (j) and prime number (p-1) in the row variable (ri) Outputs the modular operation output signal accordingly.

That is, since the row variable value ri is 5, the j value increases while the five r values of r _0, r _1, r _2, r _{3, and} r ₄ are cyclically increased, and if j is 1, the modular operation Is (r _i ) mod (p-1), where a case is defined as shown in FIG. 4 according to the range of ri values.

The modular value obtained by the five cases defined in FIG. 4 is stored in the register 300, and as the value of the column variable j increases, the output of the second modular operator 400 is obtained as follows.

j = 1: reg = (r _i ) mod (p-1) value obtained by case

j = 2: (r _i x2) mod (p-1) = (reg + ri) mod (p-1)

j = 3: (r _i x3) mod (p-1) = (reg + ri) mod (p-1) .....

When the modular value is obtained in the above manner, the initial modular calculation value when j = 1 is calculated according to the case, and the modular function is implemented by only two steps of subtraction in the calculators 401 and 402 of the second modular calculation unit 400. It will output data every clock.

That is, the modular operation output signal output from the calculators 101 to 104 is selected by the mux control signal of the first modular operation unit 100. In this case, when the column variable j is '0', The modular operation output signal is stored in the register 300.

Here, each time the column variable j is increased, the current modular operation output signal is added to the value stored in the register 300 and the adder 600 and input to the second modular operation unit 400. The arithmetic operators 401 and 402 of the second modular operator 400 process the output signal of the adder 600 and the multiplied values of the column variable j and the prime number p-1 sequentially increasing. Outputs an output signal and a mux control signal.

Thereafter, the mux 500 selects the output signal of the second modular operation unit 400 as the mux control signal, stores the result in the register 300, and outputs the result to the outside.

The specific embodiments or examples made in the detailed description of the present invention are intended to clarify the technical contents of the present invention to the extent that they should not be construed as limited to these specific embodiments and should not be construed in consultation. Various changes can be made within the scope of.

As described in detail above, the present invention, in the modular operation, by calculating and storing the initial modular operation value when the column variable is 1 according to the case, by reducing the modular operation step by using the stored value in the modular operation, This has the effect of quickly processing modular operations.

Claims (2)

A first modular calculator comprising a plurality of calculators which process a row variable value of the interleaver with a multiplication of sequentially increasing column variables and prime numbers, and output a modular arithmetic output signal and a mux control signal accordingly; A first mux for selecting a modular arithmetic output signal output from the plurality of arithmetic units by a mux control signal of the first modular arithmetic unit; A register configured to store a signal output from the first mux or an output signal output from the second mux; An adder for adding a value stored in the register with a row variable value of an interleaver; A second modular operation unit comprising a plurality of arithmetic units configured to perform a predetermined process with multiplying the output signal of the adder, the multiplication value of the column variable and the prime number sequentially, and output a modular output signal and a mux control signal accordingly; And a second mux for selecting a modular output signal outputted from the plurality of calculators by the mux control signal of the second modular calculator. The method of claim 1, wherein the plurality of calculators, A comparator for comparing the product of the previous column variable with the prime number, the product of the current column variable with the prime number, and the row variable, respectively; A modular computing device for a mobile communication system, comprising: a subtractor for subtracting a previous column variable from an arbitrary row variable.