KR20040059277A - Flash Memory Device And Method For Manufacturing The Same - Google Patents

Abstract

PURPOSE: A flash memory device and a manufacturing method thereof are provided to restrain electron transfer by dividing a tunnel nitride layer into nitride patterns and to adjust easily the interval between the nitride patterns by using a spacer as an etching mask. CONSTITUTION: A nitride layer, a sacrificial oxide layer(51) and a hard mask layer(53) are sequentially deposited on the first oxide layer(40). A photoresist pattern with a predetermined window is formed on the hard mask layer. A hard mask pattern is formed by performing RIE(Reactive Ion Etching) on the hard mask layer under CF4 gas atmosphere using the photoresist pattern as an etching mask. At this time, a spacer(57) is formed at sidewalls of the hard mask pattern. The nitride layer is divided into nitride patterns(50a,50b) by etching using the spacer and the hard mask pattern as an etching mask.

Description

Flash memory device and method for manufacturing the same {Flash Memory Device And Method For Manufacturing The Same}

TECHNICAL FIELD The present invention relates to a flash memory, and more particularly, to a flash memory device and a method of manufacturing the same, which prevent malfunction of a cell by blocking electron movement in a tunnel nitride film.

In general, semiconductor memory devices are classified into random access memory (RAM) and read only memory (ROM). The RAM is a volatile and fast data input and output, such as dynamic random access memory (DRAM) and static random access memory (SRAM), which erases data stored over time. Once the ROM has stored the data, it remains in that state, but the input and output of the data is slow. The ROM is subdivided into a ROM, a programmable ROM (PROM), an erasable PROM (EPROM), and an electrically erasable PROM (EEPROM). Recently, the demand for EEPROM that can electrically program or erase data is increasing rapidly. The cell of the flash memory having the EEPROM or the batch erase function has a stack-type gate structure in which a floating gate and a control gate are stacked.

The flash memory has a NAND type in which 16 cells are connected in series to form a unit string, and the unit string is connected in parallel between a bit line and a ground line, and each cell is a bit line. It is divided into NOR type which is connected in parallel between and ground line. The NAND flash memory is advantageous for high integration and the NOR flash memory is advantageous for high speed operation. The Noah-type flash memory uses a common source method. That is, one contact is formed every 16 cells, and the source lines of the 16 cells are generally connected to an n + diffusion layer.

On the other hand, the cell operation of the S-O-N-O-S flash memory device is classified into three operations of read, write, and erase similarly to nonvolatile memory devices. . In the write operation, when a program voltage is applied to the gate and the drain of the transistor of the cell, hot electrons are formed and then trapped in the nitride film of the adjacent region of the drain by tunneling of the gate insulating film. The threshold voltage of the transistor is increased. Thus, data is written. In the erase operation, when the gate, the drain and the source are opened, and an erase voltage is applied to the semiconductor substrate, electrons trapped in the nitride film are pushed to the semiconductor substrate, thereby lowering the threshold voltage. Thus, data is erased. In the read operation, a read voltage is applied to the gate and a current flowing between the source and the drain is sensed by the sensing circuit. Thus, the reading of the date is made.

As shown in FIG. 1, the S-O-N-O-S flash memory device having three operations of reading, writing, and erasing has each active region ACT for an unshown drain and source of each cell. The semiconductor substrate 10 extends in the longitudinal direction, and the active regions ACT are arranged side by side and spaced apart at regular intervals in the lateral direction. In addition, each word line WL is formed to extend in the horizontal direction to orthogonal to the active region ACT, and the word lines WL are arranged side by side and spaced apart at regular intervals in the longitudinal direction. A source S and a drain D are respectively formed in the active region ACT with the word line WL interposed therebetween. An isolation area ISO is disposed outside the active area ACT for isolation of the active area ACT.

However, in a transistor for a cell of a conventional S-O-N-O-S flash memory device, as shown in FIG. 2A, the active region between the source S and the drain D of the semiconductor substrate 10 is located. The oxide film 21, the nitride film 23, and the oxide film 25 for the word line WL of FIG. 1 are formed in the order from the lower side to the upper side, and the polycrystalline silicon layer 30 is formed on the oxide film 25. Is formed. Here, the oxide film 21, the nitride film 23, the oxide film 25 and the polycrystalline silicon layer 30 are all formed in the same pattern. In addition, as shown in FIG. 2B, the oxide film 21, the nitride film 23, the oxide film 25, and the polycrystalline silicon layer 30 are formed in the trench 11 of the active region and the isolation region of the semiconductor substrate 10. Are formed together on the insulating film 13 in the ().

However, in the conventional S-O-N-O-S flash memory device, since the turn-on current amount of the transistor can be adjusted according to the injection position of electrons, four types of '11', '10', '01', and '00' A multi-bit cell representing a state may be implemented. The '10' and '01' states can be generated only when electrons are locally limited to the source S side and the drain D side of the nitride film 13, respectively.

However, since the nitride film 23 is composed of one film which is not separated from each other, even if the nitride film 23 is an insulating film, one side of the nitride film 23, for example, the source S of the nitride film 23 is used. Electrons trapped on the side tend to move to the drain D side of the nitride film 23. This causes the cells of the S-O-N-O-S flash memory device to malfunction.

Accordingly, an object of the present invention is to prevent malfunction of a cell of an S-O-N-O-S flash memory device by suppressing electron movement in a tunnel nitride film.

Another object of the present invention is to reduce the cell size by easily adjusting the fine separation interval of the nitride film.

1 is a plan view showing a cell of a typical S-O-N-O-S flash memory.

2A and 2B are cross-sectional views taken along the lines A-A and B-B of FIG. 1, respectively.

3 is a cross-sectional view of a flash memory device according to the present invention.

4 to 9 are cross-sectional process diagrams illustrating a method of manufacturing a flash memory device according to the present invention.

Flash memory device according to the present invention for achieving the above object

Sources / drains formed spaced apart from each other in the active region of the semiconductor substrate; Patterns of a first oxide layer formed on the gate region between the source / drain and separated by a plurality of separation regions having a predetermined interval; Patterns of a nitride film formed on the patterns of the first oxide film, respectively; A pattern of a second oxide film formed together over the patterns of the nitride film and in the isolation region; And a pattern of a conductive layer formed on the pattern of the second oxide film.

Preferably, two or more patterns of the nitride film may be formed on the first oxide film.

Preferably, the patterns of the nitride film may be separated at intervals of 0.02 to 0.5 μm.

In addition, a method of manufacturing a flash memory device according to the present invention for achieving the above object is

Forming a first oxide film on the semiconductor substrate; Stacking a nitride film on the first oxide film and separating the nitride film into patterns of a plurality of nitride films at predetermined intervals; Stacking a second oxide film on the semiconductor substrate in the isolation region and on top of the patterns of the nitride film; Stacking a conductive layer on the second oxide film; And forming patterns of the conductive layer, the second oxide layer, and the nitride layer as a pattern for a gate by using a photolithography process.

Preferably, separating the patterns of the nitride film

Stacking a nitride film on the first oxide film and sequentially stacking a sacrificial oxide film and a hard mask layer on the nitride film; Forming a pattern of a photosensitive film having a predetermined window on the hard mask layer; Forming a spacer on a sidewall of the hard mask layer while etching the hard mask layer by using the pattern of the photoresist layer as an etching mask; And etching the sacrificial oxide film and the nitride film by using the spacer and the hard mask layer as an etching mask to separate the nitride film into patterns of the nitride film.

Preferably, two or more patterns of the nitride film may be separated.

Preferably, the patterns of the nitride film may be separated at intervals of 0.02 to 0.5 μm.

Preferably, separating the patterns of the nitride film

Exposing the sacrificial oxide layer by etching the spacer and the hard mask layer; And etching the sacrificial oxide film and the first oxide film of the isolation region to expose the patterns of the nitride film and the semiconductor substrate of the isolation region.

Preferably, the spacer can be formed of a polymer spacer.

Preferably, the hard mask layer may be formed of an oxide film or a nitride film of a TEOS series.

Hereinafter, a flash memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part of the same structure and the same action as the conventional part.

3 is a cross-sectional structural view showing a flash memory device according to the present invention. Referring to FIG. 3, in a cell of a flash memory device of the present invention, a first oxide film 40 is formed on a portion of a semiconductor substrate 10, and a separation gap D is separated on the first oxide film 40. The pattern of the first nitride film 50a and the pattern of the second nitride film 50b are disposed to be spaced apart from each other, and the pattern of the first nitride film 50a and the pattern of the second nitride film 50b, and the first interposed therebetween. The pattern of the second oxide film 60 is formed on the first oxide film 40, and the pattern of the polycrystalline silicon layer 70, which is a conductive layer, is formed on the pattern of the second oxide film 60. In addition, a source S and a drain D are formed on the semiconductor substrate 10 with the pattern of the polycrystalline silicon layer 70 interposed therebetween.

In the flash memory device configured as described above, the pattern of the first nitride film 50a and the pattern of the second nitride film 50b are spaced apart from each other with the separation region of the separation gap D therebetween. Therefore, the electrons trapped in one side of the pattern of the first nitride film 50a and the pattern of the second nitride film 50b, for example, the pattern of the first nitride film 50a, are different from the prior art. It becomes difficult to move to the pattern of 50b.

Therefore, the present invention can improve operational reliability by preventing malfunction of the cells of the S-O-N-O-S flash memory device.

A method of manufacturing a flash memory device according to the present invention configured as described above will be described with reference to FIGS. 4 to 9.

Referring to FIG. 4, first, a trench is formed in an isolation region (not shown) of a semiconductor substrate 10 using an isolation process such as a shallow trench isolation (STI) process, and an insulating film is buried in the trench. And flatten.

In this state, the first oxide film 40 is formed to a thickness of, for example, 50 to 150 Å by a thermal oxidation process on the active region of the semiconductor substrate 10, for example, the first conductivity type P-type single crystal silicon substrate. . Subsequently, a nitride film 50 is laminated on the first oxide film 40 to, for example, a thickness of, for example, 50 to 150 Pa by using a low pressure chemical vapor deposition process, and the sacrificial oxide film 51 is formed on the nitride film 50. ) 50-150 GPa and the hard mask layer 53 is laminated on the sacrificial oxide film 51 to a thickness of 1000-3000 GPa.

The hard mask layer 53 may be a TEOS (tetra ethyl ortho silane) type oxide film or nitride film. In particular, the hard mask layer 53 is preferably made of a material that is easily produced by the polymer when the dry etching process using, for example, CF ₄ gas.

Thereafter, the photoresist film 55 is coated on the hard mask layer 53, and the photoresist film 55 is positioned so that the window 56 of the photoresist film 55 is positioned on an area for a dual bit cell. ) Pattern.

Referring to FIG. 5, the surface of the sacrificial oxide layer 51 is exposed by dry etching the hard mask layer 53 using the pattern of the photoresist layer 55 as an etching mask. In this case, when the hard mask layer 53 is etched by a dry etching process, for example, a reactive ion etching process using CF ₄ gas, the polymer spacers 57 may be formed on both sidewalls of the hard mask layer 53. It can be formed.

Here, the bottom gap D of the polymer spacer 57 determines the size of the exposed region of the sacrificial oxide film 51. This determines the spacing D of the separation regions of the nitride film 50 to be formed in subsequent steps. Therefore, the present invention can reduce the separation interval D of the nitride film 50 to a minute size, for example, 0.02 to 0.5 μm, which is difficult to define by the current photolithography process.

Referring to FIG. 6, after removing the pattern of the photoresist film 55 of FIG. 5, the exposed portion of the sacrificial oxide film 51 using the polymer spacer 57 and the hard mask layer 53 as an etching mask. And the nitride film 50 below it are etched to expose the first oxide film 40. In this case, the nitride film 50 is spaced apart from each other at a separation interval D, for example, 0.02 to 0.5 μm, in a pattern of the first and second nitride films 50a and 50b.

Referring to FIG. 7, the patterns of the first and second nitride films 50a and 50b are sequentially etched by sequentially etching the polymer spacer 57, the hard mask layer 53, and the sacrificial oxide film 51 of FIG. 6. Expose In this case, since the exposed first oxide film 40 of the isolation region is also etched, the semiconductor substrate 10 below it is exposed.

Referring to FIG. 8, a second oxide film 60 is stacked on the exposed portions of the first and second nitride films 50a and 50b and the exposed portion of the semiconductor substrate 10 at a thickness of 50 to 150 GPa. A conductive layer, for example, a polycrystalline silicon layer 70, is laminated on the second oxide film 60 to a thickness of 1500 to 3000 GPa.

9, a pattern of the photoresist film 80 is formed on a portion of the polycrystalline silicon layer 70, for example, a portion for the gate. Then, the pattern of the polycrystalline silicon layer 70, the second oxide layer 60, and the first and second nitride layers 50a and 50b is etched using the pattern of the photoresist layer 80 as an etching mask. .

Thereafter, a structure as shown in FIG. 3 is formed by forming a second conductivity type N + type source / drain (S / D) centering the gate region using a conventional process.

Accordingly, the present invention can block the electron transfer between the first and second nitride films by separating the nitride films of the first oxide film, nitride film, and second oxide film of the word line into patterns of the first and second nitride films. As a result, malfunction of the cell of the flash memory element can be prevented.

In addition, the present invention can form a spacer on the sidewall of the hard mask layer to separate the pattern of the first and second nitride films at intervals below the limit of the current photolithography process. This can reduce the size of the cell.

Therefore, the present invention can form four cells in the same cell size of the flash memory and can improve the operation reliability of the cells.

Meanwhile, for convenience of description, the nitride film is separated based on two first and second nitride film patterns. However, the nitride film may be separated into more than two nitride film patterns.

As described in detail above, the flash memory device and the method of manufacturing the same according to the present invention can suppress electron movement in the tunnel nitride film by separating the tunnel nitride film from each other. This prevents cell malfunction of the flash memory device and further improves operation reliability.

In addition, according to the present invention, by forming a polymer spacer on the sidewall of the hard mask layer while dry etching the hard mask layer, the separation interval of the tunnel nitride layer can be made below the limit of the current photolithography process. This reduces the cell size of the flash memory device.

Meanwhile, the present invention is not limited to the contents described in the drawings and the detailed description, and various modifications may be made without departing from the spirit of the present invention, which is obvious to those skilled in the art. .

Claims (11)

Sources / drains formed spaced apart from each other in the active region of the semiconductor substrate; Patterns of a first oxide layer formed on the gate region between the source / drain and separated by a plurality of separation regions having a predetermined interval; Patterns of a nitride film formed on the patterns of the first oxide film, respectively; A pattern of a second oxide film formed together over the patterns of the nitride film and in the isolation region; And And a pattern of a conductive layer formed on the pattern of the second oxide film. The flash memory device of claim 1, wherein the nitride film has two or more patterns. The flash memory device of claim 1, wherein the patterns of the nitride film are separated at intervals of 0.02 to 0.5 μm. Forming a first oxide film on the semiconductor substrate; Stacking a nitride film on the first oxide film and separating the nitride film into patterns of a plurality of nitride films with a separation region at a predetermined interval; Stacking a second oxide film on the semiconductor substrate in the isolation region and on top of the patterns of the nitride film; Stacking a conductive layer on the second oxide film; And And forming patterns of the conductive layer, the second oxide layer, and the nitride layer as a pattern for a gate using a photolithography process. The method of claim 4, wherein the separating of the patterns of the nitride layer is performed. Stacking a nitride film on the first oxide film and sequentially stacking a sacrificial oxide film and a hard mask layer on the nitride film; Forming a pattern of a photosensitive film having a predetermined window on the hard mask layer; Forming a spacer on a sidewall of the hard mask layer while etching the hard mask layer by using the pattern of the photoresist layer as an etching mask; And And etching the sacrificial oxide film and the nitride film by using the spacer and the hard mask layer as an etch mask to separate the nitride film into patterns of the nitride film. The method of claim 4, wherein the pattern of the nitride film is separated into two or more. The method of claim 4, wherein the patterns of the nitride film are separated at intervals of 0.02 to 0.5 μm. The method of claim 5, wherein the separating of the patterns of the nitride layer is performed. Exposing the sacrificial oxide layer by etching the spacer and the hard mask layer; And And etching the sacrificial oxide film and the first oxide film of the isolation region to expose the patterns of the nitride film and the semiconductor substrate of the isolation region. The method of manufacturing a flash memory device according to claim 5, wherein the spacer is formed of a polymer spacer. The method of claim 5, wherein the hard mask layer is formed of a TEOS-based oxide film. The method of manufacturing a flash memory device according to claim 5, wherein the hard mask layer is formed of a nitride film.