KR20040059013A - FIFO buffer using dual address pointer and data input/output method in the FIFO buffer - Google Patents

Abstract

PURPOSE: A FIFO(First Input First Output) buffer having address pointers and a data I/O(Input/Output) method for the same are provided to access many data transfer paths to one FIFO at the same time by equipping the FIFO with the write/read pointers. CONSTITUTION: A RAM array(10) temporarily stores the transmitted data. A data writer(20) independently writes the data depending on a write signal for each data by equipping with the write pointers(21,23) matched with each data sort. A data reader(30) independently reads the data depending on a read signal for each data by equipping with the read pointers(31,33) matched with each data sort. A flag generator(40) generates a flag informing that an operation for writing/reading the RAM array is available, and the flag discriminating the sort of the write/read data depending on the write/read signal. A pointer adjuster(50) adjusts a pointer value of the write/read pointers depending on the flag signal.

Description

First-in-first-out buffer with a plurality of address pointers and data input / output method in the buffer {FIFO buffer using dual address pointer and data input / output method in the FIFO buffer}

The present invention relates to a first-in, first-out (FIFO) buffer, and more particularly, a plurality of address pointers open multiple data paths simultaneously, such as USB, to transfer data independently. It relates to a first-in, first-out buffer that can increase.

In general, when data is transferred between processors, there is a difference in data processing speed of each processor, and thus a standby state occurs during data transmission. To prevent such a situation and to reduce data processing speed, a buffer storage device is used. Its role is to place a FIFO buffer between processors to buffer incoming and outgoing data.

At this time, the method of processing data transmitted from the FIFO buffer is a first-in first-out method in which the first input data is output first.

In particular, in data transmission using a universal serial bus (USB), various data paths are simultaneously opened at a unit time due to the unique characteristics of the USB, and thus data is independently transmitted and received.

The speed of USB is significantly improved, and a lot of data comes and goes in a short time. Due to the nature of USB, the amount of data is constantly changing. In this regard, when several data paths are opened at the unit time and transmitted individually, the data can be stored in the FIFO according to a predetermined method.

However, the size of this FIFO will be made the maximum packet size. The maximum packet size is the maximum amount of data that can be transmitted on any one of several paths in a unit time, and is usually expressed in bytes.

However, although the maximum packet size may be fixed for one path, when several paths exist, a combination thereof is formed and used in a unit called an interface.

In this case, the most important types of transfer are bulk transfer (BULK) and isochronous transfer (ISO). In general, since ISO has a much larger amount of transmission per unit time than BULK, the FIFO is designed to be the same as the maximum packet size of ISO.In the case of input / output, two FIFOs of the same size are required. Each will be assigned to input / output.

In addition, the FIFO has pointers on the write side and the read side, respectively, and they are used in pairs to indicate from which side to which data should be transferred, whether the transfer is in progress or whether the transfer is completed, depending on the address pointed to by each. Play a role.

FIG. 1 is a view briefly illustrating a read / write method of a conventional FIFO buffer using a single pointer.

First, in the initial initialized state, the read and write pointers each point to the lowest address of the FIFO, which is usually 0.

At this time, the FIFO buffer gives an empty flag (EF) to the data writer (transmitter processor) to inform that the FIFO buffer can be written to the FIFO buffer. Next, the transmitting processor sends data to be stored together with the write signal WS (Write Strobe). In this case, depending on the system specification, how many bytes of data are written at a time varies from system to system. Therefore, for each write signal WS, data of a corresponding size (for example, m bytes) is written at the corresponding address, and the write pointer is increased by the size of the written data.

As soon as the write signal WS is applied and the write pointer increases, the empty flag EF disappears, and the transmitting processor refers to whether a full flag (FF) is generated.

You cannot write more than the maximum packet size in the write operation, and writing more data in the USB emumeration process is illegal, so no countermeasures are required. Thus, when the write pointer increases to the maximum packet size, a full flag FF is issued to indicate that writing is complete.

The generation of the full flag FF indicates that the read operation may be performed.

If the read pointer starts at address 0 and increases to the address indicated by the write pointer, it is regarded as all read, so reset each pointer to 0 and generate empty flag EF again.

However, in the conventional FIFO, there is a disadvantage in that in some cases, only part of the FIFO is used since there is no guarantee that the data paths always operate at the maximum packet size. If the input / output of the BULK and the input / output of the ISO occur at the same time, there is one FIFO used as input / output, so the input / output of the BULK is pushed to the ISO input / output and delayed data transmission to the next frame. Should.

This is a bottleneck because of the structural limitations of the hardware FIFOs implemented, regardless of the bandwidth allocation defined in USB.

In order to solve this problem, two additional FIFOs may be provided for input / output of the BULK, but in such a case, the area occupied by the FIFO becomes too large.

Accordingly, an object of the present invention is to provide a plurality of write pointers and read pointers in one FIFO so that multiple data transmission paths can simultaneously access one FIFO.

1 is an internal block diagram of a conventional FIFO buffer.

2 is a block diagram showing a configuration of a FIFO buffer having a plurality of write and read pointers according to the present invention.

3 is a diagram showing a relationship between flag generation and a write / read pointer according to the present invention;

A first-in first-out (FIFO) buffer having a plurality of address pointers of the present invention for achieving the above object includes a RAM array for temporarily storing data to be transmitted; A data recording unit having a plurality of write pointers corresponding to each data type according to the type of data, and independently performing a write operation on each data according to a write signal for each data; A data reading unit having a read pointer corresponding to the write pointer of the data recording unit, and independently performing a read operation on each data according to a read signal for each data; A flag generator configured to generate a flag indicating whether a write / read operation to a RAM array is possible and a flag to distinguish a type of data to be written / read according to the write signal and the read signal; And a pointer controller for adjusting pointer values of the plurality of write pointers and the read pointers according to the flag signal.

A data input / output method of the present invention using a first-in first-out (FIFO) buffer having a plurality of address pointers includes: a first step of writing first data to an address designated by the first write pointer; A second step of designating a second write pointer and a second read pointer to a next address of an address corresponding to a maximum packet size of the first data when a write signal for the second data is applied during a write operation on the first data; And a third step of writing second data to an address designated by the second write pointer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a configuration of a FIFO buffer having a plurality of write and read pointers according to the present invention.

The FIFO buffer of the present invention is provided with a separate read and write pointer for BULK and a read and write pointer for ISO, and is applied to a serial method in which multiple data transfer paths are simultaneously opened such as USB to independently transmit data.

The FIFO buffer of the present invention includes a RAM array 10, a data recording unit 20, a data reading unit 30, a flag generating unit 40, and a pointer adjusting unit 50.

RAM array 10 stores data transferred between processes.

The data recording unit 20 includes a plurality of write pointers corresponding to each data type according to the type of data, and independently performs a write operation on each data according to a write signal for each data.

The data recorder 20 stores a pointer value indicating a location to be stored when the ISO data is stored in the RAM array 10 and a first write pointer 21 for storing the ISO data from the USB controller (transmitter processor) not shown. When the ISO data is input together with the write signal WR_ISO, the first write controller 22 stores the ISO data input to the pointer value stored in the first write pointer 21 and increases the write pointer value by the stored data size. . The data recorder 20 stores the BULK data from a second write pointer 23 and a USB controller (transmitter processor) (not shown) that store a pointer value indicating a location to be stored when the BULK data is stored in the RAM array 10. When the BUKL data is input together with the write signal WR_BULK, the second write controller 24 stores the BULK data input to the pointer value stored in the second write pointer 23 and increases the pointer by the stored data.

The data reader 30 includes a read pointer corresponding to the write pointer of the data recorder 20 to independently read each data according to a read signal for each data.

The data reader 30 reads the ISO data from a first read pointer 31 that stores a pointer value indicating a position to read ISO data stored in the RAM array 21 and a host (receive processor) not shown. When the signal RD_ISO is inputted, the first read control unit 32 outputs ISO data where the pointer value of the first read pointer 31 designates. In addition, the data reading unit 30 may read the BULK data from a second read pointer 33 and a host (receiving processor) not shown, which store a pointer value indicating a position of reading the BULK data stored in the RAM array 10. When the read signal BULK_RD is input, the second read control unit 34 outputs the BULK data where the pointer value of the second read pointer 33 is designated.

The flag generator 40 generates a flag indicating whether the write / read operation to the RAM array 10 is possible and a flag that distinguishes the type of data to be written / read according to the data write / read signal.

The pointer controller 50 adjusts the pointer values of the plurality of write pointers and the read pointers of the data recorder 20 and the data reader 30 according to the flag signals of the flag generator 40 to adjust the pointer values of different data types. It enables independent data transfer. That is, when a write command for another type of data is applied while a write operation on one type of data is in progress, a write pointer and a read pointer to the data to be newly written at the next address of the last address at which the data started to be written first is written. Locate it.

3 is a diagram illustrating a relationship between flag generation and a write / read pointer according to the present invention.

First, when the FIFO buffer is initialized, the first and second write pointers and the first and second read pointers are located at the lowest address of the RAM address. Then, the flag generator 40 outputs empty flags FIFO_empty_flag_for_ISO and FIFO_empty_flag_for_BULK indicating that ISO data and BULK data can be written to the transmission processor.

When the empty flag FIFO_empty_flag_for_ISO is generated and the ISO data is applied from the transmitting processor together with the write signal WR_ISO for the ISO data, the first write control unit 22 writes the ISO data to the RAM array 21 in units of m bytes, and the first data. The write pointer 21 is incremented by an address corresponding to m bytes. At this time, in the USB transmission method, since the maximum amount of data (maximum packet size) that can be transmitted in one frame is determined due to the characteristics of USB, the first write pointer increases by an address corresponding to m bytes, and only increases to an address corresponding to the maximum packet size. .

In addition, the flag generator 40 outputs the ISO data write flag WR_ISO_flag to the pointer controller 50 to indicate that a write operation on the current ISO data is in progress.

When the first write pointer 21 increases to the maximum packet size, the flag generator 40 outputs the full flag signal FIFO_for_ISO_full_flag for the ISO data.

When the full flag signal FIFO_for_ISO_full_flag for the ISO data is generated, the receiving processor sends a read signal RD_ISO to the first read control unit 32 to increment the first read pointer 31 from the lowest address to an address corresponding to the maximum packet size. Read the ISO data.

By the way, if the write signal WR_BULK for the BULK data is applied to the second write control unit 24 while the ISO data is being written, the second write control unit 24 informs the flag generation unit 40 of this fact. Then, the flag generator 40 outputs the BULK data write flag WR_BULK_flag to the pointer controller 50.

When the BULK data write flag WR_BULK_flag is applied together with the ISO data write flag WR_ISO_flag, the pointer controller 50 sets the pointer values of the second write pointer 23 and the second read pointer 33 to the maximum packet size of ISO data + m. Specify the address corresponding to.

The reason why the pointer is placed at the maximum packet size of the ISO data + m is that the data size transmitted at once in the USB cannot exceed the maximum packet size, and the pointer value of the first write pointer 21 indicates the maximum packet size of the ISO data. This is because the number of m bytes is increased by the number of bytes again.

In this way, the pointer values of the second write pointer 23 and the second read pointer 33 are assigned to the next address of the last address of the ISO data recorded by the first write control unit 22 in the RAM array 21. The second write control unit 24 and the second read control unit 34 recognize the corresponding address as the lowest address. Therefore, the second write control section 24 starts writing the BULK data from the address (maximum packet size of the ISO data + m) designated by the second write pointer 23 independently of the write / read operation of the ISO data.

Even in the read operation, since the pointer value of the second read pointer 33 starts from an address corresponding to the maximum packet size of the ISO data + m, the read operation by the second read control unit 34 is performed by the first read control unit 32. Can be performed independently of the read operation.

As described above, by providing two pairs of read / write pointers in one FIFO, each data transmission can be independently performed in a manner having different data transmission paths, thereby improving transmission efficiency.

Claims (7)

RAM array for temporarily storing the data to be transmitted; A data recording unit having a plurality of write pointers corresponding to each data type according to the type of data, and independently performing a write operation on each data according to a write signal for each data; A data reading unit having a read pointer corresponding to the write pointer of the data recording unit to independently read each data according to a read signal for each data; A flag generator for generating a flag indicating whether a write / read operation to the RAM array is possible and a flag for distinguishing a type of data to be written / read according to the write signal and the read signal; And And a first-in, first-out buffer having a plurality of address pointers including a pointer controller for adjusting pointer values of the plurality of write pointers and read pointers according to the flag signal. The method of claim 1 The data recorder A first write pointer for storing a pointer value indicating a location of the RAM array in which first data is to be stored; A first write in which the first data is stored in the RAM array corresponding to the pointer value of the first write pointer according to the write signal for the first data, and the pointer value of the first write pointer is increased by the stored data. Control unit; A second write pointer for storing a pointer value indicating a location of the RAM array in which second data is to be stored; And A second write that stores the second data in the RAM array corresponding to the pointer value of the second write pointer and increases the pointer value of the second write pointer by the stored data according to the write signal for the second data. A first-in first-out buffer having a plurality of address pointers, comprising a control unit. The method of claim 1, The data reading unit A first read pointer for storing a pointer value indicating a position to read the first data stored in the RAM array; A first read controller configured to output data at a place designated by a pointer value of the first read pointer according to the read signal for the first data; A second read pointer for storing a pointer value indicating a position to read the second data stored in the RAM array; And A first-in first-out buffer having a plurality of address pointers having a second read control section for outputting data where a pointer value of the second read pointer designates in accordance with a read signal for the second data. The method of claim 1, When the write signal for the second data is applied during the write operation on the first data, the pointer adjusting unit corresponds to the maximum packet size of the first data when the pointer values of the second write pointer and the second read pointer are applied. A first-in first-out buffer having a plurality of address pointers, the address being designated as the next address. The method of claim 1, The first-in first-out buffer having a plurality of address pointers, wherein the first data is ISO data and the second data is BULK data. A data input / output method in a FIFO buffer having a first read / write pointer for first data and a second read / write pointer for second data, the method comprising: A first step of writing the first data to an address designated by the first write pointer; When the write signal is applied to the second data during the write operation on the first data, the second write pointer and the second read pointer are designated as the next address of an address corresponding to the maximum packet size of the first data. Second step; And And a third step of writing the second data to an address designated by the second write pointer. The method of claim 6, And the first data is ISO data, and the second data is BULK data.