KR20040058529A - Testing Device - Google Patents

Abstract

PURPOSE: A test apparatus is provided to check whether an operation of a corresponding unit circuit is performed well by providing an input signal to the unit circuit. CONSTITUTION: According to the test apparatus(100), a signal generation device provides a test signal to a system realized on a wafer in response to control signals. A clock generation device receives an external clock and then provides a clock signal to the signal generation unit and the system by changing a frequency of the external clock. The system includes an assembly logic circuit part performing a logic operation as to the input signal, and a plurality of unit circuits comprising a sequential logic circuit part outputting the signal being output from the assembly logic circuit part by synchronizing it to the clock signal.

Description

Testing Device

The present invention relates to an apparatus for testing the operation of the system at the wafer level, and more particularly to an apparatus for testing the operation of the system at the wafer level using a faster clock than the clock provided by the test apparatus.

1 shows the configuration of a system implemented on a wafer. The clock signal is input via XIN and the data signal is input via PIN. The system includes a plurality of unit logics including a combinational logic circuit and a flip-flop for synchronizing the output of each combinational logic circuit with a clock signal and providing the next stage. The system's processing result is finally output through POUT.

When testing while the system is implemented on a wafer, conventional test equipment can only provide a fixed speed clock, which limits the ability to test high-speed systems. In addition, it was difficult to test whether some unit circuits operate normally in a system composed of several unit circuits.

In order to solve the problems of the related art, the present invention provides a test apparatus that can change an externally provided clock to a high speed clock and provide an input signal to a predetermined unit circuit to check whether the operation of the unit circuit is performed properly. It aims to do it.

1 is a configuration diagram of a system before installing a test apparatus according to the present invention.

2 is a block diagram of a test apparatus and a system according to an embodiment of the present invention.

3 is an operation timing diagram of a test apparatus according to an embodiment of the present invention.

The test apparatus according to the present invention includes a signal generator for providing a test signal to a system implemented on a wafer in response to first to third control signals, and a clock signal for receiving an external clock and changing a frequency thereof. And a clock generator provided to the system.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a configuration diagram when a test is performed by applying the test apparatus 100 according to an embodiment of the present invention to a system.

The test apparatus 100 according to the present embodiment uses the clock signal clk that doubles the frequency of the clock input to XIN. The clock signal clk is also provided to the flip-flop FF included in each unit circuit of the system.

The test apparatus 100 according to the present invention selects one signal among a plurality of flip-flops 110, 120, 130, and 140, the output signal of the flip-flop 140, and the signal FF1 output from the previous unit circuit, The multiplexer 170, the XNOR gate 150, and the AND gate 160 are provided to the unit circuit as the input signal MIN.

The input signal TIN is input to the flip-flop 110. The XNOR gate 150 receives the outputs of the flip-flops 110 and 120 and performs an "XNOR" operation. The "XNOR" operation outputs "high" if the input signal is at the same level and outputs a "low" signal at different levels. The output signal of the XNOR gate 150 and the control signal TIWEN are input to the AND gate 160. Flip-flops 120 and 130 have an enable terminal.

The flip-flops 120 and 130 sample the input signal at the rising edge of the clock signal clk only when the enable signal is activated. The output of AND gate 160 is provided to enable terminals of flip-flops 130 and 140. The multiplexer 170 selects the output signal of the flip-flop 140 when the control signal TRUN is "high", and selects the signal FF1 output from the previous unit circuit when the control signal TRUN is "low". The operation of the test apparatus 100 according to the present embodiment will be described below.

3 is an operation timing diagram of the test apparatus according to the present invention. The timing diagram of FIG. 3 shows the process of generating a test signal that transitions from "high" to "low".

The flip-flop 110 samples TIN at the rising edge of the clock signal clk and outputs R0. The flip-flop 120 samples R0 at the rising edge of the clock signal clk and outputs R1. In FIG. 3, the output signals R0 and R1 are represented to transition after a predetermined time after the clock rises in consideration of delays in the flip-flops 110 and 120.

The output of the XNOR gate 150 is " high " if R0 and R1 are at the same level, " low " Therefore, the control signal EN becomes "high" only when the control signal TIWEN is "high" and both R0 and R1 are at the same level. Flip-flop 130 samples R1 at the rising edge of clock signal clk when control signal EN is "high", and flip-flop 140 at the rising edge of clock signal clk when control signal EN is "high". Sample R2 at. In FIG. 3, the output signals R2 and R3 are represented to transition after a predetermined time has passed since the clock has risen in consideration of the delay of the flip-flops 130 and 140.

The signal FF1 provided by the first unit circuit is kept low, and when the control signal TRUN is transitioned from "high" to "low" after a predetermined time has elapsed since R3 rises, the second unit circuit is provided. The signal MIN transitions from "high" to "low".

If the combined logic circuit in the second unit circuit operates at a high enough speed, the correct signal will be output at the rising edge of the next clock, otherwise the previous output value will be maintained even after the next clock.

A similar method as shown in FIG. 3 may be used to cause the signal MIN to transition from "low" to "high".

By using the test apparatus according to the present invention, it is possible to verify whether a predetermined unit circuit operates correctly and how fast the unit circuit can operate.

Claims (4)

A signal generator providing a test signal to a system implemented in a wafer in response to the first to third control signals; And A clock generator that receives an external clock and provides a clock signal with a changed frequency to the signal generator and the system. Test apparatus comprising a. The method of claim 1, The system A combinational logic circuit unit for performing a logic operation on the input signal; And And a plurality of unit circuits each having a sequential logic circuit section for outputting the signal output from said combinational logic circuit section in synchronization with a clock signal. The method of claim 1, Signal generator A first flip-flop that samples the second control signal in synchronization with the clock signal; A second flip-flop sampling the output signal of the first flip-flop in synchronization with the clock signal; A controller configured to receive an output signal of the first flip-flop, an output signal of the second flip-flop, and the third control signal and output an internal control signal; A third flip-flop activated by the internal control signal and sampling an output signal of the second flip-flop in synchronization with the clock signal; A fourth flip-flop activated by the internal control signal and sampling an output signal of the third flip-flop in synchronization with the clock signal; And A selection circuit for selecting and outputting one of the signal of the fourth flip-flop and an external signal in response to a first control signal Including And the output of the selection circuit is used as the predetermined test signal. The method of claim 3, The control unit An XNOR gate configured to perform an XNOR operation on the output signal of the first flip-flop and the output signal of the second flip-flop; And an AND gate for ANDing the output signal of the XNOR gate and the third control signal, And providing the output of the AND gate as the internal control signal.