KR20040058444A - Dual Panel Type Electroluminescent Device and Method for Fabricating the same - Google Patents

Abstract

PURPOSE: A dual panel type organic electro-luminescence device and a fabricating method thereof are provided to improve the productivity and the efficiency of the production management by forming an array element and an electro-luminescence diode on different substrates, respectively. CONSTITUTION: A gate line(212) is formed to a first direction on a first substrate. A data line(236) is formed to a second direction across the first direction. A power supply line(242) is formed to the second direction apart from the data line. A switching TFT(Ts) is formed at an intersection between the gate line and the data line. The switching TFT includes a semiconductor layer, which is formed with amorphous silicon. A driving TFT(TD) is formed at an intersection between the switching TFT and the power supply line. The driving TFT includes the same semiconductor layer as the switching TFT. A connecting electrode(276) is connected to the driving TFT. A column-shaped electric connection pattern is formed within a region of the connecting electrode in order to connect an organic electro-luminescence diode to the connecting electrode.

Description

Dual panel type electroluminescent device and method of manufacturing the same {Dual Panel Type Electroluminescent Device and Method for Fabricating the same}

The present invention relates to an organic electroluminescent device, and more particularly, to a dual panel type organic electroluminescent device having an amorphous silicon thin film transistor structure and an manufacturing method thereof. One of the new flat panel displays, the organic light emitting display device is self-luminous, and thus has a better viewing angle and contrast ratio than a liquid crystal display device. In addition, since it is possible to drive DC low voltage, fast response speed, and all solid, it is strong against external shock, wide use temperature range, and especially inexpensive in manufacturing cost.

In particular, since the organic light emitting device has a very simple process unlike a liquid crystal display device or a plasma display panel (PDP), deposition and encapsulation equipment are all.

In particular, in the active matrix system, the voltage applied to the pixel is charged in the storage capacitance (C _ST ), and the power is applied until the next frame signal is applied, thereby relating to the number of gate wirings. Run continuously for one screen without

Therefore, in the active matrix system, since the same luminance is displayed even when a low current is applied, low power consumption, high definition, and large size can be obtained.

Hereinafter, the basic structure and operation characteristics of the active matrix organic electroluminescent device will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a basic pixel structure of a general active matrix organic light emitting display device.

As shown, a scan line is formed in the first direction, is formed in a second direction crossing the first direction, and a signal line and a power supply line spaced apart from each other by a predetermined distance are provided. Formed to define one pixel area.

The scanning line and the intersection of the signal line has the addressing element (addressing element) the switching thin film transistor; is formed at the (T _S Switching TFT), is connected to the switching thin film transistor (T _S) for the storage capacitance (C _ST) is And a driving thin film transistor T _D , which is a current source element, is connected to a connection portion and a power supply line of the switching thin film transistor T _S and the storage capacitance C _ST . A positive electrode (+) is connected to the driving thin film transistor (T _D ), and the positive electrode (+) is a cathode (-) through an electroluminescent diode (E) of a constant current driving method. Connected with

An anode (+) and a cathode (-) connected by the organic light emitting diode device (E) constitute an organic light emitting device.

The switching thin film transistor T _S controls a voltage, and the storage capacitance C _ST serves to store a current source.

Hereinafter, the driving principle of the active matrix organic light emitting display device will be described.

In the active matrix method, when a signal is applied to a corresponding electrode according to a selection signal, the gate of the switching thin film transistor is turned on, and the data signal passes through the gate of the switching thin film transistor, whereby the driving thin film transistor and the storage capacitance are applied. When the gate of the driving thin film transistor is turned on, current is supplied from the power supply line to the organic light emitting layer through the gate of the driving thin film transistor to emit light.

At this time, the degree of opening and closing of the gate of the driving thin film transistor is changed according to the magnitude of the data signal, so that gray scale display can be performed by adjusting the amount of current flowing through the driving thin film transistor.

In the non-selection period, data charged in the storage capacitance is continuously applied to the driving thin film transistor, so that the organic light emitting diode can be continuously emitted until a signal of the next screen is applied.

FIG. 2 is a plan view of one pixel portion of a conventional active matrix type organic light emitting display device, and will be described with an example of a two TFT structure having one switching thin film transistor and one driving thin film transistor.

As shown in the drawing, the gate wiring 37 is formed in the first direction, the data wiring 51 and the power supply wiring 41 are formed to intersect the gate wiring 37 and are spaced apart from each other. An area where the 37, the data line 51, and the power supply line 41 intersect with each other defines the pixel area P.

The switching thin film transistor T _S is positioned in an area where the gate wiring 37 and the data wiring 51 cross each other, and the driving thin film transistor T _S and the power supply wiring 41 are crossed at a point where the switching thin film transistor T _S and the power supply wiring 41 cross each other. The thin film transistor T _D is positioned, and the storage capacitance C _ST overlaps the power supply wiring 41 and the capacitor electrode 134 forming an integrated pattern with the semiconductor layer 31 of the switching thin film transistor T _S. Is formed.

The first electrode 58 is formed in connection with the driving thin film transistor T _D , and although not shown in the drawing, the organic light emitting layer and the second electrode are sequentially formed in the region covering the first electrode 58. Is formed.

The first electrode forming part is defined as an organic light emitting part (I).

Reference numeral 32 denotes a semiconductor layer for driving thin film transistor T _D , and 35 and 38 are gate electrodes of the switching thin film transistor T _S and the driving thin film transistor T _D, respectively. Corresponds to

Hereinafter, the stacked structure of the organic light emitting unit, the driving thin film transistor, and the storage capacitance will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a cross section taken along the cutting line ii-ii of FIG. 2.

As illustrated, a driving thin film transistor T _D including the semiconductor layer 32, the gate electrode 38, the source and drain electrodes 50 and 52 is formed on the insulating substrate 1. The power electrode 42 branched from the power supply wiring (not shown) is connected to the source electrode 50, and the first electrode 58 made of a transparent conductive material is connected to the drain electrode 52.

A capacitor electrode 34 made of the same material as that of the semiconductor layer 32 is formed in a lower portion corresponding to the power electrode 42, so that the power electrode 42 and the capacitor electrode 34 overlap each other. The region forms the storage capacitance C _ST .

In addition, an organic light emitting layer 64 and a cathode 66 made of an opaque metal material are sequentially stacked on the first electrode 58 to form the organic light emitting unit I.

Looking at the stacked structure of the insulating layers positioned in the organic light emitting unit (I), the buffer layer 30 to the buffer between the insulating substrate 1 and the semiconductor layer 32 and the storage capacitance (C _ST ) The first protective layer 40 used as the insulator for the insulation, the second protective layer 44 between the drain electrode 52 and the power electrode 42, the first electrode 58 and the source electrode 50. The third protective layer 54 therebetween and the fourth protective layer 60 between the thin film transistor T and the first electrode 58 are sequentially stacked, and the first to fourth protective layers 40, 44, 54, and 60 each include a contact hole (not shown) for electrical connection between each layer.

Hereinafter, FIGS. 4A to 4I are cross-sectional views illustrating cross-sectional views cut along the cutting line ii-ii of FIG. 2 according to manufacturing steps, respectively. The exposure and development using photo-resist (PR) as a photosensitive material, respectively. It proceeds by the process of patterning by the photolithography process including the process), and this series of patterning processes are defined as a mask process, and it demonstrates in order of a process.

In FIG. 4A, a buffer layer 30 is formed on the insulating substrate 1 using the first insulating material over the entire surface of the substrate, and the polysilicon is used on the buffer layer 30 to be active by the first mask process. Layer 32a and capacitor electrode 34 are formed.

Next, in FIG. 4B, a second insulating material and a first metal are successively deposited on the substrate having passed through the step of FIG. 4A, and then gate insulating films are respectively formed at the center of the active layer 32a by a second mask process. 36 and the gate electrode 38.

In FIG. 4C, a first protective layer 40 made of a third insulating material is formed on the substrate having passed through FIG. 4B, and a second metal is deposited on the first protective layer 40. The power electrode 42 is formed in the position which covers the said capacitor electrode 34 by a three mask process.

In FIG. 4D, after depositing a third insulating material on the substrate having passed through FIG. 4C, the fourth mask process exposes both ends of the active layer 32a and a part of the power electrode 42. The second protective layer 44 having the first and second ohmic contact holes 46a and 46b and the capacitor contact hole 48 is formed.

Both ends of the active layer 32a form a drain region iiia and a right portion constitute a source region iiib so as to be connected to source and drain electrodes to be formed in a later process.

In this step, the exposed both ends of the active layer 32a are ion-doped to form the ion-doped portion as an ohmic contact layer 32b containing impurities to form the active layer 32a. And a semiconductor layer 32 composed of an ohmic contact layer 32b.

Next, in step 4E, after depositing the third metal, the power electrode 42 is formed through the capacitor contact hole 48 of FIG. 4D and the first ohmic contact hole 46A of FIG. 4D by a fifth mask process. ) And a source electrode 50 connected to the ohmic contact layer 32b of the source region iiib, spaced apart from the source electrode 50 by a predetermined interval, and drained through the second ohmic contact hole 46b of FIG. 4D. A drain electrode 52 connected to the ohmic contact layer 32b in the region iiia is formed.

In this step, the driving thin film transistor T _D including the semiconductor layer 32, the gate electrode 38, the source and drain electrodes 50 and 52 is completed.

Meanwhile, the power electrode 42 and the capacitor electrode 34 are electrically connected to the source electrode 52 and the semiconductor layer of the switching thin film transistor, respectively, using the first protective layer 40 as an insulator. The storage capacitance C _ST is formed.

In FIG. 4F, after depositing the fourth insulating material on the substrate having passed through FIG. 4E, the third protective layer 54 having the drain contact hole 56 is formed by the sixth mask process.

Next, in step 4G, an organic field, which is an organic light emitting layer region, is formed by a seventh mask process using a fourth metal so as to be connected to the drain electrode 50 through the drain contact hole 56 in FIG. 4F. The first electrode 58 is formed in the light emitting part I.

In FIG. 4H, after depositing a fifth insulating material on the substrate having undergone the 4g step, the first electrode exposing the first electrode 58 corresponding to the organic light emitting unit I by an eighth mask process is exposed. The fourth protective layer 60 having the exposed portion 62 is formed.

The fourth protective layer 60 serves to protect the driving thin film transistor T _D from moisture and foreign matter.

As a result, the manufacturing process accompanied by the mask process is finished, and then, in step 4i, the organic light emitting layer 64 connected to the first electrode 58 through the first electrode exposed portion 62 of FIG. 4h, and The second electrode 66 is formed over the entire surface of the organic electroluminescent layer 64 by using a fifth metal.

For example, when the first electrode 58 is used as an anode, the material forming the fifth metal may reflect light emitted from the organic electroluminescent layer 64 to the first electrode 58 to emit the organic electroluminescent device. In order to realize the screen, the metal material having the reflective characteristic and the low work function value is selected so that the electron can be easily presented.

Hereinafter, a laminated structure of a conventional organic light emitting diode panel will be described in detail with reference to the accompanying drawings.

FIG. 5 is a cross-sectional view of a conventional organic light emitting display device and illustrates an encapsulation structure centering on an organic light emitting display unit and a driving thin film transistor connection unit.

As shown in the drawing, the first and second substrates 70 and 90 are disposed to be spaced apart from each other by a subpixel unit, which is the minimum unit for implementing a screen, and the sub-pixel unit is disposed on an inner surface of the first substrate 70. a first electrode connected to the formed plurality of driving thin film transistor (T _D) array element layer 80 including for, and is formed, the array element layer 80, an upper portion the driving thin film transistor (T _D) for a sub-pixel unit An organic electroluminescent layer 74 is formed on the first electrode 72 to emit red, green, and blue colors in subpixel units, and is formed on the entire upper surface of the organic electroluminescent layer 74. Two electrodes 76 are formed.

The organic light emitting layer 74 interposed between the first and second electrodes 72 and 76 and the first and second electrodes 72 and 76 forms an organic light emitting diode device E, and the organic light emitting layer 74 The light emitted from the light emitting device is characterized in that the bottom emission method is emitted toward the first electrode (72).

The second substrate 90 is used as an encapsulation substrate, and a recess 92 is formed at an inner central portion of the second substrate 90, and moisture from the outside is formed in the recess 92. A moisture absorbent 94 is sealed to block absorption to protect the organic light emitting diode device E.

The inner surface of the second substrate 90 in which the moisture absorbent 94 is sealed and the second electrode 76 are positioned to be spaced apart from each other by a predetermined distance.

The edges of the first and second substrates 70 and 90 are encapsulated by the seal pattern 85.

As described above, the conventional bottom emission type organic light emitting diode device is manufactured by bonding an array device and a substrate on which an organic light emitting diode is formed and a separate substrate for encapsulation. In this case, since the product of the yield of the array device and the yield of the organic light emitting diode determines the yield of the organic light emitting diode, the overall organic process of the organic light emitting diode structure yields the overall process yield by the organic electroluminescent diode process. There was a problem that is greatly limited. For example, even if the array element is well formed, if the defect is caused by foreign matter or other elements in forming the organic light emitting layer using the thin film of about 1,000 mW, the organic light emitting element is judged as a poor grade. .

This results in a loss of overall costs and material costs that were required to manufacture the array device of good quality, there was a problem that the production yield is lowered.

In addition, the bottom emission method has a high degree of freedom and stability due to the encapsulation process, and has a problem in that it is difficult to be applied to a high resolution product due to the limitation of the aperture ratio. The top emission method is easy to design a thin film transistor and improves the aperture ratio It is advantageous in terms of product life, but in the conventional top emission type structure, since the material selection range is narrow as the cathode is normally positioned on the organic light emitting layer, the transmittance is limited and the light efficiency is reduced, and the light transmittance is minimized. In order to configure a thin film type protective film, there was a problem in that it does not sufficiently block outside air.

In order to solve the above problems, the present invention is to provide a high-resolution / high-opening structure active matrix organic electroluminescent device with improved production yield.

To this end, in the present invention, the array element and the organic light emitting diode element are formed on different substrates, and the thin film transistor for driving the array element and the second electrode of the organic light emitting diode element are connected through separate electrical connection patterns. An object of the present invention is to provide a dual panel type organic light emitting display device.

Another object of the present invention is to provide a process for manufacturing a substrate for a dual panel type organic electroluminescent device including an inverted staggered thin film transistor using an amorphous silicon material.

When the process is performed by including the reverse staggered thin film transistor, the process may be performed under low temperature conditions, and even if the process is performed including an electrical connection pattern, the number of masks does not increase.

1 is a view showing a basic pixel structure of a general active matrix organic electroluminescent device.

2 is a plan view of one pixel portion of a conventional active matrix organic electroluminescent device.

3 is a cross-sectional view taken along the cut line ii-ii of FIG. 2.

4A to 4I are cross-sectional views each showing a cross section cut along the cutting line ii-ii of FIG.

5 is a cross-sectional view of a conventional organic light emitting display device.

6 is a cross-sectional view of a dual panel organic electroluminescent device according to a first embodiment of the present invention.

7 is a plan view of a dual panel type organic light emitting display device according to a second exemplary embodiment of the present invention.

8a to 8h, 9a to 9h, 10a to 10h, and 11a to 11h each make a cross section cut along the cutting lines IIa-IIa, IIb-IIb, IIc-IIc, and IId-IId of FIG. Fig. 2 is a cross-sectional view showing step by step, wherein IIa-IIa is a driving thin film transistor portion, IIb-IIb is a data pad portion, IIc-IIc is a gate pad portion, and IId-IId is a power supply pad portion.

<Explanation of symbols for main parts of drawing>

210: substrate 216: gate electrode

220: gate insulating film 224a, 224b: active layer, ohmic contact layer

224 semiconductor layer 228 source electrode

232: drain electrode 246: source contact hole

256: interlayer insulating film 244: power electrode

264 drain drain hole 272 protective layer

274: electrical connection pattern 276: connection electrode

ch: Channel T _D : Driving Thin Film Transistor

In order to achieve the above object, in the first aspect of the present invention, the first substrate (array substrate) and the second substrate (organic electroluminescent diode substrate) disposed to be spaced apart from each other, and are located between the first and second substrates, A dual panel type organic electroluminescent device comprising a pattern portion for electrically connecting the first and second substrates, comprising: a gate wiring formed in a first direction on the first substrate; A data line formed in a second direction crossing the first direction; A power supply wiring formed in the second direction and positioned to be spaced apart from the data wiring; A switching thin film transistor formed at an intersection point of the gate line and the data line and having a semiconductor layer made of amorphous silicon (a-Si); A driving thin film transistor formed at an intersection point between the switching thin film transistor and the power supply wiring and having a semiconductor layer made of the same material as the switching thin film transistor; A connection electrode formed to be connected to the driving thin film transistor; The present invention provides an array substrate for a dual panel type organic electroluminescent device, which is positioned in the connection electrode region and includes a columnar electrical connection pattern connecting the organic light emitting diode device to the connection electrode.

A gate pad, a data pad, and a power supply pad are formed at one end of the gate wiring, the data wiring, and the power supply wiring, respectively, and an area covering the gate pad, the data pad, and the power supply pad is the same as the power supply wiring. In the process, the gate pad electrode, the data pad electrode, and the power supply pad electrode each made of the same material are positioned, and in the region covering the gate pad electrode, the data pad electrode, and the power supply pad electrode, the same material is used in the same process as the connection electrode. Another gate pad electrode, a data pad electrode, a power supply pad electrode made of a further characterized in that it is formed.

The switching thin film transistor has a structure in which a gate electrode branched from the gate wiring, an active layer made of an amorphous silicon material, and an ohmic contact layer made of an impurity silicon material are sequentially stacked in the region covering the gate electrode. A semiconductor layer, a source electrode and a drain electrode spaced apart from each other on the semiconductor layer, wherein the driving thin film transistor includes a driving gate electrode connected to the drain electrode and a position covering the driving gate electrode; And a driving source electrode and a drain electrode spaced apart from each other above the driving semiconductor layer, wherein the driving source electrode is connected to a power electrode branched from the power supply wiring. It features.

According to a second aspect of the present invention, an array substrate for an organic light emitting diode device having a dual panel type structure in which an array device and an organic light emitting diode device are configured on different substrates, and the two devices are electrically connected through separate electrical connection patterns. In the manufacturing method of the method, the gate electrode, the gate by a first mask process is a series of processes to form a first metal material on the substrate, and then patterned by a photolithography process using a photo-resist (PR) as a photosensitive material Forming a pad; A first insulating material, an amorphous silicon material, and an impurity silicon material are continuously formed at a position covering the gate electrode and the gate pad, and then the first insulating material is used as a gate insulating film, and the gate electrode is covered by a second mask process. Forming a semiconductor layer at a position, and using a third mask process using a second metal material at a position covering the semiconductor layer, the source electrode and the drain electrode positioned to be spaced apart from each other on the semiconductor layer, and the data pad. And using the source electrode and the drain electrode as a mask to remove the impurity silicon material in the separation interval between the source electrode and the drain electrode, and form an amorphous silicon material region constituting the lower layer as a channel, and An amorphous silicon material is used as an active layer, and the impurity silicon material is an ohmic contact layer. Constructing; The gate electrode, the semiconductor layer, the source electrode, and the drain electrode form a thin film transistor, and the source electrode, the gate pad, the data pad, and the power supply pad are formed by a fourth mask process using a second insulating material at a position covering the thin film transistor. Forming an interlayer insulating film having a source contact hole, a gate pad contact hole, a data pad contact hole, and a power supply pad contact hole, each of which exposes a portion thereof; By a fifth mask process using a third metal material on the interlayer insulating layer, a power electrode connected to the source electrode through the source contact hole and through the gate pad contact hole, data pad contact hole, and power supply pad contact hole. Forming a gate pad electrode, a data pad electrode, and a power supply pad electrode respectively connected to the gate pad, the data pad, and the power supply pad; A drain contact hole and a gate pad electrode partially exposing the drain electrode by a sixth mask process using a third insulating material at a position covering the power electrode, the gate pad electrode, the data pad electrode, and the power supply pad electrode; Forming a protective layer having first to third open portions partially exposing the pad electrode and the power supply pad electrode; Forming a pillar-shaped electrical connection pattern on an electrical connection portion defined as an area connected to the organic light emitting diode device by a seventh mask process using a fourth insulating material on the protective layer; Forming a connection electrode connected to a drain electrode through the drain contact hole and positioned in an area covering the electrical connection pattern by an eighth mask process using a fifth metal material in the region covering the electrical connection pattern; It provides a method for manufacturing an array substrate for a dual panel type organic electroluminescent device.

In the forming of the connection electrode, another gate pad electrode connected to a gate pad electrode, a data pad electrode, and a power supply pad electrode through the first to third contact holes using the same material as the connection electrode. And forming a data pad electrode and a power supply pad electrode, respectively, wherein the thin film transistor corresponds to a driving thin film transistor connected to an organic light emitting diode device, and the gate pad contact hole and the power supply pad contact. The hole is a contact hole that the gate insulating film and the interlayer insulating film have in common, and the first mask process includes forming a gate wiring connected to the gate electrode, and in the fourth mask process, the hole intersects with the gate wiring. Forming a data line in a direction to be directed to the fifth mask process; Stand, it characterized in that it comprises a step of forming a power supply line which is located and connected to the power electrodes, spaced apart in the same direction as the data line.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment

FIG. 6 is a cross-sectional view of a dual panel type organic light emitting display device according to a first embodiment of the present invention, and is schematically illustrated around an electrical connection structure.

As shown in the drawing, the first and second substrates 110 and 150 are disposed to face each other at a predetermined interval in subpixel units, which are the minimum units for implementing the screen.

An array element layer 140 including a plurality of driving thin film transistors T _D formed in subpixel units is formed on the inner surfaces of the first substrates 110 and 150, and a drive is formed on the array element layer 140. The electrical connection pattern 142 is formed by being connected to the thin film transistor T _D.

The electrical connection pattern 142 is selected from a conductive material, and the electrical connection pattern 142 may be formed of a multilayer including an insulating material in order to be formed in a sense of thickness, and may be driven through a separate connection electrode. T _D ) may be connected.

The driving thin film transistor T _D may include a gate electrode 112, a semiconductor layer 114, a source electrode 116, and a drain electrode 118, and the aforementioned electrical connection pattern 142 may be substantially drained. It is connected to the electrode 118.

The first electrode 152 is formed on the entire inner surface of the second substrate 150, and the red, green, and blue light emitting layers 156a, 156b, and 156c are repeatedly arranged in subpixel units below the first electrode 152. ) Is formed, and the second electrode 162 is formed in the subpixel unit below the organic light emitting layer 160.

In more detail, the organic light emitting layer 160 may include a first carrier transfer layer 154 in contact with the bottom surface of the first electrode 152, and a lower portion of the red, green, and blue light emitting layers 156a, 156b, and 156c. And a second carrier transfer layer 158 in contact with the top surface of the second electrode 162.

For example, when the first electrode 152 corresponds to an anode and the second electrode 162 corresponds to a cathode, the first carrier transport layer 154 sequentially corresponds to a hole injection layer and a hole transport layer, and a second carrier The transport layer 158 corresponds to an electron transport layer and an electron injection layer in order.

The organic light emitting layer 160 interposed between the first and second electrodes 152 and 162 and the first and second electrodes 152 and 162 corresponds to the organic light emitting diode device E.

In the present invention, the top surface of the electrical connection pattern 142 is connected to the lower surface of the second electrode 162, the current supplied from the driving thin film transistor (T _D ) is the second electrode through the electrical connection pattern 142. Characterized in that it is delivered to (162).

The seal patterns 170 are positioned at edges of the first and second substrates 110 and 150 to bond the first and second substrates 110 and 150 to each other.

In the present embodiment, the organic light emitting diode device E and the array device layer 140 are formed on different substrates, but are configured in a dual panel type in which two devices are connected using an electrical connection pattern 142. It is characterized by.

For convenience of description, a two-pixel structure in which three subpixels constitute one pixel is illustrated as an example, and a thin film transistor structure and a connection method of an electrical connection pattern may be variously changed.

In addition, since the dual panel type organic light emitting display device according to the present invention has an upper light emitting method as shown in the light emitting direction on the drawing, the thin film transistor design is easy and high opening ratio / high resolution can be realized.

Second Embodiment

7 is a plan view of a dual panel type organic light emitting display device according to a second exemplary embodiment of the present invention.

As illustrated, the gate wiring 212 is formed in the first direction, and the data wiring 236 and the power supply wiring 242 are formed to be spaced apart from each other in the second direction crossing the first direction. A switching thin film transistor T _S is formed at a point where the gate wiring 212 and the data wiring 236 intersect. The switching thin film transistor T _S is disposed to be spaced apart from the gate electrode 214 branched from the gate line 212, the source electrode 226 branched from the data line 236, and the source electrode 226. The semiconductor layer 222 is formed in a region covering the drain electrode 230, the gate electrode 214, the source electrode 226, and the drain electrode 230.

The driving thin film transistor T _S and the power supply wiring 242 are connected to the driving thin film transistor T _D. The driving thin film transistor T _D includes a driving gate electrode 216 made of the same material in the same process as the gate wiring 212 and connected to the drain electrode 230, and the driving gate electrode ( The driving source electrode 228 and the drain electrode 232 and the driving gate electrode 216 formed of the same material in the same process as the data line 236 and positioned to be spaced apart from each other by overlapping with both sides of the 216. ), The driving semiconductor layer 224 is positioned in an area covering the driving source electrode 228 and the drain electrode 232.

A power electrode 244 connected to the driving source electrode 228 is branched to the power supply wiring 242, and is connected to the driving drain electrode 232 and connected to an electrical connection portion IV region. 276 is formed.

The electrical connection part IV corresponds to a region range corresponding to the second electrode of the organic light emitting diode substrate (not shown).

Although not shown in the drawings, the electrical connection part IV includes a columnar electrical connection pattern, and the electrical connection pattern will be described in more detail through a cross-sectional stacked structure.

In addition, the drain electrode 230 includes a capacitor electrode 234 extending to overlap the power supply wiring 242, so that the region where the capacitor electrode 234 and the power supply wiring 242 overlap each other is a storage capacitance. (C _ST ).

A gate pad 218, a data pad 238, and a power supply pad 240 are positioned at one end of each of the gate wire 212, the data wire 236, and the power supply wire 242. In this case, the power supply pad 240 is made of the same material in the same process as the data line 236, and is spaced apart from each other in the same direction as the capacitor electrode 234.

The gate pad electrode 258 and the data pad electrode 260 formed of the same material in the same process as the power supply wiring 242 are disposed at the positions covering the gate pad 218, the data pad 238, and the power supply pad 240. And a power supply pad electrode 262 are formed, respectively.

The power supply wiring 242 and the power supply pad electrode 262 correspond to an integrated pattern.

In this case, since the data pad 238 and the power supply pad 240 are applied with different signal voltages, the data pad 238 and the power supply pad 240 may be formed at different ends as shown in the drawing.

Third Embodiment

8A to 8H, 9A to 9H, 10A to 10H, and 11A to 11H each make cross sections cut along the cutting lines IIa-IIa, IIb-IIb, IIc-IIc, and IId-IId of FIG. A cross-sectional view showing step by step, IIa-IIa is a driving thin film transistor unit, IIb-IIb is a data pad unit, IIc-IIc is a gate pad unit, IId-IId is a power supply pad unit. The gate electrode, the driving semiconductor layer, the driving source electrode, and the drain electrode will be briefly described as a gate electrode, a semiconductor layer, a source electrode, and a drain electrode.

8A, 9A, 10A, and 11A are steps of forming the gate electrode 216 and the gate pad 218 on the substrate 210 by a first mask process using a first metal material.

The first metal material is selected from a metal material having a low specific resistance value, and is preferably selected from a metal material including aluminum.

Although not shown in detail in the drawings, the mask process used in the present invention is applied by applying a photosensitive material PR, then placing a mask having a desired pattern, and then exposed using a PR pattern formed through exposure and development as a mask. Corresponds to the method of patterning by etching the layer to be etched.

8B, 9B, 10B, and 11B show a first insulating material, an amorphous silicon material (a-Si), and an impurity silicon material (n + a-Si) in a region covering the gate electrode 216 and the gate pad 218. Next, the first insulating material is formed as the gate insulating film 220, and the amorphous silicon material (a-Si) and the impurity silicon material (n + a-Si) are formed by the second mask process. The patterned semiconductor layer 224 is formed in a region covering the 216.

The semiconductor layer 224 includes an active layer 224a made of amorphous silicon material (a-Si) and an ohmic contact layer 224b made of impurity silicon material (n + a-Si).

The first insulating material is preferably selected from a silicon insulating material, and more preferably, a silicon nitride film (SiNx).

8C, 9C, 10C, and 11C illustrate source electrodes positioned on the semiconductor layer 224 and spaced apart from each other by forming a second metal material in a region covering the semiconductor layer 224. 228 and the drain electrode 232, the data pad 238 positioned in the data pad forming unit IIIa, and the power supply pad 240 positioned in the power supply pad forming unit IIIb.

Although not shown in the drawings, this step includes forming a data wiring in a second direction, wherein the data pad forming portion IIIa and the power supply pad forming portion IIIb are formed of one of the data wiring and the power supply wiring, respectively. Corresponding to the end region, preferably located at one end in the opposite direction to each other.

The second metal material is selected from a metal material having strong chemical corrosion resistance, and preferably selected from molybdenum (Mo), titanium (Ti), chromium (Cr), and tungsten (W).

In this step, the step of removing the ohmic contact layer 224b in the section between the source electrode 228 and the drain electrode 232, exposing the active layer 224a forming the lower layer, the exposed active layer Region 224a forms a channel ch.

The gate electrode 216, the semiconductor layer 224, the source electrode 228, and the drain electrode 232 form a driving thin film transistor T _D.

8D, 9D, 10D, and 11D, a second insulating material is formed in a region covering the driving thin film transistor T _D , the data pad 238, and the power supply pad 240, and then a fourth mask process. The source contact hole 246, the gate pad contact hole 248, and the data pad which partially expose the source electrode 228, the gate pad 218, the data pad 238, and the power supply pad 240, respectively. An interlayer insulating layer 256 having a contact hole 250 and a power supply pad contact hole 252 is formed.

In this case, the gate pad contact hole 248 corresponds to a contact hole that the gate insulating film 220 and the interlayer insulating film 256 in a region covering the gate pad 218 have in common.

The second insulating material is selected from an organic insulating material or an inorganic insulating material, and may be composed of a single layer or a plurality of layers, but the insulating material contacting the thin film transistor is preferably selected from the inorganic insulating material.

8E, 9E, 10E, and 11E illustrate a power connected to the source electrode 228 through the source contact hole 246 by a fifth mask process using a third metal material on the interlayer insulating layer 256. A gate pad electrode 258 connected to the gate pad 218 through the electrode 244, a gate pad contact hole 248, and a data pad electrode connected to the data pad 238 through the data pad contact hole 250. 260 and forming a power supply pad electrode 262 connected to the power supply pad 240 through the power supply pad contact hole 252.

Although not shown in the drawing, the step of forming the power electrode 244 includes a step of forming a power supply wiring connected to the power electrode 244, and the power supply wiring is integrated with the power supply pad electrode 262. Corresponds to the pattern.

8F, 9F, 10F, and 11F use a third insulating material in an area covering the power electrode 244, the gate pad electrode 258, the data pad electrode 260, and the power supply pad electrode 262. The drain contact hole 264 partially exposing the drain electrode 232, the gate pad electrode 258, the data pad electrode 260, and the power supply pad electrode 262 by the sixth mask process, and the first to third parts. A protective layer 272 having contact holes 266, 268, and 270 is formed.

8G, 9G, 10G, and 11G are column-shaped electrical connection patterns 274 formed in the electrical connection portion IV by a seventh mask process using a fourth insulating material in an area covering the protective layer 272. Forming a step.

The electrical connection part IV is preferably located in a region corresponding to the second electrode of the organic light emitting diode device (not shown).

The fourth insulating material is preferably selected from organic insulating materials that are easy to form with a sense of thickness.

8H, 9H, 10H, and 11H illustrate a drain electrode 232 through the drain contact hole 264 by an eighth mask process using a fourth metal material in an area covering the electrical connection pattern 274. Connected to each other to form a connection electrode 276 positioned in an area covering the electrical connection pattern 274.

Although not shown in the drawing, in this step, a gate pad electrode (258 in FIG. 9G), a data pad electrode (260 in FIG. 10G), and a power supply pad electrode (262 in FIG. 11G) are formed using the fourth metal material. And another pad electrode connected to each other.

However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

As described above, according to the dual panel type organic light emitting diode and a method of manufacturing the same according to the present invention, first, since the array element and the organic light emitting diode element are formed on different substrates, production yield and production management efficiency can be improved. Second, the product lifespan can be increased, and secondly, the upper light emitting method makes it easier to design thin film transistors and realizes high opening ratio / high resolution. Third, by adopting an inverse staggered thin film transistor structure using amorphous silicon material, This is possible, and even if a separate electrical connection pattern is added, the process can be performed without adding a mask process.

Claims (11)

A first substrate (array substrate) and a second substrate (organic electroluminescent diode substrate) disposed to be spaced apart from each other, and a pattern portion disposed between the first and second substrates to electrically connect the first and second substrates. In the dual panel type organic light emitting device, Gate wiring formed on the first substrate in a first direction; A data line formed in a second direction crossing the first direction; A power supply wiring formed in the second direction and positioned to be spaced apart from the data wiring; A switching thin film transistor formed at an intersection point of the gate line and the data line and having a semiconductor layer made of amorphous silicon (a-Si); A driving thin film transistor formed at an intersection point between the switching thin film transistor and the power supply wiring and having a semiconductor layer made of the same material as the switching thin film transistor; A connection electrode formed to be connected to the driving thin film transistor; Located in the connection electrode region, a columnar electrical connection pattern connecting the organic light emitting diode device and the connection electrode. Array panel for a dual panel type organic light emitting device comprising a. The method of claim 1, And a gate pad, a data pad, and a power supply pad are formed at one end of the gate wiring, the data wiring, and the power supply wiring, respectively. The method of claim 2, In the region covering the gate pad, the data pad, and the power supply pad, a dual panel type organic light emitting display device, in which a gate pad electrode, a data pad electrode, and a power supply pad electrode made of the same material are positioned in the same process as the power supply wiring, respectively. Array substrate for. The method of claim 3, wherein In the region covering the gate pad electrode, the data pad electrode, and the power supply pad electrode, a dual panel further including another gate pad electrode, a data pad electrode, and a power supply pad electrode made of the same material in the same process as the connection electrode. Array substrate for organic light emitting device. The method of claim 1, The switching thin film transistor has a structure in which a gate electrode branched from the gate wiring, an active layer made of an amorphous silicon material, and an ohmic contact layer made of an impurity silicon material are sequentially stacked in the region covering the gate electrode. A semiconductor layer, a source electrode and a drain electrode spaced apart from each other on the semiconductor layer, wherein the driving thin film transistor includes a driving gate electrode connected to the drain electrode and a position covering the driving gate electrode; An array substrate for a dual panel type organic light emitting display device, comprising: a driving semiconductor layer; and a driving source electrode and a drain electrode spaced apart from each other above the driving semiconductor layer. The method of claim 5, wherein The driving source electrode is an array substrate for a dual panel type organic light emitting device connected to a power electrode branched from the power supply wiring. In a method of manufacturing an array substrate for a dual panel type organic electroluminescent device in which an array device and an organic light emitting diode device are configured on different substrates, and the two devices are electrically connected through separate electrical connection patterns, Forming a gate electrode and a gate pad by forming a first metal material on a substrate, and then performing a first mask process which is a series of processes patterned by a photolithography process using a photo-resist (PR) photosensitive material; ; A first insulating material, an amorphous silicon material, and an impurity silicon material are continuously formed at a position covering the gate electrode and the gate pad, and then the first insulating material is used as a gate insulating film, and the gate electrode is covered by a second mask process. Forming a semiconductor layer at a location; A third mask process using a second metal material at a position covering the semiconductor layer to form a source electrode and a drain electrode spaced apart from each other on the semiconductor layer, a data pad, and the source electrode and the drain electrode By using as a mask, the impurity silicon material in the separation interval between the source electrode and the drain electrode is removed to form an amorphous silicon material region constituting the lower layer as a channel, the amorphous silicon material of the semiconductor layer as an active layer, Forming the impurity silicon material into an ohmic contact layer; The gate electrode, the semiconductor layer, the source electrode, and the drain electrode form a thin film transistor, and the source electrode, the gate pad, the data pad, and the power supply pad are formed by a fourth mask process using a second insulating material at a position covering the thin film transistor. Forming an interlayer insulating film having a source contact hole, a gate pad contact hole, a data pad contact hole, and a power supply pad contact hole, each of which exposes a portion thereof; By a fifth mask process using a third metal material on the interlayer insulating layer, a power electrode connected to the source electrode through the source contact hole and through the gate pad contact hole, data pad contact hole, and power supply pad contact hole. Forming a gate pad electrode, a data pad electrode, and a power supply pad electrode respectively connected to the gate pad, the data pad, and the power supply pad; A drain contact hole and a gate pad electrode partially exposing the drain electrode by a sixth mask process using a third insulating material at a position covering the power electrode, the gate pad electrode, the data pad electrode, and the power supply pad electrode; Forming a protective layer having first to third open portions partially exposing the pad electrode and the power supply pad electrode; Forming a pillar-shaped electrical connection pattern on an electrical connection portion defined as an area connected to the organic light emitting diode device by a seventh mask process using a fourth insulating material on the protective layer; Forming a connection electrode connected to a drain electrode through the drain contact hole and positioned in an area covering the electrical connection pattern by an eighth mask process using a fifth metal material in the region covering the electrical connection pattern; Method of manufacturing an array substrate for a dual panel type organic electroluminescent device comprising a. The method of claim 7, wherein In the forming of the connection electrode, another gate pad electrode connected to a gate pad electrode, a data pad electrode, and a power supply pad electrode through the first to third contact holes using the same material as the connection electrode. And forming a data pad electrode and a power supply pad electrode, respectively. The method of claim 7, wherein The thin film transistor is a method for manufacturing an array substrate for a dual panel type organic electroluminescent device corresponding to a driving thin film transistor connected to the organic light emitting diode device. The method of claim 7, wherein And the gate pad contact hole and the power supply pad contact hole are contact holes that the gate insulating film and the interlayer insulating film have in common. The method of claim 7, wherein The first mask process includes forming a gate wiring connected to the gate electrode, and in the fourth mask process, forming a data wiring in a direction crossing the gate wiring. 5. A method of manufacturing an array substrate for a dual panel type organic light emitting display device, the method comprising: forming a power supply line connected to the power electrode and spaced apart from each other in the same direction as the data line.