KR100497093B1 - Array substrate for dual panel type electroluminescent device and method for fabricating the same - Google Patents

Abstract

According to the dual panel type organic light emitting display device and its manufacturing method according to the present invention, firstly, since the array device and the organic light emitting diode device are formed on different substrates, the production yield and production management efficiency can be improved, and the product It can increase the lifespan. Second, it is easy to design thin film transistor and realize high opening ratio / high resolution because of top emitting method. Third, low temperature process is possible by adopting inverse staggered thin film transistor structure using amorphous silicon material. Even if a separate electrical connection pattern is added, the number of mask processes can be reduced than before, and thus, the production yield can be more effectively increased by simplifying the process.

Description

Array substrate for dual panel type electroluminescent device and method for fabricating the same}

The present invention relates to an organic electroluminescent device, and more particularly to a low-mask dual panel type organic electroluminescent device (Active-Matrix Organic Electroluminescent Device) and a method of manufacturing the same.

One of the new flat panel displays, the organic light emitting display device is self-luminous, and thus has a better viewing angle and contrast ratio than a liquid crystal display device. In addition, since it is possible to drive DC low voltage, fast response speed, and all solid, it is strong against external shock, wide use temperature range, and especially inexpensive in terms of manufacturing cost.

In particular, since the organic light emitting device has a very simple process unlike a liquid crystal display device or a plasma display panel (PDP), deposition and encapsulation equipment are all.

In particular, in the active matrix system, the voltage applied to the pixel is charged in the storage capacitance (C _ST ), and the power is applied until the next frame signal is applied, thereby relating to the number of gate wirings. Run continuously for one screen without

Therefore, in the active matrix system, since the same luminance is displayed even when a low current is applied, low power consumption, high definition, and large size can be obtained.

Hereinafter, the basic structure and operation characteristics of the active matrix organic electroluminescent device will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a basic pixel structure of a general active matrix organic light emitting display device.

As shown, a scan line is formed in the first direction, is formed in a second direction crossing the first direction, and a signal line and a power supply line spaced apart from each other by a predetermined distance are provided. Formed to define one pixel area.

The scanning line and the intersection of the signal line has the addressing element switching thin film transistor (addressing element); and is formed with a (T _S Switching TFT), a switching thin film transistor connected to the (T _S) of storage capacitance (C _ST) is formed And a driving thin film transistor T _D , which is a current source element, is connected to a connection portion and a power supply line of the switching thin film transistor T _S and the storage capacitance C _ST to form the driving thin film transistor T _D. An anode (+) is connected to (T _D ), and an anode (+) is connected to a cathode (−) through an electroluminescent diode (E) of a constant current driving method.

An anode (+) and a cathode (-) connected by the organic light emitting diode device (E) constitute an organic light emitting device.

The switching thin film transistor T _S controls the voltage, and the storage capacitance C _ST serves to store a current source.

Hereinafter, the driving principle of the active matrix organic light emitting display device will be described.

In the active matrix method, when a signal is applied to a corresponding electrode according to a selection signal, the gate of the switching thin film transistor is turned on, and the data signal passes through the gate of the switching thin film transistor, and is applied to the driving thin film transistor and the storage capacitance. When the gate of the driving thin film transistor is turned on, current from the power supply line is applied to the organic light emitting layer through the gate of the driving thin film transistor to emit light.

At this time, the degree of opening and closing of the gate of the driving thin film transistor is changed according to the magnitude of the data signal, so that the gray scale display can be performed by adjusting the amount of current flowing through the driving thin film transistor.

In the non-selection period, data charged in the storage capacitance is continuously applied to the driving thin film transistor, so that the organic light emitting diode can emit light continuously until the next screen signal is applied.

FIG. 2 is a plan view of one pixel portion of a conventional active matrix type organic light emitting display device, and a description will be given using an example of a two TFT structure having one switching thin film transistor and one driving thin film transistor.

As shown in the drawing, the gate wiring 37 is formed in the first direction, the data wiring 51 and the power supply wiring 41 are formed to intersect the gate wiring 37 and are spaced apart from each other. An area where the 37, the data line 51, and the power supply line 41 intersect with each other defines the pixel area P.

A switching thin film transistor T _S is positioned in an area where the gate wiring 37 and a data wiring 51 cross each other, and a driving thin film transistor Ts is positioned at a point where the switching thin film transistor T _S and the power supply wiring 41 cross each other. T _D ) is disposed to form a storage capacitance C _ST in which the power supply wiring 41 and the capacitor electrode 134 forming an integrated pattern with the semiconductor layer 31 of the switching thin film transistor T _S overlap each other. .

In addition, the first electrode 58 is formed in connection with the driving thin film transistor T _D , and although not shown in the drawing, the organic light emitting layer and the second electrode are sequentially formed in the region covering the first electrode 58. Is formed.

The first electrode forming part is defined as an organic light emitting part (I).

Reference numeral 32 denotes a semiconductor layer for the driving thin film transistor T _D , and 35 and 38 correspond to a gate electrode of the switching thin film transistor T _S and the driving thin film transistor T _D , respectively. .

Hereinafter, the stacked structure of the organic light emitting unit, the driving thin film transistor, and the storage capacitance will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a cross section taken along the cutting line ii-ii of FIG. 2.

As illustrated, a driving thin film transistor T _D including the semiconductor layer 32, the gate electrode 38, the source and the drain electrodes 50 and 52 is formed on the insulating substrate 1. A power electrode 42 branched from a power supply wiring (not shown) is connected to the electrode 50, and a first electrode 58 made of a transparent conductive material is connected to the drain electrode 52.

A capacitor electrode 34 made of the same material as that of the semiconductor layer 32 is formed in a lower portion corresponding to the power electrode 42, so that the power electrode 42 and the capacitor electrode 34 overlap each other. The region forms the storage capacitance C _ST .

In addition, an organic light emitting layer 64 and a cathode 66 made of an opaque metal material are sequentially stacked on the first electrode 58 to form the organic light emitting unit I.

Looking at the stacked structure of the insulating layers positioned in the organic light emitting unit (I), the buffer layer 30 to the buffer between the insulating substrate 1 and the semiconductor layer 32 and the storage capacitance (C _ST ) The first protective layer 40 used as the insulator for the insulation, the second protective layer 44 between the drain electrode 52 and the power electrode 42, the first electrode 58 and the source electrode 50. The third protective layer 54 therebetween and the fourth protective layer 60 between the thin film transistor T and the first electrode 58 are sequentially stacked, and the first to fourth protective layers 40, 44, 54, and 60 each include a contact hole (not shown) for electrical connection between each layer.

Hereinafter, FIGS. 4A to 4I are cross-sectional views illustrating cross-sectional views cut along the cutting line ii-ii of FIG. 2 according to manufacturing steps, respectively. The exposure and development using photo-resist (PR) as a photosensitive material, respectively. It proceeds by the process of patterning by the photolithography process including the process), and this series of patterning processes are defined as a mask process, and it demonstrates in order of a process.

In FIG. 4A, a buffer layer 30 is formed on the insulating substrate 1 using the first insulating material over the entire surface of the substrate, and the polysilicon is used on the buffer layer 30 to be active by the first mask process. Layer 32a and capacitor electrode 34 are formed.

Next, in FIG. 4B, a second insulating material and a first metal are successively deposited on the substrate having passed through the step of FIG. 4A, and then gate insulating films are respectively formed at the center of the active layer 32a by a second mask process. 36 and the gate electrode 38.

In FIG. 4C, a first protective layer 40 made of a third insulating material is formed on the substrate having passed through FIG. 4B, and a second metal is deposited on the first protective layer 40. The power electrode 42 is formed in the position which covers the said capacitor electrode 34 by a three mask process.

In FIG. 4D, after depositing a third insulating material on the substrate having passed through FIG. 4C, the fourth mask process exposes both ends of the active layer 32a and a part of the power electrode 42. The second protective layer 44 having the first and second ohmic contact holes 46a and 46b and the capacitor contact hole 48 is formed.

Both ends of the active layer 32a form a drain region iiia and a right portion constitute a source region iiib so as to be connected to source and drain electrodes to be formed in a later process.

In this step, the exposed both ends of the active layer 32a are ion-doped, and the ion-doped portion is formed of an ohmic contact layer 32b containing impurities to form the active layer 32a. ) And the ohmic contact layer 32b are completed.

Next, in step 4E, after depositing the third metal, the power electrode 42 is formed through the capacitor contact hole 48 of FIG. 4D and the first ohmic contact hole 46A of FIG. 4D by a fifth mask process. ) And a source electrode 50 connected to the ohmic contact layer 32b of the source region iiib, spaced apart from the source electrode 50 by a predetermined interval, and drained through the second ohmic contact hole 46b of FIG. 4D. A drain electrode 52 connected to the ohmic contact layer 32b in the region iiia is formed.

In this step, the driving thin film transistor T _D including the semiconductor layer 32, the gate electrode 38, the source and drain electrodes 50 and 52 is completed.

On the other hand, the power electrode 42 and the capacitor electrode 34 are electrically connected to the source electrode 52 and the semiconductor layer of the switching thin film transistor (not shown), respectively, the first protective layer 40 as an insulator, the storage The capacitance C _ST is formed.

In FIG. 4F, after depositing the fourth insulating material on the substrate having passed through FIG. 4E, the third protective layer 54 having the drain contact hole 56 is formed by the sixth mask process.

Next, in step 4G, an organic field, which is an organic light emitting layer region, is formed by a seventh mask process using a fourth metal so as to be connected to the drain electrode 50 through the drain contact hole 56 in FIG. 4F. The first electrode 58 is formed in the light emitting part I.

In FIG. 4H, after depositing a fifth insulating material on the substrate having undergone the 4g step, the first electrode exposing the first electrode 58 corresponding to the organic light emitting unit I by an eighth mask process is exposed. The fourth protective layer 60 having the exposed portion 62 is formed.

The fourth protective layer 60 serves to protect the driving thin film transistor T _D from moisture and foreign matter.

As a result, the manufacturing process accompanied by the mask process is finished, and then, in step 4i, the organic light emitting layer 64 connected to the first electrode 58 through the first electrode exposed portion 62 of FIG. 4h, and The second electrode 66 is formed over the entire surface of the organic electroluminescent layer 64 by using a fifth metal.

For example, when the first electrode 58 is used as an anode, the material forming the fifth metal may reflect light emitted from the organic electroluminescent layer 64 to the first electrode 58 to emit the organic electroluminescent device. In order to realize the screen, the metal material having the reflective characteristic and the low work function value is selected so that the electron can be easily presented.

Hereinafter, a laminated structure of a conventional organic light emitting diode panel will be described in detail with reference to the accompanying drawings.

FIG. 5 is a cross-sectional view of an organic light emitting display device according to the related art, and illustrates an encapsulation structure around an organic light emitting display unit and a driving thin film transistor connection unit.

As shown in the drawing, the first and second substrates 70 and 90 are disposed to be spaced apart from each other by a subpixel unit, which is the minimum unit for implementing a screen, and the sub-pixel unit is disposed on an inner surface of the first substrate 70. a plurality of driving thin film transistors formed (T _D) for containing the array and the element layer 80 is formed, the array element layer 80, an upper portion the driving thin film transistor (T _D) is connected to the first electrode (72 in sub-pixels, ) Is formed, and an organic light emitting layer 74 emitting red, green, and blue colors in subpixel units is formed on the first electrode 72, and a second electrode is formed on the entire upper surface of the organic light emitting layer 74. 76 is formed.

The organic light emitting layer 74 interposed between the first and second electrodes 72 and 76 and the first and second electrodes 72 and 76 forms an organic light emitting diode device E, and the organic light emitting layer 74 The light emitted from the light emitting device is characterized in that the bottom emission method is emitted toward the first electrode (72).

The second substrate 90 is used as an encapsulation substrate, and a recess 92 is formed at an inner central portion of the second substrate 90, and moisture from the outside is formed in the recess 92. A moisture absorbent 94 is sealed to block absorption to protect the organic light emitting diode device E.

The inner surface of the second substrate 90 in which the moisture absorbent 94 is sealed and the second electrode 76 are positioned to be spaced apart from each other by a predetermined distance.

The edges of the first and second substrates 70 and 90 are encapsulated by the seal pattern 85.

As described above, the conventional bottom emission type organic light emitting diode device is manufactured by bonding an array device and a substrate on which an organic light emitting diode is formed and a separate substrate for encapsulation. In this case, since the product of the yield of the array device and the yield of the organic light emitting diode determines the yield of the organic light emitting diode, the overall organic process of the organic light emitting diode structure yields the overall process yield by the organic electroluminescent diode process. There was a problem that is greatly limited. For example, even if the array element is well formed, if the defect is caused by foreign matter or other elements in forming the organic light emitting layer using the thin film of about 1,000 mW, the organic light emitting element is judged as a poor grade. .

This results in a loss of overall costs and material costs that were required to manufacture the array device of good quality, there was a problem that the production yield is lowered.

In addition, the bottom emission method has a high degree of freedom and stability due to the encapsulation process, and has a problem in that it is difficult to be applied to a high resolution product due to the limitation of the aperture ratio, and the top emission method is easy to design a thin film transistor and improves the aperture ratio. It is advantageous in terms of product life, but in the conventional top emission type structure, since the material selection range is narrow as the cathode is normally positioned on the organic light emitting layer, the transmittance is limited and the light efficiency is reduced, and the light transmittance is minimized. In order to configure a thin film type protective film, there was a problem in that it does not sufficiently block outside air.

In order to solve the above problems, the present invention is to provide a high-resolution / high aperture structure active matrix organic electroluminescent device with improved production yield.

To this end, in the present invention, the array element and the organic light emitting diode element are formed on different substrates, and the dual layer for connecting the driving thin film transistor of the array element and the second electrode of the organic light emitting diode element through a separate electrical connection pattern. An object of the present invention is to provide a panel type organic electroluminescent device.

Another object of the present invention is to provide a manufacturing process of a substrate for a four mask dual panel type organic electroluminescent device by employing an inverted staggered thin film transistor structure using an amorphous silicon material.

When the process is performed by including the reverse staggered thin film transistor, the process may be performed under low temperature conditions, and the number of mask processes may be reduced even if the process is performed including an electrical connection pattern.

In order to achieve the above object, in the first aspect of the present invention, the first substrate (array substrate) and the second substrate (organic electroluminescent diode substrate) disposed to be spaced apart from each other, and are located between the first and second substrates, A dual panel type organic electroluminescent device comprising a pattern portion for electrically connecting the first and second substrates, comprising: a gate wiring formed in a first direction on the first substrate; A data line formed in a second direction crossing the first direction; A power supply wiring formed in the second direction, spaced apart from the data wiring, made of the same material in the same process as the gate wiring, and having a separate power supply link wiring at an intersection with the gate wiring; A switching thin film transistor formed at an intersection point of the gate line and the data line and having a semiconductor layer; A driving thin film transistor formed at an intersection point between the switching thin film transistor and the power supply wiring and having a semiconductor layer made of the same material as the switching thin film transistor; A connection electrode formed to be connected to the driving thin film transistor; Located in the connection electrode region, the organic light emitting diode device and the connection electrode are connected to each other, and in the contact hole process of the protective layer for the thin film transistor, a pillar-shaped connection pattern formed in an integral pattern with the protective layer by diffraction exposure method. The semiconductor layer may be patterned in the same process as the data line to provide an array substrate for a dual panel type organic light emitting display device having a pattern structure corresponding to the data line.

A gate pad, a data pad, and a power supply pad are formed at one end of the gate wiring, the data wiring, and the power supply wiring, respectively, and in the region covering the gate pad and the power supply pad, the same material in the same process as the connection electrode. And a gate pad electrode and a power supply pad electrode each of which is formed in the switching thin film transistor, the gate electrode branched from the gate wiring, an active layer formed in an area covering the gate electrode, and formed of an amorphous silicon material; A semiconductor layer having an ohmic contact layer made of an impurity silicon material is sequentially stacked, and a source electrode and a drain electrode positioned to be spaced apart from each other on the semiconductor layer, and the driving thin film transistor is connected to the drain electrode. A driving gate electrode and the driving gate And a driving source electrode and a drain electrode positioned to be spaced apart from each other on the driving semiconductor layer at a position covering the electrode.

A protective layer is located in an area covering the thin film transistor, and the protective layer includes a source contact hole, a drain contact hole, a data pad contact hole, and a gate partially exposing a source electrode, a drain electrode, a data pad, a gate pad, and a power supply pad. Further comprising a pad contact hole, a power supply pad contact hole, made of the same material in the same process as the connection electrode, and includes a power electrode connected to the source electrode through the source contact hole, wherein the power electrode is supplied with power The power supply link wiring is also made of the same material in the same process as the data wiring, and the power supply link wiring and the power supply wiring are made of the same material in the same process as the connection electrode. Connected to each other, and the formation thickness of the electrical connection pattern is thicker than the thickness in other areas of the protective layer. And that is characterized.

According to a second aspect of the present invention, there is provided an array substrate for a dual panel type organic electroluminescent device in which an array element and an organic light emitting diode element are formed on different substrates, and the two elements are electrically connected through separate connection electrodes. In the manufacturing method, a gate electrode and a gate pad are formed by a first mask process, which is a series of processes in which a first metal material is formed on a substrate and then patterned by a photolithography process using a photo-resist (PR) material. Forming a power supply pad; A first insulating material, an amorphous silicon material, an impurity silicon material, and a second metal material are successively formed at a position covering the gate electrode and the gate pad, and the first insulating material is a gate insulating film, and the first diffraction exposure method The semiconductor layer, a source electrode and a drain electrode spaced apart from each other on the semiconductor layer, and a data pad are formed by a second mask process using a second mask process, and the source electrode and the drain electrode are used as masks. And removing the impurity silicon material in the separation interval between the drain electrodes to form an amorphous silicon material region constituting the lower layer as a channel, the amorphous silicon material of the semiconductor layer as an active layer, and the impurity silicon material as an ohmic contact layer. Constructing; The gate electrode, the semiconductor layer, the source electrode, and the drain electrode form a thin film transistor, a second insulating material is formed on the thin film transistor and the data pad, and then the source is subjected to a third mask process using a second diffraction exposure method. The organic light emitting diode has a source contact hole, a drain contact hole, a data pad contact hole, a gate pad contact hole, and a power supply pad contact hole that partially expose an electrode, a drain electrode, a data pad, a gate pad, and a power supply pad. Forming a protective layer having a monolithic pattern of an electrical connection pattern having a columnar shape in an electrical connection portion defined as an area connected with the device; A fourth electrode process using a third metal material on the passivation layer, a connection electrode positioned in a region covering the electrical connection pattern through the drain contact hole and covering the electrical connection pattern, and a source through the source contact hole A power electrode connected to an electrode, a data pad electrode connected to a data pad through the data pad contact hole, a gate pad electrode connected to a gate pad through the gate pad contact hole, and a power supply pad through the power supply pad contact hole It provides a method of manufacturing an array substrate for a dual panel type organic electroluminescent device comprising the step of forming a power supply pad electrode connected to the.

The first mask process may include forming a gate wiring connected to the gate electrode and a power supply wiring crossing the gate wiring and connected to the power supply pad. Forming a data line spaced apart from each other in the same direction as the power supply line and forming a power supply link line which is a power supply line part positioned at an intersection with the gate line. And forming a pattern for electrically connecting a supply wiring and a power supply link wiring, and electrically connecting the power electrode and a power supply wiring, wherein the thin film transistor is a driving thin film connected to an organic light emitting diode device. A second mask corresponding to a transistor and using the first diffraction exposure method In the ink process, applying a PR material on the second metal material and disposing a mask having a slit pattern at a position corresponding to a channel portion defined as an area corresponding to a center portion of the gate electrode. Forming a PR pattern having a concave portion in the channel portion through a subsequent exposure process, and performing the exposure process, and continuously exposing the exposed second metal material, the impurity silicon material, and the amorphous silicon material using the PR pattern. And etching the PR pattern to a thickness value at which the metal material of the channel portion is exposed, and etching the exposed metal layer using the etched PR pattern as a mask. It features.

In a third mask process using the second diffraction exposure method, the second insulating material is selected from a negative type photosensitive organic insulating material, and the source electrode and the drain electrode are formed on the substrate coated with the negative type photosensitive organic insulating material. And exposing using a mask having a light blocking portion at a position corresponding to the forming portion, the pad forming portion, the opening portion in the electrical connection pattern forming portion, and the slit portion in other regions. The formation thickness is thicker than the thickness in other regions of the protective layer, and the gate pad contact hole and the power supply pad contact hole are contact holes which the gate insulating layer and the protective layer have in common.

First Embodiment

FIG. 6 is a cross-sectional view of a dual panel type organic light emitting display device according to a first embodiment of the present invention, and is schematically illustrated around an electrical connection structure.

As shown in the drawing, the first and second substrates 110 and 150 are disposed to face each other at a predetermined interval in subpixel units, which are the minimum units for implementing the screen.

An array element layer 140 including a plurality of driving thin film transistors T _D formed in subpixel units is formed on the inner surfaces of the first substrates 110 and 150, and a drive is formed on the array element layer 140. The electrical connection pattern 142 is formed by being connected to the thin film transistor T _D.

The electrical connection pattern 142 is selected from a conductive material, and the electrical connection pattern 142 may be formed of a multilayer including an insulating material in order to be formed in a sense of thickness, and may be driven through a separate connection electrode. T _D ) may be connected.

The driving thin film transistor T _D may include a gate electrode 112, a semiconductor layer 114, a source electrode 116, and a drain electrode 118, and the aforementioned electrical connection pattern 142 may be substantially drained. It is connected to the electrode 118.

The first electrode 152 is formed on the entire inner surface of the second substrate 150, and the red, green, and blue light emitting layers 156a, 156b, and 156c are repeatedly arranged in subpixel units below the first electrode 152. ) Is formed, and the second electrode 162 is formed in the subpixel unit below the organic light emitting layer 160.

In more detail, the organic light emitting layer 160 may include a first carrier transfer layer 154 in contact with the bottom surface of the first electrode 152, and a lower portion of the red, green, and blue light emitting layers 156a, 156b, and 156c. And a second carrier transfer layer 158 in contact with the top surface of the second electrode 162.

For example, when the first electrode 152 corresponds to an anode and the second electrode 162 corresponds to a cathode, the first carrier transport layer 154 corresponds to the hole injection layer and the hole transport layer in order, and the second carrier The transport layer 158 corresponds to an electron transport layer and an electron injection layer in order.

The organic light emitting layer 160 interposed between the first and second electrodes 152 and 162 and the first and second electrodes 152 and 162 corresponds to the organic light emitting diode device E.

In the present invention, the top surface of the electrical connection pattern 142 is connected to the lower surface of the second electrode 162, the current supplied from the driving thin film transistor (T _D ) is the second electrode through the electrical connection pattern 142. Characterized in that it is delivered to (162).

The seal patterns 170 are positioned at edges of the first and second substrates 110 and 150 to bond the first and second substrates 110 and 150 to each other.

In the present embodiment, the organic light emitting diode device E and the array device layer 140 are formed on different substrates, but are configured in a dual panel type in which two devices are connected using an electrical connection pattern 142. It is characterized by.

For convenience of description, a two-pixel structure in which three subpixels constitute one pixel is illustrated as an example, and a thin film transistor structure and a connection method of an electrical connection pattern may be variously changed.

In addition, since the dual panel type organic light emitting display device according to the present invention has an upper light emitting method as shown in the light emitting direction on the drawing, the thin film transistor design is easy and high opening ratio / high resolution can be realized.

Second Embodiment

7 is a plan view of a dual panel type organic light emitting display device according to a second exemplary embodiment of the present invention.

As shown, the gate wiring 212 is formed in the first direction, and the data wiring 250 and the power supply wiring 220 are formed to be spaced apart from each other in the second direction crossing the first direction. A switching thin film transistor T _S is formed at a point where the gate line 212 and the data line 250 cross each other. The switching thin film transistor T _S includes a gate electrode 214 branched from the gate line 212, a source electrode 240 branched from the data line 250, and a drain disposed to be spaced apart from the source electrode 240. The semiconductor layer 236 is formed in a region covering the electrode 244, the gate electrode 214, the source electrode 240, and the drain electrode 244.

The power supply wiring 220 is made of the same material as the gate wiring 212 in the same process.

The driving thin film transistor T _S is connected to the switching thin film transistor T _S and the power supply line 220 to form a driving thin film transistor T _D. The driving thin film transistor T _D includes a driving gate electrode 216 made of the same material in the same process as the gate wiring 212, and connected to the drain electrode 244, and the driving gate electrode 216. Are overlapped with both sides of the c) and spaced apart from each other, and are formed of the same source and drain electrodes 242 and 246 in the same process as the data line 250, the driving gate electrode 216, The driving semiconductor layer 238 is positioned in an area covering the driving source and drain electrodes 242 and 246.

The power source 270 is formed by being connected to the driving source electrode 242 and the source contact hole 254, and one side of the power electrode 270 is connected to a power supply line through the power supply contact hole 264. 220).

In addition, the connection electrode 272 is formed in the electrical connection portion IV in connection with the driving drain electrode 246. The power electrode 270 and the connection electrode 272 are made of the same material in the same process.

The electrical connection part IV corresponds to a region range corresponding to the second electrode of the organic light emitting diode substrate (not shown).

Although not shown in the drawings, the electrical connection part IV includes a columnar electrical connection pattern, and the electrical connection pattern will be described in more detail through a cross-sectional stacked structure.

In addition, the drain electrode 246 includes a capacitor electrode 248 extending to overlap with the power supply wiring 220, and a region where the capacitor electrode 248 and the power supply wiring 220 overlap each other is a storage capacitance. (C _ST ).

Data pads 252, gate pads 218, and power supply pads 222 are formed at one end of each of the data line 250, the gate line 212, and the power supply line 220. The data pad electrode 274, the gate pad electrode 276, and the power supply, which are made of the same material in the same process as the connection electrode 272, are disposed at a position covering the gate pad 218, the gate pad 218, and the power supply pad 222. Pad electrodes 278 are formed, respectively.

In addition, the semiconductor layer 236, the driving semiconductor layer 238, and the data wiring 250 have a pattern structure corresponding to each other as they are formed in the same process, so that the semiconductor layer 236 and the driving semiconductor layer are formed. The material constituting 238 is present as the semiconductor material layer 226 in the data line 250, the capacitor electrode 248, and the data pad 252.

In particular, in the present embodiment, as the gate wiring 212 and the power supply wiring 220 are formed in the same process, in order to prevent the gate wiring 212 and the power supply wiring 220 from being shorted at the intersection, the data wiring In the same process as the reference numeral 250, the first link wiring 279a for supplying power to the intersection with the gate wiring 212 is used as the connection wiring for the power supply wiring 220 using the same material.

In more detail, on both sides of the power supply first link wiring 279a, the power supply second link wiring 279b made of the same material as the connection electrode 272 in the same process is located, thereby providing a power supply second. The link wire 279b is substantially connected to the power supply wire 220.

In this case, since the data pad 252 and the power supply pad 222 are applied with different signal voltages, the data pad 252 and the power supply pad 222 are preferably formed at opposite ends of each other as shown in the drawing.

Third Embodiment

8a to 8d, 9a to 9d, 10a to 10d, and 11a to 11d each make cross sections cut along the cutting lines IIa-IIa, IIb-IIb, IIc-IIc, and IId-IId of FIG. Fig. 2 is a cross-sectional view showing step-by-step, IIa-IIa is a driving thin film transistor unit, IIb-IIb is a data pad unit, IIc-IIc is a gate pad unit, and IId-IId is a power supply pad unit. The electrode, the driving semiconductor layer, the driving source electrode, and the drain electrode will be briefly described as a gate electrode, a semiconductor layer, a source electrode, and a drain electrode.

8A, 9A, 10A, and 11A, forming a gate electrode 216, a gate pad 218, and a power supply pad 222 on a substrate 210 by a first mask process using a first metal material. to be.

Although not shown in the drawing, in this step, the power supply wiring is formed in an integrated pattern with the power supply pad 222.

The first metal material is selected from a metal material having a low specific resistance value, and is preferably selected from a metal material including aluminum.

Although not shown in detail in the drawings, the mask process used in the present invention is applied by applying a photosensitive material PR, then placing a mask having a desired pattern, and then exposed using a PR pattern formed through exposure and development as a mask. Corresponds to the method of patterning by etching the layer to be etched.

8B, 9B, 10B, and 11B illustrate a first insulating material, an amorphous silicon material (a-Si), and an impurity silicon material in an area covering the gate electrode 216, the gate pad 218, and the power supply pad 222. (n + a-Si) and a second metal material are sequentially formed, and then the first insulating material is used as the gate insulating film 224, and the second metal material and the impurity silicon material (n + a) are formed by a second mask process. -Si) and an amorphous silicon material (a-Si) are continuously etched to have a semiconductor layer 232 positioned in a region covering the gate electrode 216, and a pattern structure corresponding to the semiconductor layer 232, Forming a source pad 242 and a drain electrode 246 spaced apart from each other on the semiconductor layer 232 and a data pad 252 in the data forming unit III.

Although not shown in the drawing, this step includes forming a data line in a second direction, wherein the data pad forming unit III corresponds to one end region of the data line, preferably the power supply pad. 222 and the opposite end of each other.

The gate electrode 216, the semiconductor layer 232, the source electrode 242, and the drain electrode 246 form a driving thin film transistor T _D.

The semiconductor layer 232 has a structure in which an active layer 232a made of an amorphous silicon material and an ohmic contact layer 232b made of an impurity amorphous silicon material are sequentially stacked. In this step, the source electrode 242 is stacked. ) And the drain electrode 246 as a mask to remove the ohmic contact layer 232b disposed in the section between the source electrode 242 and the drain electrode 246 and expose the active layer 232a exposed in the separation section. ) Configuring the region into channels ch.

Below the data pad 252, a semiconductor material layer 226 having a structure in which an amorphous silicon material layer 226a and an impurity silicon material layer 226b made of the same material as the semiconductor layer 232 is sequentially stacked corresponds to the data pad 252. Exists as a pattern structure.

In this step, in the process of continuously etching the source electrode 242, the drain electrode 246 and the semiconductor layer 232 by the same mask process, selectively removing only the metal material layer from the channel ch part. In order to selectively etch using one of these mask processes, it is preferable to use a diffraction exposure method capable of adjusting the exposure amount of light.

The diffraction exposure method will be described in more detail with reference to another drawing. (See FIGS. 12A and 12B)

Preferably, the first insulating material is selected from a silicon insulating material, more preferably, a silicon nitride film (SiNx), and the second metal material is selected from a metal material having high chemical corrosion resistance, and preferably, molybdenum ( Mo, titanium (Ti), chromium (Cr), tungsten (W) is selected from any one.

8C, 9C, 10C, and 11C show a second insulating material formed in an area covering the driving thin film transistor T _D , the data pad 252, the gate pad 218, and the power supply pad 222. Next, a source contact hole 254 partially exposing the source electrode 242, the drain electrode 246, the data pad 252, the gate pad 218, and the power supply pad 222 by a third mask process. ), A protective layer 268 having a drain contact hole 256, a data pad contact hole 258, a gate pad contact hole 260, and a power supply pad contact hole 262.

In this case, the gate pad contact hole 260 and the power supply pad contact hole 262 have a common gate insulating film 320 and a protective layer 268 in a region covering the gate pad 218 and the power supply pad 319. The branches correspond to the respective contact holes.

In particular, the protective layer 268 is characterized in that the electrical connection portion IV has a columnar connection pattern 266 integrally.

The electrical connection part IV is preferably located in a region corresponding to the second electrode of the organic light emitting diode device (not shown).

In this step, the second insulating material is selected from the photosensitive organic material without a separate PR material, and a mask process is performed. The photosensitive organic material is selected from a photo-acrylic resin. It is preferable.

In this case, the thickness d1 of the connection pattern 266 may be thicker than the thickness d2 of the peripheral protection layer 268. The contact hole and the connection pattern may be formed in the protection layer 268 in one mask process. In order to simultaneously form 266, a diffraction exposure process is used, and this diffraction exposure process will be described in detail with reference to a separate drawing.

8D, 9D, 10D, and 11D show a source electrode 242 through the source contact hole 254 by a fourth mask process using a third metal material in an area covering the electrical connection pattern 266. A connection electrode 272 which is connected to the drain electrode 246 via the power contact 270, the drain contact hole 256, and is formed on an electrical connection portion covering the electrical connection pattern 266, and the data pad contact hole ( A data pad electrode 274 connected to the data pad 252 through the 258, a gate pad electrode 276 connected to the gate pad 218 through the gate pad contact hole 260, and a power pad contact hole Forming a power supply pad electrode 278 connected to the power supply pad 222 through 262.

Although not shown in the drawing, the power electrode 270 is connected to the power supply wiring formed in the gate process through a separate contact hole.

12A and 12B are cross-sectional views sequentially illustrating a contact hole process and a connection pattern manufacturing process of a protective layer using a diffraction exposure process according to the present invention.

In FIG. 12A, a thin film transistor T including a gate electrode 312, a semiconductor layer 314, a source electrode 316, and a drain electrode 318 is formed on the substrate 310. In the region adjacent to the thin film transistor T forming portion, an electrical connection portion V is defined.

On the entire surface of the substrate covering the thin film transistor (T), for example, forming a negative type organic material layer 320 in which a photosensitive part remains in a pattern through a developing process, and a negative type organic material layer 320 The mask 330 is disposed on the upper side thereof, and then an exposure process is performed.

In this case, the mask 330 includes a light blocking portion VIa at a position corresponding to a portion of the drain electrode 318, an open portion VIb at a position corresponding to a portion of the electrical connection portion V, and a light. The slit part VIc located in the area | regions other than the interruption | blocking part VIa and the open part VIb is comprised.

The light blocking portion VIa is a region for completely blocking light, the open portion VIb is a region for irradiating all the light onto a substrate, and the slit portion VIc is a light blocking portion VIa through a diffraction phenomenon of light. This corresponds to an area that lowers the amount of light irradiation.

In FIG. 12B, the exposed negative type organic material layer 320 of FIG. 12A may include a drain contact hole 340 partially exposing the drain electrode 318 and an electrical connection part through a developing process. It is formed of a protective layer 350 having a convex pattern portion VII positioned at V).

In this case, the convex pattern part VII forms an electrical connection pattern 352, and the thickness D1 of the electrical connection pattern 352 is thicker than the thickness D2 of the other protective layer 350.

The thickness difference D1-D2 between the electrical connection pattern 352 and the area of the protective layer 350 is due to the difference in the exposure amount in the exposure process of FIG. 12A.

As described above, in the present invention, the contact hole process and the convex pattern forming process may be formed in the same mask process by a mask process using a mask having three regions having different amounts of light irradiation.

However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

As described above, according to the dual panel type organic light emitting diode and a method of manufacturing the same according to the present invention, first, since the array element and the organic light emitting diode element are formed on different substrates, production yield and production management efficiency can be improved. Second, the product lifespan can be increased, and secondly, the upper light emitting method makes it easier to design thin film transistors and realizes high opening ratio / high resolution. Third, by adopting an inverse staggered thin film transistor structure using amorphous silicon material, This is possible, and even if a separate electrical connection pattern is added, the number of mask processes can be reduced than before, and the production yield can be more effectively increased by simplifying the process.

1 is a view showing a basic pixel structure of a general active matrix organic electroluminescent device.

2 is a plan view of one pixel portion of a conventional active matrix organic electroluminescent device.

3 is a cross-sectional view taken along the cut line ii-ii of FIG. 2.

4A to 4I are cross-sectional views each showing a cross section cut along the cutting line ii-ii of FIG.

5 is a cross-sectional view of a conventional organic light emitting display device.

6 is a cross-sectional view of a dual panel organic electroluminescent device according to a first embodiment of the present invention.

7 is a plan view of a dual panel type organic light emitting display device according to a second exemplary embodiment of the present invention.

8a to 8d, 9a to 9d, 10a to 10d, and 11a to 11d each make cross sections cut along the cutting lines IIa-IIa, IIb-IIb, IIc-IIc, and IId-IId of FIG. Fig. 2 is a cross-sectional view showing step by step, wherein IIa-IIa is a driving thin film transistor portion, IIb-IIb is a data pad portion, IIc-IIc is a gate pad portion, and IId-IId is a power supply pad portion.

<Explanation of symbols for main parts of drawing>

210: substrate 216: gate electrode

218: gate pad 222: power supply pad

224: gate insulating film 232a: active layer

232b: ohmic contact layer 232: semiconductor layer

242: source electrode 246: drain electrode

254: source contact hole 256: drain contact hole

268: protective layer 270: power electrode

272: connecting electrode IV: electrical connection

ch: Channel T _D : Driving Thin Film Transistor

Claims (15)

A first substrate (array substrate) and a second substrate (organic electroluminescent diode substrate) disposed to be spaced apart from each other, and a pattern portion disposed between the first and second substrates to electrically connect the first and second substrates. In the dual panel type organic light emitting device, Gate wiring formed on the first substrate in a first direction; A data line formed in a second direction crossing the first direction; A power supply wiring formed in the second direction, spaced apart from the data wiring, made of the same material in the same process as the gate wiring, and having a separate power supply link wiring at an intersection with the gate wiring; A switching thin film transistor formed at an intersection point of the gate line and the data line and having a semiconductor layer; A driving thin film transistor formed at an intersection point between the switching thin film transistor and the power supply wiring and having a semiconductor layer made of the same material as the switching thin film transistor; A connection electrode formed to be connected to the driving thin film transistor; Located in the connection electrode region, the organic light emitting diode device and the connection electrode are connected to each other, and a pillar-shaped connection pattern formed in an integrated pattern with the protective layer by diffraction exposure method in the contact hole process of the protective layer for thin film transistor. And the semiconductor layer is patterned in the same process as the data line, and has a pattern structure corresponding to the data line. The method of claim 1, And a gate pad, a data pad, and a power supply pad are formed at one end of the gate wiring, the data wiring, and the power supply wiring, respectively. The method of claim 2, And a gate pad electrode and a power supply pad electrode each made of the same material in the same process as the connection electrode, in an area covering the gate pad and the power supply pad. The method of claim 1, The switching thin film transistor has a structure in which a gate electrode branched from the gate wiring, an active layer made of an amorphous silicon material, and an ohmic contact layer made of an impurity silicon material are sequentially stacked in the region covering the gate electrode. A semiconductor layer, a source electrode and a drain electrode spaced apart from each other on the semiconductor layer, wherein the driving thin film transistor includes a driving gate electrode connected to the drain electrode and a position covering the driving gate electrode; An array substrate for a dual panel type organic light emitting display device, comprising: a driving semiconductor layer; and a driving source electrode and a drain electrode spaced apart from each other above the driving semiconductor layer. The method according to any one of claims 2 to 4, A protective layer is located in an area covering the thin film transistor, and the protective layer includes a source contact hole, a drain contact hole, a data pad contact hole, and a gate partially exposing a source electrode, a drain electrode, a data pad, a gate pad, and a power supply pad. An array substrate for a dual panel type organic light emitting device having a pad contact hole and a power supply pad contact hole. The method of claim 5, wherein An array of dual panel type organic light emitting diodes, which includes a power electrode made of the same material in the same process as the connection electrode and connected to the source electrode through the source contact hole, wherein the power electrode is also connected to a power supply line. Board. The method of claim 1, The power supply link wiring is made of the same material in the same process as the data wiring, and the power supply link wiring and the power supply wiring are connected to each other through a pattern made of the same material in the same process as the connection electrode. Array substrate for organic electroluminescent device. The method of claim 1, The formation thickness of the electrical connection pattern, the array panel for a dual panel type organic electroluminescent device, characterized in that thicker than the thickness in other areas of the protective layer. In a method for manufacturing an array substrate for a dual panel type organic electroluminescent device, in which an array device and an organic light emitting diode device are configured on different substrates, and two devices are electrically connected through separate connection electrodes, After the first metal material is formed on the substrate, the gate electrode, the gate pad, and the power supply pad are formed by a first mask process, which is a series of processes of patterning the photo metal using a photo-resist (PR) photosensitive material. Forming; A first insulating material, an amorphous silicon material, an impurity silicon material, and a second metal material are successively formed at a position covering the gate electrode and the gate pad, and the first insulating material is a gate insulating film, and the first diffraction exposure method The semiconductor layer, a source electrode and a drain electrode spaced apart from each other on the semiconductor layer, and a data pad are formed by a second mask process using a second mask process, and the source electrode and the drain electrode are used as masks. And removing the impurity silicon material in the separation interval between the drain electrodes to form an amorphous silicon material region constituting the lower layer as a channel, the amorphous silicon material of the semiconductor layer as an active layer, and the impurity silicon material as an ohmic contact layer. Constructing; The gate electrode, the semiconductor layer, the source electrode, and the drain electrode form a thin film transistor, a second insulating material is formed on the thin film transistor and the data pad, and then the source is subjected to a third mask process using a second diffraction exposure method. The organic light emitting diode has a source contact hole, a drain contact hole, a data pad contact hole, a gate pad contact hole, and a power supply pad contact hole that partially expose an electrode, a drain electrode, a data pad, a gate pad, and a power supply pad. Forming a protective layer having a monolithic pattern of an electrical connection pattern having a columnar shape in an electrical connection portion defined as an area connected with the device; A fourth electrode process using a third metal material on the passivation layer, a connection electrode positioned in a region covering the electrical connection pattern through the drain contact hole and covering the electrical connection pattern, and a source through the source contact hole A power electrode connected to an electrode, a data pad electrode connected to a data pad through the data pad contact hole, a gate pad electrode connected to a gate pad through the gate pad contact hole, and a power supply pad through the power supply pad contact hole Forming a power supply pad electrode connected to the Method of manufacturing an array substrate for a dual panel type organic electroluminescent device comprising a. The method of claim 9, The first mask process may include forming a gate wiring connected to the gate electrode and a power supply wiring crossing the gate wiring and connected to the power supply pad. Forming a data line spaced apart from each other in the same direction as the power supply line and forming a power supply link line which is a power supply line part positioned at an intersection with the gate line. A method of manufacturing an array substrate for a dual panel type organic light emitting display device, comprising: forming a pattern electrically connecting a supply wiring and a power supply link wiring; and electrically connecting the power electrode and a power supply wiring. The method of claim 9, The thin film transistor is a method for manufacturing an array substrate for a dual panel type organic electroluminescent device corresponding to a driving thin film transistor connected to the organic light emitting diode device. The method of claim 9, In the second mask process using the first diffraction exposure method, applying a PR material on the second metal material, and a slit pattern at a position corresponding to a channel portion defined as an area corresponding to a center portion of the gate electrode. placing a mask having a slit pattern and then exposing the mask; forming a PR pattern having a concave portion in the channel portion through the exposing step; a second metal material exposed using the PR pattern; Continuously etching the impurity silicon material and the amorphous silicon material, subjecting the PR pattern to a thickness value at which the metal material of the channel part is exposed, and exposing using the etched PR pattern as a mask A method of manufacturing an array substrate for a dual panel type organic electroluminescent device comprising etching the metal layer. The method of claim 9, In a third mask process using the second diffraction exposure method, the second insulating material is selected from a negative type photosensitive organic insulating material, and the source electrode and the drain electrode are formed on the substrate coated with the negative type photosensitive organic insulating material. Dual-panel type organic electroluminescence comprising the step of exposing using a mask having a light blocking portion at a position corresponding to the forming portion, the pad forming portion, the opening portion in the electrical connection pattern forming portion, and the slit portion in other regions. Method of manufacturing array substrate for device. The method of claim 9, Forming thickness of the electrical connection pattern, the manufacturing method of the array panel for a dual panel type organic electroluminescent device thicker than the thickness in the other region of the protective layer. The method of claim 9, And the gate pad contact hole and the power supply pad contact hole are contact holes which the gate insulating film and the protective layer have in common.