KR20040052304A - Security apparatus and method for digital hardware system - Google Patents

Abstract

PURPOSE: A device and a method for the security of a digital hardware system are provided to encrypt/decrypt data fast by using an exclusive binary operator and a similar random number generator, offer the high security by using an asymmetric encryption algorithm, and reinforce the security of the digital hardware system such as a set-top box or a digital game machine. CONSTITUTION: A hardware block(110) having a hardware security mechanism is equipped with a security target block(100) that is the security target of a CPU or a PCI(Peripheral Component Interconnect) bridge, and a hardware security block(120) providing the hardware security mechanism and performing bidirectional communication while providing the stability for data and an instruction through a hardware system bus(130). The hardware security block includes a key distribution controller(140), a controller(150), the similar random number generator(160), the exclusive binary operator(170), and the asymmetric encryption module(180).

Description

SECURITY APPARATUS AND METHOD FOR DIGITAL HARDWARE SYSTEM

The present invention relates to an apparatus and method for securing a digital hardware system, and more particularly, to an apparatus and method for providing security of a digital hardware system such as a set-top box or a digital game machine by using an asymmetric key encryption algorithm and an appropriate security mechanism.

Typically, the security of digital hardware systems has been secured based on the security of secret keys, which mainly use hash functions or symmetric key cryptographic algorithms. However, the safety that depends on the secret key and hash function value has the disadvantage that the secret key value is exposed by hardware attack such as eavesdropping of the system bus and the security is easily destroyed.

Such a hardware attack method can be applied to almost any hardware system using a symmetric key cryptographic algorithm.

For example, the next-generation video game console, Xbox, uses a secret key cryptographic algorithm called Rc4 and a hash function value to encrypt the system code associated with booting and starting the game console system to provide game console security. . However, these security mechanisms only detect the secret key value and hack the security code part, allowing attackers to illegally play the desired game. In other words, it can be applied to any Xbox system that uses that secret key value, causing significant economic damage to the Xbox developer.

In addition, most of the set-top boxes that enable the paying of cable TV use a secret key value or a hash function value to authenticate a user. Such a secret key value is easily exposed to hackers by hardware and software attacks, so that the security of the system is improved. It has the problem of being destroyed.

As such, system security technologies include "Computer Systems and Methods with Security Capabilities of Data Stored in Storage Devices," registered 1998-052997 on December 1, 1998, and 266611, registered on June 27, 2000, " Data scrambling circuit "and" multi-data scrambling circuit "registered on June 27, 2000 as 266605.

As described above, the disclosed prior art will be described in detail, "a computer system and method having a security function of data stored in a storage device" means FAT (file allocation table) information of a hard disk each time the computer system is powered off. Is stored in a separate EEPROM, and the FAT information recorded on the hard disk is deleted. After the system is powered on and booted, it checks whether the password and serial number of the hard disk match and restores the FAT information stored in the EEPROM to the hard disk only when they match. Therefore, even if the hard disk is removed and mounted on another computer system, the FAT cannot be restored, so data stored on the hard disk cannot be obtained. As such, since the HDD can be used only in the original computer system storing the FAT information, security of the hard disk information can be maintained.

In order to implement the security mechanism proposed in the present invention, a removable hard disk drive, an EEPROM memory for storing FAT information of the hard disk drive, and FAT information from the hard disk drive when the computer system is powered off. A function for deleting FAT information of the hard disk drive after storing in EEPROM memory means, and a control means for extracting FAT information from EEPROM memory when the computer system is powered on and restoring FAT information to the hard disk drive. Do.

Next, the "data scrambling circuit" uses the output signal of each encryption function block to improve the degree of encryption by using a specific value stored in the storage, and by selectively using each of the output signal with the improved degree of encryption as the final cipher text, Improved random ratio (RANDOM RATE).

Next, when scrambled data encrypted data, the "multi-data scrambling circuit" makes it possible to scramble data by selectively inputting data of different sizes using a multiplexer. The biggest feature of this invention is that it allows the variable length of the conventional scheme to be variably selected to scramble the selected data.

Thus, when looking at the technology disclosed in the prior patent, it can be applied to all Xbox systems that use a secret key value, which causes a significant economic damage to the company that developed the Xbox, secret key value or hash function value In the cable TV that performs the user authentication process, the secret key value is easily exposed to the hacker by hardware and software attacks, and the problem of the security of the system still remains.

Accordingly, the present invention has been made to solve the above-described problems, and its object is to enable fast data encryption and decryption using an exclusive binary operator and a similar random number generator capable of very low hardware complexity and high performance. Digital hardware that provides high security using asymmetric key cryptographic algorithm by cryptographic module and enhances the security of digital hardware system such as set-top box or digital game machine by performing exclusive binary operation based on distributed key value A system security apparatus and method are provided.

In the present invention for achieving the above object, the digital hardware system security apparatus includes a hardware block having a hardware security mechanism, the security target block that is the security target of the CPU or PCI bridge; And a hardware security block that provides a hardware security mechanism and performs bidirectional communication while providing stability to data and instructions over a hardware system bus; The hardware security block includes a key distribution controller having a key distribution protocol structure for distributing keys without exposing secret keys to each other between hardware security blocks providing a security mechanism connected by a hardware system bus; A controller for controlling operations between hardware security block components; Linear Feedback Shift Registe and asymmetric key cryptographic algorithms for clock synchronization of hardware system buses, storing and outputting key values that are safely distributed to one another without exposing their secret keys. Pseudo random number generator; An exclusive binary operator configured to encrypt a high-performance system bus and an input / output bus by performing a modular-2 addition operation on the output value of the pseudorandom number generator and the data passing through the hardware system bus; Asymmetric key cryptographic algorithm based RSA cryptographic algorithm and an elliptic curve cryptographic algorithm using the asymmetric key cryptographic module characterized in that it comprises asymmetric encryption.

In addition, in the present invention for achieving the above object, the digital hardware system security method generates a random number during a booting process in which power is supplied to the hardware security block, and uses an RSA in an asymmetric key encryption module in a hardware security block that uses a random value as a secret key. Generating and distributing a public key value by performing a key distribution protocol through an exponential power operation or an elliptic curve scalar multiplication operation; The distributed key value is stored in a pseudo random number generator in a hardware security block and used as a seed value for generating a pseudo random number; The generated random number is used by data input / output in a security target block such as a CPU or a PCI bridge which is a protection target of the hardware security system, and an exclusive binary operator in the hardware security block; The data computed by the exclusive binary operator is transmitted to the counterpart hardware block through the hardware system bus, and the data is encrypted by the counterpart hardware block.

In addition, in the present invention for achieving the above object, the digital hardware system security apparatus includes a hardware block having a hardware security mechanism is a security target block that is a security target of the CPU or PCI bridge; And a hardware security block that provides a hardware security mechanism and performs bidirectional communication while providing stability to data and instructions over a multiple implemented hardware system bus; The hardware security block includes a key distribution controller having a key distribution protocol structure for distributing keys without exposing secret keys to each other between hardware security blocks providing security mechanisms connected by multiple implemented hardware system buses; A controller for controlling operations between hardware security block components; For clock synchronization of multiple implemented hardware system buses, linearly shifted shift registers and asymmetric key cryptographic algorithms are used to safely distribute key values to the shift registers without exposing their secret keys. A pseudo random number generator for storing and outputting; An exclusive binary operator configured to encrypt a high-performance system bus and an input / output bus by performing a modular-2 addition operation on the output value of the pseudorandom number generator and the data passing through the multiple-implemented hardware system bus; A distributor for bus permutation for selecting which of the multiplexed hardware system buses and which bus to transmit the encrypted data over at a particular time; Asymmetric key cryptographic algorithm based RSA cryptographic algorithm and an elliptic curve cryptographic algorithm using the asymmetric key cryptographic module characterized in that it comprises asymmetric encryption.

1 is a block diagram illustrating a digital hardware system security apparatus according to an embodiment of the present invention.

2 is a flowchart illustrating a method of operating a digital hardware system security apparatus according to the present invention;

3 is a block diagram illustrating a digital hardware system security apparatus according to another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100,200: Security target block 110,210: Hardware block

120220: Hardware Security Block 130230: Hardware System Bus

140,240: key distribution controller 150,250: controller

160,260 pseudo-random number generator 170270 exclusive binary operator

180,290: Asymmetric Key Cryptographic Module 280: Splitter for Bus Emulation

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a digital hardware system security apparatus according to an embodiment of the present invention, which includes a hardware block 110 having a hardware security mechanism connected through a hardware system bus 130.

The hardware block 110 having a hardware security mechanism includes a security target block 100 that is a security target, such as a CPU or a PCI bridge, and a hardware security block 120 that provides a hardware security mechanism, and provides a dual hardware security mechanism. The hardware security block 120 internally includes a key distribution controller 140, a controller 150, a pseudorandom number generator 160, an exclusive binary operator 170 for bus encryption, and an asymmetric key cryptographic module 180. Has

The security target block 100 may be a CPU, an input / output bus controller such as a PCI bridge, a PCI interface controller, and a memory bus input / output controller.

The hardware security block 120 is a block implemented in hardware such as a CPU or an input / output bus controller, a system bus controller, and the like, and performs bidirectional communication while providing stability to data and instructions through the hardware system bus 130. Here, when hardware hacking such as physical detection and eavesdropping is performed on the hardware system bus 130, the traffic data communicated in both directions is encrypted or permutated. In this case, the important thing is to be able to provide safety without degrading the bus speed, and be configured to easily solve the synchronization problem between each node connected to the hardware system bus 130.

The key distribution controller 140 in the hardware security block 120 can distribute the keys without exposing the secret keys to each other between the hardware security blocks 120 that provide the security mechanisms connected by the hardware system bus 130. Has a programmable structure as a controller block. That is, it enables to perform various key distribution protocols. At this time, the Diffie Hellman key distribution protocol, which is the most common key distribution protocol using the asymmetric key cryptographic module 180, intercepts a key in the middle of the bus and provides an appropriate key value for each of them. Since a method exists, the key distribution controller 140 is implemented, which is a secure Diffie Hellman key distribution protocol.

The controller 150 in the hardware security block 120 controls the operation between the components of the hardware security block 120.

The pseudo-random number generator 160 in the hardware security block 120 is a block configured using a linear feedback shift register (LFSR), and does not expose its secret key using an asymmetric key cryptographic algorithm. The key values securely distributed from each other are stored in the shift register of the pseudorandom number generator, and then operate in synchronization with the clock of the hardware system bus 130.

The exclusive binary operator 170 in the hardware security block 120 performs a modular-2 addition operation on the output value of the pseudo random number generator 160 and the data passing through the hardware system bus 130. This enables very fast operation to encrypt high-performance system buses and I / O buses from hundreds of Mbps up to Gbps.

The asymmetric key cryptographic module 180 in the hardware security block 120 is a block that enables asymmetric key cryptographic algorithms such as RSA and elliptic curve cryptography to be performed at high speed. Because of the high hardware complexity and low-speed operation of the RSA cryptographic algorithm, the multiplier-based Montgomery algorithm is used in consideration of performance characteristics and hardware complexity. On the other hand, when the elliptic curve cryptographic algorithm is used, the elliptic curve cryptographic algorithm has a smaller hardware complexity and higher performance than the RSA, and thus can be suitably used in a hardware security system.

Referring to the flowchart of FIG. 2, the operation of the digital hardware system security apparatus according to the present invention will be described in detail based on the above-described configuration.

First, the hardware security block 120 that provides the hardware security mechanism of FIG. 1 generates a random number internally, that is, a booting process (step 201), and uses an asymmetric key that uses the generated random number as a secret key. The cryptographic module 180 performs a key distribution protocol through an RSA exponential power operation or an elliptic curve scalar multiplication operation. That is, the key values generated during the boot process are used in the asymmetric key cryptographic module 180 in the two hardware security blocks 120 to generate a public key value (step 202).

Once generated, the public key values are transferred to the other hardware block 110 through a hardware system bus 130 such as an input / output bus or a memory bus, where the key distribution operation is performed by the key distribution controller 140. Is performed (step 203), and the operation between the necessary hardware security block 120 components is controlled by the controller 150.

On the other hand, even if the hardware attacker intercepts the public key value transmitted through the hardware system bus 130, since it is already encrypted by the asymmetric key cryptographic module 180, it is exponential power to interpret it in case of RSA Since it solves a computational problem and an elliptic curve cryptographic algorithm, it solves a discrete logarithmic problem and thus cannot be decrypted.

Here, the key distribution protocol uses a simple Diffie Hellman key distribution protocol, but since the key distribution controller 140 is programmable, a more secure key distribution protocol may be used.

The key value distributed by the key distribution controller 140 is stored in the pseudo random number generator 160 in the hardware security block 120 (step 204) and used as a seed value for generating the pseudo random number (step 205). ). Here, the register constituting the pseudo-random number generator 160 is an optical hardware attack method, but de-capping and the value is a physical hardware attack to prevent the seed key value to be found, chip Implementations should protect using appropriate hardware prevention techniques.

In addition, the random number value generated every clock is calculated by the exclusive binary operator 170 and the data input and output from the security target block 100 such as a CPU or a PCI bridge which is a protection target of the hardware security system (step 206). That is, the data calculated by the exclusive binary operator 170 is transmitted to the counterpart hardware block 110 via the hardware system bus 130 (step 207), and the counterpart hardware block 110 is exclusive to the encrypted data. Decoding by performing the binary operation once more (step 208).

3 is a block diagram of a digital hardware system security apparatus according to another embodiment of the present invention, which includes a hardware block 210 having a hardware security mechanism connected through a hardware system bus 230.

The hardware block 210 having a hardware security mechanism includes a security target block 200 to be secured, such as a CPU or a PCI bridge, and a hardware security block 220 that provides a hardware security mechanism, and provides a dual hardware security mechanism. The hardware security block 220 internally includes a key distribution controller 240, a controller 250, a pseudorandom number generator 260, an exclusive binary operator 270 for bus encryption, and bus permutation. Has a distributor 280 and an asymmetric key cryptographic module 180.

In comparison with the apparatus of FIG. 1 described above, a divider 280 for bus emulation is added, and the hardware system bus 230 is implemented in multiples.

That is, by constructing multiple hardware system buses 230 through which data is transmitted, and arbitrarily selecting by the distributor 280 for bus emulation which time to transmit encrypted data over which bus, external attackers Even if a physical detection of the bus was made, it would be more impossible to decipher it.

In addition, detecting a physically large number of hardware system bus 230 lines is more practically difficult than detecting a smaller number of buses, especially when implementing bus lines on a PCB substrate, with different layers. By implementing the layout, detection of the hardware system bus 230 is more impossible.

On the other hand, the counterpart hardware security block 220 should know exactly which bus is selected from the hardware system bus 230 and which bus is encrypted data transmitted at a specific time.

That is, the divider 280 for bus emulation may be implemented using a multiplexer and a demultiplexer, and the hardware system bus 230 line selection may be implemented by combining specific bit values of the pseudo random number generator. For example, the hardware system bus 230 line may be selected using a specific lower bit value, and the hardware system bus 230 line may be selected by combining specific bit values.

At this time, the security is the same as the safety of the pseudo-random number generator 260 is secure, the synchronization with the distributor 280 for the bus bus counterpart synchronization is a key value shared by the key distribution protocol provided by the key distribution controller 240 Synchronized by, it is easy to implement.

In other words, the same random key value is generated in the pseudo-random number generator 260 in each hardware security module 220 at a specific point in time, and by this value, by the selection of the distributor 280 for bus emulation, Encrypted data is transmitted over a particular bus line at a particular time on hardware system bus 230.

From the receiving side, since the pseudo-random number generator 260 of the receiving hardware security module 220 also has the same random key value at the same clock time, an appropriate bus line is selected by the distributor so that the data to be received can be precisely selected. After receiving the decrypted data, it transmits to the security target block 220.

As described above, the present invention enables high-speed data encryption and decryption using an exclusive binary operator and a similar random number generator capable of very low hardware complexity and a high performance, and high using an asymmetric key encryption algorithm by an asymmetric key encryption module. It provides security and provides high speed and security by performing exclusive binary operations based on distributed key values.

In addition, the digital hardware system security apparatus according to the present invention encrypts the underlying system bus at high speed so that protocol information, security related information, and secret key values are not exposed from illegal attacks by hardware hackers.

In addition, when a hardware attacker illegally changes the system software including an authentication procedure, the hardware attacker detects the illegal information and confirms the theft. Finally, the hardware system security mechanism proposed in the present invention has an effect that can be applied to various systems in which user authentication and security are important, that is, digital game machines, PDAs, set-top boxes, and IC cards.

Claims (11)

A digital hardware system security device, A hardware block with a hardware security mechanism A security target block that is a security target of the CPU or PCI bridge; And Providing a hardware security mechanism, comprising a hardware security block for performing bidirectional communication while providing stability for data and instructions over a hardware system bus; The hardware security block includes: A key distribution controller having a key distribution protocol structure for distributing keys without exposing secret keys to each other between hardware security blocks providing security mechanisms connected by the hardware system bus; A controller for controlling the operation between the hardware security block components; Store and output key values securely distributed to one another without exposing their secret keys using a Linear Feedback Shift Registe and an asymmetric key cryptographic algorithm for clock synchronization of the hardware system bus. A pseudo-random number generator; An exclusive binary operator configured to encrypt a high performance system bus and an input / output bus by performing a modular-2 addition operation on the output value of the pseudorandom number generator and the data passing through a hardware system bus; And an asymmetric key cryptographic module for encrypting asymmetrically using the asymmetric key cryptographic algorithm-based RSA cryptographic algorithm and an elliptic curve cryptographic algorithm. The method of claim 1, When hardware hacking is performed on the hardware system bus, the traffic data communicated in both directions is encrypted or permutated. Even if a hacker eavesdrops on it, the contents of the data are not known and the safety is achieved without degrading the bus speed. And provide a solution for resolving synchronization between nodes connected to the hardware system bus. The method of claim 1, Since the Diffie Hellman key distribution protocol, which is a key distribution protocol using the asymmetric key cryptographic module, intercepts a key in the middle of the bus and provides an appropriate key value for each of them, the method exists to attack. Digital hardware system security device, characterized in that implemented in the key distribution controller to prevent this. The method of claim 1, In the case of using the RSA encryption algorithm, a multiplier-based Montgomery algorithm is used in consideration of the performance characteristics and the hardware complexity due to the high hardware complexity and the low-speed operating characteristics, and in the case of using the elliptic curve encryption algorithm, A digital hardware system security device characterized by its complexity and high performance that makes it suitable for use in hardware security systems. A security method in a digital hardware system having a security target block and a hardware security block, A key distribution protocol is generated through an RSA exponential multiplication or an elliptic curve scalar multiplication operation in an asymmetric key cryptographic module in the hardware security block that generates a random number in the booting process when power is supplied to the hardware security block and uses the random number as a secret key. Performing and generating and distributing a public key value; The distributed key value is stored in a pseudo random number generator in a hardware security block and used as a seed value for generating a pseudo random number; The generated random number value is used by data inputted and outputted from a security target block such as a CPU or a PCI bridge which is a protection target of a hardware security system, and an exclusive binary calculator in the hardware security block; And the data calculated by the exclusive binary operator is transmitted to a counterpart hardware block through a hardware system bus, and performing an exclusive binary operation once more on the encrypted data in the counterpart hardware block to decrypt the data. How to secure your digital hardware system. The method of claim 5, wherein The key distribution protocol uses a Diffie Hellman key distribution protocol, but since the key distribution controller in the hardware security block is programmable, a more secure key distribution protocol may be used. . The method of claim 5, wherein Registers constituting the pseudo random number generator are optical hardware attack methods, but de-capping and values are physical hardware attacks to prevent seed key values from being found. A method of securing a digital hardware system, characterized in that it must be protected using prevention techniques. A digital hardware system security device, A hardware block with a hardware security mechanism A security target block that is a security target of the CPU or PCI bridge; And Providing a hardware security mechanism, comprising a hardware security block for performing bidirectional communication while providing stability to data and instructions over a multiple implemented hardware system bus; The hardware security block includes: A key distribution controller having a key distribution protocol structure for distributing keys without exposing secret keys to each other between hardware security blocks providing security mechanisms connected by the multiple implemented hardware system buses; A controller for controlling the operation between the hardware security block components; Shift registers are securely distributed to each other without exposing their secret keys using a linear feedback shift register and an asymmetric key cryptographic algorithm for clock synchronization of the multiplely implemented hardware system bus. A pseudo-random number generator for storing and outputting the result; An exclusive binary operator configured to encrypt a high-performance system bus and an input / output bus by performing a modular-2 addition operation on the output value of the pseudo-random number generator and the data passing through the multiplely implemented hardware system bus; A divider for bus permutation that selects which bus of said multiplely implemented hardware system buses to select and which bus to transmit at a particular time; And an asymmetric key cryptographic module for encrypting asymmetrically using the asymmetric key cryptographic algorithm-based RSA cryptographic algorithm and an elliptic curve cryptographic algorithm. The method of claim 8, The divider for the bus emulation can be implemented using a multiplexer and a demultiplexer, and the multiplexing hardware system bus line selection is implemented by combining specific bit values of the pseudo random number generator. Device. The method of claim 8, And the synchronizing of the distributor for the bus emulation with the distributor for the opposing bus emulation is synchronized by a key value shared by a key distribution protocol provided by the key distribution controller. The method of claim 10, The same random key value is generated in the pseudo-random number generator in the hardware security module, selection control of the distributor for bus emulation is performed by the generated value, and the encrypted data is transmitted through the selected bus line. Digital hardware system security device.