KR20060110383A - Multi-mode ciphering apparatus for network security processor - Google Patents

Abstract

A multi-mode encryption apparatus for a network security processor is provided to reduce waiting time of a symmetric key encryption algorithm by realizing a plurality of encryption algorithms and hash functions with hardware and operating in a multi-mode. In a multi-mode encryption apparatus for a network security processor, a control unit(210) properly operates a multi-mode by determining overall operation for the data pass of an encryption block. Input and output units(401,402,415) perform functions of network environment and an interface. A register and a counter(403) store an initial vector. A cipher(408) has a plurality of block encryption algorithms, and performs encryption by using the block encryption algorithms selectively.

Description

MULTI-MODE CIPHERING APPARATUS FOR NETWORK SECURITY PROCESSOR}

Figure 1 (a) is an illustration of the original image.

Figure 1 (b) is an illustration of a partially encrypted image.

1C is an exemplary view of an image having a watermark embedded therein.

1D is an exemplary diagram of a watermark extracted after image modulation.

2 is a block diagram of a multi-bit AES data path in accordance with the present invention.

3A is a block diagram of a single-DES data path in accordance with the present invention.

3B is a block diagram of a multiple-DES data path in accordance with the present invention.

4 is a block diagram of a data path of a mode operation encryption block according to the present invention;

5 is a table of encryption / decryption operation modes according to the present invention.

6A is a block diagram of a data path of MD-5.

6B is a block diagram of a data path of HAS-160.

6C is a block diagram of a data path of an SHA.

*** Description of the symbols for the main parts of the drawings ***

210: control unit 401,402: input unit

403: Registers and Counters 404,406,412,414: Multiplexer

405,413: Adder 407: Input buffer

408: cypher 409: output buffer

410,411: Storage 415: Output

The present invention relates to encryption technology for protection and security of information, and in particular, a network security for operating in multiple modes by implementing a plurality of encryption algorithms and hash functions in hardware to be compatible with network protocols. A multimode cryptographic apparatus of a processor.

In recent years, as communication technologies are developed, interconnection between different computers via wired / wireless communication is more frequent, and as the capacity of video / video data is reduced by compression technology, the exchange of these data becomes more active.

Therefore, access rights and protection of personal information such as ID cards and X-ray files, paid information for the purpose of business profits such as video / video contents, and secret information of public institutions have emerged as important matters. Accordingly, cryptographic techniques for security in the form of transmission and storage, including information protection, are being used more than ever.

In general, encryption algorithms can be broadly classified into public key algorithms, symmetric key algorithms, and hash functions. In addition, chaos system is also used as a means of encryption, but it is vulnerable to brute-force attack by outputting cipher data having a certain pattern, thereby limiting the scope of application.

By the way, in the conventional encryption technology, there is a problem that it takes a lot of waiting time delay and calculation time, and there is a problem such as incompatibility with the existing information protection device or security device.

Accordingly, an object of the present invention is to provide a cryptographic apparatus that introduces a symmetric key encryption algorithm and operates in multiple modes for high strength encryption.

According to the first aspect of the present invention, the waiting time of the symmetric key encryption algorithm is reduced and the operation speed is improved.

According to the second aspect of the present invention, two encryption / decryption algorithms and three hash functions are embedded in the encryption device in order to maintain compatibility with various encryption and hash algorithms used between information protection devices / security devices.

According to a third aspect of the present invention, an encryption / decryption operation mode is applied to maximize the performance of an existing information protection / security algorithm.

According to the fourth aspect of the present invention, the hardware is made into a database such as AltL (RTL), Gate Level Netlist, GDS, etc. so that the hardware can be applied to various fields by IP.

According to the fifth aspect of the present invention, information security / security strength is freely adjusted by allowing the selection of keys of various lengths.

An encryption apparatus of a multimode network according to the present invention includes a control unit for determining an overall operation of a data path of an encryption / decryption block so that the multimode is properly operated; An input / output unit that performs a network environment and an interface function; Registers and counters for storing initial vectors; A plurality of block encryption and block decryption algorithms are provided, and a cipher is used for selectively encrypting and decrypting the same.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is an exemplary embodiment of a data path of an encryption / decryption block in an encryption apparatus of a multimode network according to the present invention. As shown in FIG. A controller 210 for operating the mode properly; An input unit 410, 402 and an output unit 415 which perform network function and interface functions; A register and counter 403 for storing an initial vector; A cipher 408 for performing encryption by selectively using a plurality of block encryption and block decryption algorithms (AES, 3DES); It consists of multiplexers 404, 406, 412, 414, and storage 410, 411 for data selection and timing adjustment for block encryption. When described in detail with reference to Figures 1 to 3, 5 and 6 as follows.

The symmetric key encryption algorithm implemented in the present invention is also referred to as a block cipher algorithm, which encrypts and decrypts data of a certain unit block with the same key, and operates an operation mode in multiple modes for high encryption.

Representative examples of the block encryption algorithm include AES (Avance Encryption Standard), 3DES (Data Encryption Standard), SEED (Korean Data Encryption Standard), and the like. This block encryption algorithm has a disadvantage of requiring a constant data latency time and requiring a lot of computation time, but has an advantage of high encryption strength. In addition, the hash function is commonly used for video media such as digital TVs (DTVs) and cameras for information integrity authentication and watermarking, and examples thereof include MD5, SHA, and HAS-160.

For reference, (a) of FIG. 1 shows an original image, (b) shows a partially encrypted image, (c) shows an image with a watermark embedded therein, and (d) shows after image modulation. It shows the extracted watermark.

The encryption apparatus according to the present invention largely comprises a data path unit and a control unit. FIG. 2 shows a data path of a multi-bit AES according to the present invention.

The data path unit is a look-up table implemented by round key generators 222 and 223 corresponding to a key scheduler, key registers and modulo ROMs installed therein. (Mod LUT), (Inv LUT) and cyphers. In addition, the controller 210 includes a key scheduler controller and a sipher controller as a whole controller.

Hardware for encryption and decryption is designed to be integrated structure by sharing hardware, and all parts corresponding to modulo operation of nonlinear function are designed using lookup table (eg Mod LUT, Inv LUT) for high speed operation. This made it possible.

In addition, the AES implemented by the present invention is designed to accommodate all key lengths of 128, 192, and 256 bits, and it is possible to easily change the operation mode by programming depending on the situation.

Meanwhile, the block encryption algorithms DES and 3DES applied to the present invention will be described with reference to FIGS. 3A and 3B.

The 3DES is implemented by adding a multiplexer 316, which is a module for multiple-DES, and a 3DES controller 317 as shown in FIG. 3B after implementing single-DES as shown in FIG. 3A.

In the case of DES as shown in FIG. 3A, encryption and decryption are implemented by performing 16 rounds using a relatively simple algorithm having a Feistal structure.

The functions of 2DES and 3DES can be implemented by repeatedly driving a single DES as shown in FIG. 3A. In this case, as shown in FIG. 3B, the 3DES controller 317 controls various operations of the DES according to programming.

Meanwhile, the overall operation of the encryption apparatus according to the present invention will be described with reference to FIGS. 4 and 5.

4 shows a data path of an encryption / decryption block according to the present invention. Here, the cipher 408 performs encryption and decryption, and the input units 410 and 402 and the output unit 415 perform a network environment and an interface function. In addition, the register and counter (IV / Counter) 403 stores the initial vector, and the controller 210 determines the overall operation of the data path of the encryption / decryption block so that the multi-mode operates properly. In addition, the multiplexers 404, 406, 412, 414, and storage 410, 411 are used for block encryption.

The block encryption algorithm according to the present invention is implemented as a world standard block encryption algorithm such as AES, 3DES, etc., and has a virtual cipher for testing input / output operations.

In the basic operation mode of the hardware of such a structure, the minimum latency (for example, minimum 128 clocks and maximum 256 clocks) is allowed for data input through wired / wireless networks and the like, and data is encrypted or decrypted in real time.

In addition, it supports all block encryption modes (e.g. ECB, CBC, CFB, OFB) and supports the most recently used CTR (Counter) mode while simultaneously encrypting multiple bit units (e.g. 64, 128, 192, 256bit). / Decrypt

Implemented by hardware with algorithm extension function to link to network security protocol (eg IPsec), maximize the efficiency of hardware through simultaneous operation of several encryption algorithms, where network encryption mode and direct encryption mode are used simultaneously do.

A variety of ways of encryption / decryption are possible because the hardware can support its own block encryption mode using the proper sharing of hardware and programmable internal data paths.

The overall encryption operation is determined by a control signal programmed by serial communication and generated through the decoding of the instruction, the operation mode of which is shown in FIG.

That is, whether to perform encryption is determined by the control signal output from the controller 210, the encryption mode is determined as encryption or decryption, the operation mode is determined as the network encryption mode or direct encryption mode, and the block encryption algorithm is Selected as AES or 3DES or Virtual Cipher, supported among block encryption modes (e.g. ECB, CBC, CFB, OFB), AES key length selected from 128,192,256, DES mode double It is selected as DES or single DES or triple DES.

Of course, the respective selection control signals SEL1, SEL2, and SEL3 are provided to the multiplexers 406, 414, 404, 412 in the respective modes.

6A, 6B, and 6C show the data paths of the hash functions MD-5, HAS-160, and SHA, respectively. These hash functions are divided into registers, arithmetic unit, padding unit, and control unit that store input information. Is done.

Padding of I / O data is very important and requires a complicated operation, but the amount of computation is not so large, so it is processed by software.

In consideration of the fact that the calculation time is determined according to the byte addressing of the data required for the calculation, a predetermined look up table (LUT) is used during addressing.

For example, in the MD-5 data path of FIG. 6A, a lookup table was constructed on an abs-ROM 604 instead of then computing the addressing order and then addressed using this. The address signal generated in this way is summed by the adder 605 and the data input through the permutation (P) 601, the multiplexer 602, and the register 603.

As another example, in the data path of the HAS-160 of FIG. 6B, the address generator 632 was constructed as a lookup table on a ROM, and used to generate the required address.

In the drawings, the computing unit is implemented as a combination, for example. In addition, it can be seen that the structure is designed to share each data register in order to minimize the footprint of the hardware.

As described in detail above, the present invention implements a plurality of encryption algorithms and hash functions in hardware and operates in a multimode mode, thereby reducing the waiting time of the symmetric key encryption algorithm and improving the operation speed, encryption performance, and compatibility. .

In addition, by converting the hardware into a database by RTL, gate level netlist, GDS, etc., there is an effect that can be applied to various fields.

In addition, it is possible to select a key of various lengths has the effect of freely adjusting the information protection / security strength.

Claims (12)

A control unit for determining the overall operation of the data path of the encryption block so that the multi-mode is properly operated; An input / output unit that performs a network environment and an interface function; Registers and counters for storing initial vectors; And a cipher including a plurality of block encryption algorithms and selectively using the plurality of block encryption algorithms. The apparatus of claim 1, wherein the controller is configured to output a control signal programmed by serial communication and generated through decoding of the command. The method of claim 1, wherein the controller determines a control signal for determining whether to perform encryption, a control signal for determining an encryption mode or a decryption mode, a control signal for determining a network encryption mode or a direct encryption mode, and a block encryption algorithm. And a control signal for supporting the corresponding mode among the block encryption mode, the control signal for selecting the AES key length, and the control signal for selecting the DES mode. Multimode cryptographic device in a network security processor. 4. The apparatus of claim 3, wherein the block encryption algorithm is one of AES, 3DES or virtual cipher. 5. The apparatus of claim 4, wherein all of the portions corresponding to the modulo operation of the nonlinear function in the data path of the block encryption algorithm AES are composed of lookup tables. 5. The apparatus of claim 4, wherein the block encryption algorithm 3DES is configured by adding a multiplexer which is a module for multiple-DES after implementing single-DES, and a 3DES controller. 4. The apparatus of claim 3, wherein the block encryption mode is any one of ECB, CBC, CFB, and OFB. 4. The apparatus of claim 3, wherein the AES key length is any one of 128, 192, and 256 bits. 4. The apparatus of claim 3, wherein the DES mode is any one of double DES, single DES, and triple DES. The apparatus of claim 1, further comprising two stages of storage for timing adjustment when performing encryption through a cipher. The apparatus of claim 1, wherein the data path of the hash function (MD-5) applied to the block encryption algorithm is configured to address by constructing a lookup table on a ROM. The apparatus of claim 1, wherein the data path of the hash function (HAS-160) applied to the block encryption algorithm is configured to generate a required address by building a lookup table on the ROM.

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