KR20040051523A - 미세 패턴의 형성 방법, 및 반도체 장치의 제조 방법 - Google Patents

미세 패턴의 형성 방법, 및 반도체 장치의 제조 방법 Download PDF

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Publication number
KR20040051523A
KR20040051523A KR1020030089318A KR20030089318A KR20040051523A KR 20040051523 A KR20040051523 A KR 20040051523A KR 1020030089318 A KR1020030089318 A KR 1020030089318A KR 20030089318 A KR20030089318 A KR 20030089318A KR 20040051523 A KR20040051523 A KR 20040051523A
Authority
KR
South Korea
Prior art keywords
fluorine resin
fine pattern
ultraviolet light
resin resist
resist
Prior art date
Application number
KR1020030089318A
Other languages
English (en)
Korean (ko)
Inventor
야마자끼다미오
Original Assignee
가부시끼가이샤 한도따이 센단 테크놀로지스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 한도따이 센단 테크놀로지스 filed Critical 가부시끼가이샤 한도따이 센단 테크놀로지스
Publication of KR20040051523A publication Critical patent/KR20040051523A/ko

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70008Production of exposure light, i.e. light sources
    • G03F7/70016Production of exposure light, i.e. light sources by discharge lamps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
KR1020030089318A 2002-12-11 2003-12-10 미세 패턴의 형성 방법, 및 반도체 장치의 제조 방법 KR20040051523A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2002-00359935 2002-12-11
JP2002359935A JP3627187B2 (ja) 2002-12-11 2002-12-11 微細パターンの形成方法、及び半導体装置の製造方法

Publications (1)

Publication Number Publication Date
KR20040051523A true KR20040051523A (ko) 2004-06-18

Family

ID=32759187

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030089318A KR20040051523A (ko) 2002-12-11 2003-12-10 미세 패턴의 형성 방법, 및 반도체 장치의 제조 방법

Country Status (2)

Country Link
JP (1) JP3627187B2 (ja)
KR (1) KR20040051523A (ja)

Also Published As

Publication number Publication date
JP2004193367A (ja) 2004-07-08
JP3627187B2 (ja) 2005-03-09

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WITN Withdrawal due to no request for examination