KR20040051073A - Array substrate for LCD and Method for fabricating of the same - Google Patents

Abstract

PURPOSE: An array substrate of an LCD(Liquid Crystal Display) and a method for fabricating the array substrate are provided to block light leakage generated at the marginal region of a substrate. CONSTITUTION: An array substrate of an LCD includes a gate line(102) formed on a substrate(100) in one direction, a gate link line(104) and a gate pad(106) connected to the gate line, a data line(110) intersecting the gate line to define a pixel region, a data link line and a data pad connected to the data line. The array substrate further includes a thin film transistor(T), a black matrix(122), a color filter(120a,120b,120c), and a shielding pattern(126). The thin film transistor is disposed at the intersection of the gate line and the data line and includes a gate electrode(112), an active layer(114), and source and drain electrodes(116,118). The black matrix is formed on the thin film transistor. The color filter is connected to the black matrix and located at the pixel region. The shielding pattern is formed corresponding to the gate link line and the data link line.

Description

Array substrate for LCD and its manufacturing method {Array substrate for LCD and Method for fabricating of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device having a color filter on TFT (COT) structure constituting a color filter on the thin film transistor array unit, and a manufacturing method thereof.

In general, a liquid crystal display device displays an image by using optical anisotropy and birefringence characteristics of liquid crystal molecules. When an electric field is applied, the alignment of liquid crystals is changed, and the characteristics of light transmission vary according to the arrangement direction of the changed liquid crystals.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by the electric field is a device that represents the image by the transmittance of light that varies accordingly.

1 is a view schematically showing a general liquid crystal display device.

As shown, a general color liquid crystal display 11 includes a color filter 7 and a color filter 7 including a black matrix 6 formed between a sub color filter 8 and each sub color filter 8. The upper substrate 5 having the common electrode 18 deposited thereon, the pixel region P, and the pixel electrode 17 and the switching element T formed in the pixel region, and the pixel region P The liquid crystal 14 is filled between the lower substrate 22 and the upper substrate 5 and the lower substrate 22 on which array wiring is formed.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 crosses the plurality of thin film transistors TFT. ) And data wirings 15 are formed.

In this case, the pixel area P is an area defined by the gate wiring 13 and the data wiring 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area P as described above.

The pixel electrode 17 uses a transparent conductive metal having a relatively high transmittance of light, such as indium-tin-oxide (ITO).

A storage capacitor C connected in parallel with the pixel electrode 17 is formed on the gate wiring 13, and a part of the gate wiring 13 is used as the first electrode of the storage capacitor C, and a second As the electrode, an island-like metal layer 30 formed of the same material as the source and drain electrodes is used.

In this case, the island-shaped metal layer 30 is configured to be in contact with the pixel electrode 17 to receive a signal of the pixel electrode.

As described above, when the upper color filter substrate 5 and the lower array substrate 22 are bonded to each other to produce a liquid crystal panel, light leakage defects due to the bonding error between the color filter substrate 5 and the array substrate 22 may be reduced. It is very likely to occur.

A description with reference to FIG. 2 is as follows.

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1.

As described above, the first substrate 22, which is an array substrate, and the second substrate 5, which is a color filter substrate, are spaced apart from each other, and the liquid crystal layer 14 is disposed between the first and second substrates 22, 5. This is located.

The thin film transistor T including the gate electrode 32, the active layer 34, the source electrode 36, and the drain electrode 38 is disposed on the array substrate 22, and the thin film transistor T is disposed on the thin film transistor T. A protective film 40 is configured to protect it.

In the pixel region P, a transparent pixel electrode 17 is formed in contact with the drain electrode 38 of the thin film transistor T. A storage capacitor C connected in parallel with the pixel electrode 17 includes a gate line 13. It is configured on the top.

The upper substrate 5 includes a black matrix 6 corresponding to the gate wiring 13, the data wiring 15, and the thin film transistor T, and corresponds to the pixel region P of the lower substrate 22. Thus, color filters 7a, 7b, and 7c are formed.

In this case, the general array substrate is configured such that the data line 15 and the pixel electrode 17 are spaced apart by a predetermined distance A to prevent vertical cross talk, and the gate line 13 and the pixel electrode are spaced apart from each other. In addition, a predetermined interval (B) is configured to be spaced apart.

Since the spaces A and B spaced apart between the data line 15 and the gate line 13 and the pixel electrode 17 are regions where light leakage occurs, a black matrix formed on the upper color filter substrate 5 matrix) (6) will cover this part.

In addition, the black matrix 6 formed on the thin film transistor T serves to block the light so that the light radiated from the outside does not affect the active layer 34 through the passivation layer 40. .

However, a misalignment may occur during the process of bonding the upper substrate 5 and the lower substrate 22. In view of this, a margin of a constant value is determined when designing the black matrix 6. Since the design is carried out with reference to), the aperture ratio decreases by that amount.

In addition, in the case where the bonding error beyond the margin occurs, there is often a case of light leakage defects in which the light leakage regions A and B are not covered by the black matrix 6.

In this case, since the light leakage appears to the outside, there is a problem of degrading the image quality.

In order to solve the problems as described above, a structure for configuring the color filter and the black matrix on the lower substrate has been proposed, the configuration of the array substrate having such a structure will be described with reference to FIG.

3 is a plan view schematically illustrating a part of an array substrate for a liquid crystal display device having a COT structure according to a second embodiment of the present invention.

As shown in the drawing, a gate line 52 including a gate link line 54 and a gate pad 56 connected thereto is formed in parallel to each other and extends in one direction on the substrate 50, and the gate A plurality of pixel regions P are defined to cross the wiring 52 perpendicularly, and at one end, a data line 58 including a data link line (not shown) and a data pad (not shown) connected thereto is formed. (Hereinafter, description of the data pad section is omitted for convenience.)

In this case, an island-shaped gate pad terminal 53 is separately formed in the gate pad 56. The part is connected to an external driving circuit and serves to directly receive a signal from the driving circuit.

The thin film transistor T including the gate electrode 60, the active layer 62, and the source and drain electrodes 64 and 66 is formed at the point where the gate wiring 52 and the data wiring 58 cross each other. (The black matrix corresponding to the thin film transistor whose symbol is indicated for convenience is not displayed.)

A transparent pixel electrode 68 is formed in the pixel region P defined by the crossing of the two wires 52 and 58.

In the above-described configuration, a black matrix 70 is formed on the thin film transistor T, the gate wiring 52, and the data wiring 58, and each pixel region (above the pixel electrode 68). In each of P), the red, green, and blue color filters 72a, 72b, and 72c are sequentially formed.

The configuration as described above is a planar configuration of an array substrate for a liquid crystal display device having a general COT structure.

In the above-described configuration, the gate link line 54 and the gate pad 56 belong to the non-display area E, and conventionally, the non-display area E and the display area (thin film transistor array area) C Light leakage was observed in the boundary region (D) of

Hereinafter, the shape of the liquid crystal display device corresponding to the outer region of the array substrate constructed as described above will be described with reference to FIG. 4.

FIG. 4 is an enlarged cross-sectional view of the conventional COT structure liquid crystal display device cut along the line IV-IV ′ of FIG. 3 and configured as a reference.

As illustrated, the liquid crystal display device 90 having the COT structure is formed by attaching the first substrate 50 and the second substrate 92 by the sealant 94 to the outside of the sealant 94. 52 and the gate pad terminal 53 in contact therewith are exposed.

Polarizing plates 96a and 96b having polarization axes perpendicularly intersect each other to the outside of the first and second substrates 50 and 92 are formed to surround the first and second substrates 50 and 92. The top cover 98 is located.

In this case, although not shown in the first substrate 50, a thin film transistor array unit (not shown) and color filters 72a, 72b, 72c and a black matrix 70 are formed on the first substrate 50, and the second substrate 92 is formed. The transparent common electrode 99 is configured.

In the above-described configuration, conventionally, fine light leakage occurs in the boundary area D between the display area C and the non-display area E of the liquid crystal panel 90, resulting in a problem of deterioration in image quality.

The present invention has been proposed to solve the above-described problems, and in the present invention, in order to block light leakage generated in the outer region of the substrate, a region in which a gate link line connecting the gate pad and the gate wiring is formed is provided. Form a blocking pattern.

In addition, since the area where the link line passes is an area where a sealant for bonding the upper substrate and the lower substrate is printed, an inorganic insulating film is further formed on the blocking pattern to improve the contact characteristics of the printed sealant.

As described above, since the light leakage phenomenon of the liquid crystal display device can be prevented, the liquid crystal display device of high quality can be manufactured.

1 is an enlarged view schematically illustrating a general liquid crystal display device;

FIG. 2 is a cross-sectional view of the liquid crystal display device cut along the line II-II ′ of FIG.

3 is a plan view schematically showing the structure of a conventional array substrate for a liquid crystal display device having a COT structure;

4 is a cross-sectional view of a liquid crystal display device having a COT structure cut along the line IV-IV` of FIG.

5 is a plan view schematically showing the configuration of an array substrate for a liquid crystal display device having a COT structure according to a first embodiment of the present invention;

6A to 6B are cross-sectional views according to first and second examples of a cross section taken along VI-VI ′ of FIG. 5;

7 is a plan view schematically showing the configuration of an array substrate for a liquid crystal display device having a COT structure according to a second embodiment of the present invention;

8, 9, and 10 are cross-sectional views taken along the first, second, and third examples of cross sections taken along the line VII-VII of FIG. 7,

11, 12, and 13 are cross-sectional views taken along the first, second, and third examples of cross sections taken along the line VII-VII ′ of FIG. 7.

<Brief description of the main parts of the drawing>

100: substrate 102: gate wiring

104: gate link line 106: gate pad

108: gate pad terminal 110: data wiring;

112: gate electrode 114: active layer

116: source electrode 118: drain electrode

120a, 120b, 120c: Color Filter

122: black matrix 124: pixel electrode

126: blocking pattern

According to an aspect of the present invention, there is provided an array substrate for a liquid crystal display device comprising: a gate line formed in one direction on a substrate, a gate link line and a gate pad connected thereto; A data link line and a data pad defining a pixel area crossing the gate line perpendicularly to the gate line, and connected at one end thereof; A thin film transistor positioned at the intersection of the gate line and the data line, the thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; A black matrix formed on the thin film transistor; A color filter connected to the thin film transistor and positioned in the pixel area; And a blocking pattern configured to correspond to the gate link line and the data link line.

An inorganic insulating film is further formed between the black matrix and the thin film transistor.

The blocking pattern may be patterned corresponding to each spaced area of the gate link line and the data link line.

The sealant pattern, which is an adhesive, is further configured on the blocking pattern.

The sealant pattern is configured to be in direct contact with the gate and data link lines.

The pixel electrode is composed of a double layer with the color filter interposed therebetween.

According to another aspect of the present invention, an array substrate for a liquid crystal display device includes: a gate wiring formed in one direction on a substrate, a gate link line and a gate pad connected thereto; A data link line and a data pad defining a pixel area crossing the gate line perpendicularly to the gate line, and connected at one end thereof; A thin film transistor positioned at the intersection of the gate line and the data line, the thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; A black matrix formed on the thin film transistor; A color filter connected to the thin film transistor and positioned in the pixel area; A blocking pattern configured to correspond to the gate link line and the data link line; And an inorganic insulating layer formed on the black matrix and the blocking pattern.

The blocking pattern is patterned on the inorganic insulating layer corresponding to each spaced area of the gate link line and the data link line.

The inorganic insulating film is configured to directly contact the gate and the data link line.

The pixel electrode may be formed of a double layer with the color filter interposed therebetween.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First Embodiment

The first embodiment of the present invention is characterized in that a blocking pattern is formed in the light leakage region outside the substrate.

5 is a plan view schematically showing the configuration of an array substrate for a liquid crystal display device having a COT structure according to the present invention.

As shown in the drawing, the gate wiring 102 extends in one direction on one side of the substrate 100 and includes a gate link line 104 and a gate pad 106 connected thereto at one end thereof. A data line 110 is formed to intersect the vertical line 102 and include a data link line (not shown) and a data pad (not shown) connected thereto at one end thereof.

The thin film transistor T including the gate electrode 112, the active layer 114, and the source and drain electrodes 116 and 118 is formed at the point where the gate wiring 102 and the data wiring 110 cross each other. The black matrix of the part corresponding to the thin film transistor whose symbol is indicated is not displayed.)

A transparent pixel electrode 124 is formed in the pixel region P defined by the two interconnections 102 and 110 crossing each other.

In the above-described configuration, the black matrix 122 is formed on the thin film transistor T, the gate wiring 102, and the data wiring 110, and each pixel region P is disposed below the pixel electrode 124. Each of the red, green, and blue color filters 120a, 120b, and 120c are sequentially configured.

In the above-described configuration, the blocking pattern 126 is formed on the entire surface corresponding to the region F through which the gate link line 104 connecting the gate line 102 and the gate pad 106 passes.

The blocking pattern 126 may be configured in the same process as forming the black matrix 122 corresponding to the display area C or in the process of forming the color filters 120a, 120b, and 120c. have.

In the case of using the color filter, two or more color filters may be stacked or the color resins forming the color filters may be mixed.

In this case, the blocking pattern may be configured as shown in FIGS. 6A to 6B.

6A through 6B are cross-sectional views taken along the line VI-VI ′ of FIG. 5.

As shown in FIG. 6A, the gate link line 104 connecting the gate pad 106 (in FIG. 5) and the gate wiring 102 (FIG. 5) is configured to be spaced a predetermined distance apart from each other, and the link line ( An insulating film 128 is formed on the entire surface of the substrate 100 having the 104 formed thereon.

In this case, the insulating layer 128 may be formed of more than one layer, may be composed of two layers, when the two layers may be different materials.

A blocking pattern 126 is formed on the entire surface of the insulating layer 128 to correspond to the gate link line 104 and the spaced area G.

In this case, since the blocking pattern 126 is configured to block light, as illustrated in FIG. 6B, the blocking pattern 126 may be formed only at a portion corresponding to the area G between the gate link lines 104. 126) may be configured.

As described above, when the blocking pattern 126 is configured to correspond to the area connecting the wiring and the pad corresponding to the light leakage area of the outer side of the liquid crystal panel, the light leakage phenomenon can be prevented to produce a high quality liquid crystal display device. There is an advantage.

However, in the above-described configuration, the portion in which the blocking pattern 126 is formed is an area in which sealant, which is an adhesive means for bonding the first and second substrates, is printed.

Since the sealant is poor in interfacial properties with the organic film or the resin film, it is easy to generate a floating defect. Since the blocking pattern is formed of an opaque organic material or resin like the black matrix or the color filter, the sealant may be lifted. Defects are likely to occur.

Thus, a more improved example than the first embodiment will be described below with reference to the second embodiment.

Second Embodiment

The second embodiment is characterized in that a blocking pattern is formed in the light leakage region outside the substrate, and an inorganic insulating film is formed on the blocking pattern.

7 is a plan view schematically showing the configuration of an array substrate for a liquid crystal display device having a COT structure according to the present invention.

As shown, the gate wiring 202 extends in one direction on one side of the substrate 200 and includes a gate link line 204 and a gate pad 206 connected thereto at one end thereof in parallel to each other. A data line 210 intersects with the vertical line 202 and includes a data link line (not shown) and a data pad (not shown) connected thereto at one end thereof.

The thin film transistor T including the gate electrode 212, the active layer 214, and the source and drain electrodes 216 and 218 is formed at the point where the gate line 202 and the data line 210 cross each other. For convenience, the black matrix corresponding to the marked thin film transistor is not displayed.)

A transparent pixel electrode 224 is formed in the pixel region P defined by the two wires 202 and 210 intersecting each other.

In the above-described configuration, a black matrix 222 is formed on the thin film transistor T, the gate wiring 202, and the data wiring 210, and each pixel region P is formed on the pixel electrode 224. The red, green, and blue color filters 220a, 220b, and 220c are sequentially configured.

In the above-described configuration, the blocking pattern 226 is formed on the entire surface corresponding to the region F through which the gate link line 204 connecting the gate line 202 and the gate pad 206 passes.

The blocking pattern 226 may be formed in the same process as that of forming the black matrix 222 corresponding to the display area C or in the process of forming the color filter as described above.

An inorganic insulating layer 228 is formed on the blocking pattern 226, and a seal pattern 230 is formed on the inorganic insulating layer 228.

In this case, the inorganic insulating layer 228 may be configured to have the same area as the blocking pattern 226.

In the configuration as described above, the portion (H) where the seal pattern is located may be variously configured, with reference to the drawings of Figs.

8, 9, and 10 are enlarged cross-sectional views illustrating first to third examples cut along the line VII-VII of FIG. 7, respectively.

8 is a sectional view showing a configuration according to a first example of the second embodiment.

As illustrated, a plurality of gate link lines 204 connecting the gate line 202 of FIG. 7 and the gate pads 206 of FIG. 7 are formed on the substrate 200 so as to be spaced apart from each other. An insulating film 232 is formed over the entire surface of the substrate 200 having the 204 formed thereon.

As described above, the insulating layer 232 may be formed of one layer or two or more layers. When the insulating layer 232 is formed of two or more layers, different insulating materials may be used.

A blocking pattern 226 is formed on the insulating layer 232 corresponding to the gate link line 204, and the blocking pattern 226 is formed on an upper portion of the gate link line 204 and a spaced area G thereof. It forms corresponding to the corresponding front surface. The blocking pattern 226 may be formed in a process of forming a black matrix and a color filter corresponding to the display area, and in the case of using the color filter, red, green, and blue color resins may be stacked. have.

An inorganic insulating layer 228 is formed on the blocking pattern 226, which is generally formed using silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ).

The blocking pattern 226 may be formed on the entire surface of the gate link line 204 to correspond to the spaced area G, and as illustrated, only the region between the gate link line G is disposed. It may be formed by.

Hereinafter, FIG. 9 is a modified example of the configuration of FIG. 8 and proposes a cross-sectional configuration for widening a contact region of the seal pattern.

As illustrated, a plurality of gate link lines 204 connecting the gate wirings 202 of FIG. 7 and the gate pads 206 of FIG. 2 are formed on the substrate 200 so as to be spaced apart from each other. An insulating film 232 is formed over the entire surface of the substrate 200 having the 204 formed thereon.

As described above, the insulating layer 232 may be formed of one layer or two or more layers. When the insulating layer 232 is formed of two or more layers, different insulating materials may be used.

Next, the insulating layer 232 is patterned to etch a portion corresponding to the gate link line 204 to partially expose the lower gate link line 204.

Next, a blocking pattern 226 is formed on the insulating layer 232 corresponding to the spaced area G of the gate link line 204. In this case, the blocking pattern 226 may be formed in a process of forming a black matrix (222 of FIG. 7) and a color filter (220a, b, c of FIG. 7) formed corresponding to the display area (C of FIG. 7). In the case of using the color filter, red, green, and blue color filters may be stacked, or color resins may be mixed.

Next, silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) are deposited on the blocking pattern 226 and the gate link line 204 exposed to form an inorganic insulating layer 228.

Subsequently, the seal pattern 230 is formed on the inorganic insulating layer 228 through a printing method.

As described above, the contact area of the seal pattern 230 can be widened by etching the insulating film 232 corresponding to the gate link line 204, which further improves the contact characteristics of the seal pattern. There is an advantage.

10 illustrates another example, that is, a plurality of gate link lines 206 connecting the gate wirings 202 of FIG. 7 and the gate pads 206 of FIG. 7 are spaced apart from each other on the substrate 200. The insulating film 232 is formed on the entire surface of the substrate 200 having the gate link line 206 formed thereon.

As described above, the insulating layer 232 may be formed of one layer or two or more layers. When the insulating layer 232 is formed of two or more layers, different insulating materials may be used.

Next, the insulating film 232 is patterned to etch a portion corresponding to the gate link line 204 and partially expose the lower gate link line 204.

Next, a blocking pattern 226 is formed on the insulating layer 232 corresponding to the spaced area G of the gate link line 204. In this case, the blocking pattern 226 may be formed in a process of forming a black matrix and a color filter formed corresponding to the display area. When the color filter is used, red, green, and blue color resins may be stacked. Can be.

Next, the seal pattern 230 is formed on the blocking pattern 226 through a printing method.

As described above, the insulating region corresponding to the gate link line 204 is etched to widen the contact region of the seal pattern, although the inorganic insulating layer may be omitted as in the configuration of FIG. 9. However, this also has the advantage of further improving the contact characteristics of the seal pattern.

With the configuration as described above, it is possible to form the outer structure of the COT structure according to the present invention.

The structure of the first and second embodiments as described above may be applied to the structure of the thin film transistor array unit as shown in FIGS. 11, 12, and 13.

11, 12, and 13 are cross-sectional views taken along first, second, and third examples of cross sections taken along the line VII-VII ′ of FIG. 7.

FIG. 11 is an enlarged cross-sectional view showing a cross section of one pixel of an array substrate for a liquid crystal display device having a COT structure according to a first example of the present invention.

As illustrated, a gate electrode 212 is formed on the substrate 200, and a gate insulating film 232a is formed on the gate electrode 212.

The active layer 214 and the ohmic contact layer 215 are stacked on the gate insulating layer 232a corresponding to the gate electrode 212, and the ohmic contact layer 215 is in contact with the ohmic contact layer 215. While forming the source and drain electrodes 216 and 218 spaced apart from each other.

In order to protect the active layer 214 on the front surface of the substrate 200 on which the source and drain electrodes 216 and 218 are formed, a passivation layer 232b is formed of an inorganic insulating material.

In the pixel region P, color filters 220a and 220b in contact with the drain electrode 218 are formed on the gate insulating layer 232a corresponding to the pixel region P. Referring to FIG.

Next, a black matrix 222 is formed on the thin film transistor T.

In the process of forming the color filters 220a and b and the black matrix 222, a blocking pattern (not shown) is applied to the outer region of the first embodiment, that is, the light leakage region corresponding to the gate link line (not shown). It may be formed at the same time. That is, when a blocking pattern (not shown) is formed using the color filter, one or more color filter patterns may be stacked.

In the above-described configuration, in order to contact the drain electrode 218 and the pixel electrode 224, during the process of etching the gate insulating film 232a corresponding to the drain electrode 218 and the protective film 232b thereon, As illustrated in FIG. 10, an insulating film (ie, the gate insulating film and the passivation film are represented as one) 232 corresponding to the spaced space of the gate link line 204 outside the substrate may be etched.

At this time, the insulating film 232 is also a two-layer structure of the gate insulating film 232a and the protective film 232b.

12 is an enlarged cross-sectional view showing a cross section of one pixel of the array substrate for a liquid crystal display device of the COT structure applicable to the pixel portion of the second embodiment.

As illustrated, a gate electrode 212 is formed on the substrate 200, and a gate insulating film 232a is formed on the gate electrode 212.

The active layer 214 and the ohmic contact layer 215 are stacked on the gate insulating layer 232a corresponding to the gate electrode 212, and the ohmic contact layer 215 is disposed on the ohmic contact layer 215. In contact, source and drain electrodes 216 and 218 spaced apart from each other are formed.

A first passivation layer 232b is formed of an inorganic insulating material on the entire surface of the substrate 200 on which the source and drain electrodes 216 and 218 are formed to protect the active layer 214.

In the pixel region, color filters 220a and b in contact with the drain electrode 219 are formed on the gate insulating layer 232a corresponding to the pixel region P. FIG.

Next, a black matrix 222 is formed on the thin film transistor T.

The second passivation layer 228 is further formed of an inorganic insulating layer on the entire surface of the substrate 200 on which the color filters 220a and b and the black matrix 222 are formed.

In addition, a pixel electrode 224 positioned in correspondence with the pixel region P is formed on the second passivation layer 228 while being in contact with the drain electrode 218.

In the process of forming the black matrix 222 and the color filters 220a and b, a blocking pattern (not shown) may be simultaneously formed on the outer region of the second embodiment, that is, the light leakage region corresponding to the gate link line. The inorganic insulating film 228 formed on the black matrix 222 and the color filters 220a and b is formed, and the inorganic insulating film (FIGS. 8 and FIG. 228 of 10 may be formed at the same time. In this case, when the blocking pattern is formed using the color filter, one or more color filter patterns may be stacked.

In addition, in order to contact the drain electrode 218 and the pixel electrode 224, the gate as shown in the cross-sectional configuration of FIG. 9 during the process of etching the first passivation layer 232b and the gate insulating layer 232a thereunder. The insulating film 232 corresponding to the spaced space between the link lines 204 may be etched.

FIG. 13 is an enlarged cross-sectional view illustrating a configuration of one pixel of an array substrate for a liquid crystal display device having a COT structure which is different from that of FIGS. 11 and 12.

As illustrated, a gate electrode 212 is formed on the substrate 200, and a gate insulating film 232a is formed on the gate electrode 212.

The active layer 214 and the ohmic contact layer 215 are stacked on the gate insulating layer 232a corresponding to the gate electrode 212, and the ohmic contact layer 215 is in contact with the ohmic contact layer 215. While forming the source and drain electrodes 216 and 218 spaced apart from each other.

In order to protect the active layer 214 on the front surface of the substrate 200 on which the source and drain electrodes 216 and 218 are formed, a first passivation layer 232b is formed of an inorganic insulating material.

The pixel region P includes a first pixel electrode 224a in direct contact with the drain electrode 218, and color filters 220a and 220b on the first pixel electrode 224a. Second pixel electrodes 224b that contact the first pixel electrode 224a are formed on the upper portions 220a and 220b.

In the above-described configuration, before forming the first and second pixel electrodes 224a and 224b and the color filters 220a and 220b, the black matrix 222 is formed to correspond to the upper portions of the source and drain electrodes 216 and 218. A second passivation layer is formed on the black matrix 222 using an inorganic insulating material.

The configuration as described above is applicable to the liquid crystal display array substrate of the COT structure having the cross-sectional configuration of FIGS. 11 and 12 described above.

The configuration of the array substrate for a liquid crystal display device having the COT structure and the manufacturing method thereof according to the present invention have been described with the configuration as described above.

Although the above-described configuration has been described with respect to the gate link unit, this is obviously applicable to the data link unit.

As described above, the liquid crystal display device having the COT structure having the outer structure according to the present invention has an effect of producing a high-quality liquid crystal display device because light leakage defects do not occur at the periphery of the substrate.

In addition, since the color filter and the black matrix are configured on the same substrate as the thin film transistor array unit, the design of the black matrix does not have to consider the bonding margin, thereby improving the aperture ratio.

Claims (12)

A gate wiring formed in one direction on the substrate, a gate link line and a gate pad connected thereto; A data link line and a data pad defining a pixel area crossing the gate line perpendicularly to the gate line, and connected at one end thereof; A thin film transistor positioned at the intersection of the gate line and the data line, the thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; A black matrix formed on the thin film transistor; A color filter connected to the thin film transistor and positioned in the pixel area; A blocking pattern configured to correspond to the gate link line and the data link line; Array substrate for a liquid crystal display device comprising a. The method of claim 1, Array substrate for liquid crystal display device further comprising an inorganic insulating film between the black matrix and the thin film transistor The method of claim 1, And the blocking pattern is patterned to correspond to each of the separation regions of the gate link line and the data link line. The method of claim 1, An array substrate for a liquid crystal display device further comprising a sealant pattern that is an adhesive on the blocking pattern. The method of claim 4 And the sealant pattern is in direct contact with the gate and the data link line. The method according to any one of claims 1 to 5, And the pixel electrode is formed of a double layer with the color filter interposed therebetween. A gate wiring formed in one direction on the substrate, a gate link line and a gate pad connected thereto; A data link line and a data pad defining a pixel area crossing the gate line perpendicularly to the gate line, and connected at one end thereof; A thin film transistor positioned at the intersection of the gate line and the data line, the thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; A black matrix formed on the thin film transistor; A color filter connected to the thin film transistor and positioned in the pixel area; A blocking pattern configured to correspond to the gate link line and the data link line; An inorganic insulating layer formed on the black matrix and the blocking pattern; Array substrate for a liquid crystal display device comprising a. The method of claim 7, wherein Array substrate for liquid crystal display device further comprising an inorganic insulating film between the black matrix and the thin film transistor The method of claim 7, wherein And the blocking pattern is patterned on an upper portion of the inorganic insulating layer corresponding to each spaced area of the gate link line and the data link line. The method of claim 9, And the inorganic insulating film is in direct contact with the gate and the data link line. The method of claim 10, An array substrate for a liquid crystal display device further comprising a sealant pattern, which is an adhesive, on the inorganic insulating film. The method according to any one of claims 8 to 11, And the pixel electrode is formed of a double layer with the color filter interposed therebetween.