KR20040048605A - CMOS operational amplifier with class AB differential output - Google Patents

CMOS operational amplifier with class AB differential output Download PDF

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KR20040048605A
KR20040048605A KR1020020076523A KR20020076523A KR20040048605A KR 20040048605 A KR20040048605 A KR 20040048605A KR 1020020076523 A KR1020020076523 A KR 1020020076523A KR 20020076523 A KR20020076523 A KR 20020076523A KR 20040048605 A KR20040048605 A KR 20040048605A
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common mode
output
differential
operational amplifier
mode feedback
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KR1020020076523A
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KR100450776B1 (en
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탁금영
현석봉
박성수
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한국전자통신연구원
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45192—Folded cascode stages

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE: A CMOS differential operation amplifier of a class AB is provided to control bias of a transistor of an output terminal and reduce the power consumption by using two differential amplifiers for performing a common mode feedback process. CONSTITUTION: A CMOS differential operational amplifier of a class AB includes a differential amplification circuit and a common mode feedback circuit. The differential amplification circuit(100) amplifies a difference between two input signals as much as a predetermined gain. The common mode feedback circuit(200) controls bias of an output transistor of the differential amplification circuit by using a common mode feedback method. The differential amplification circuit performs an amplification process using a class AB method.

Description

클래스 ＡＢ 차동출력 ＣＭＯＳ 연산증폭기{CMOS operational amplifier with class AB differential output}CMOS operational amplifier with class AB differential output

본 발명은 증폭기에 관한 것으로, 특히 클래스 AB 차동 출력을 가지는 CMOS 연산증폭기에 관한 것이다.TECHNICAL FIELD The present invention relates to amplifiers and, more particularly, to CMOS op amps having a class AB differential output.

연산증폭기(Operational amplifier, OP-amp) 회로는 아날로그 집적 회로에서는 기본적인 구성회로이고 오래 전부터 여러 가지 구조의 op-amp 회로들이 사용되고 있다. Op-amp는 오픈 루프 이득(open-loop gain)이 크고 주파수가 높아져도 그 이득(gain)이 높게 유지될수록 이상적인 동작을 한다고 볼 수 있다. 따라서, 소모 전력은 줄이고 대역폭은 늘리려는 방향으로 op-amp 회로에 대한 연구가 진행되어왔다.Operational amplifier (OP-amp) circuits are basic components in analog integrated circuits, and op-amp circuits of various structures have been used for a long time. Op-amps are ideal for high open-loop gain and high frequency, keeping the gain high. Therefore, researches on op-amp circuits have been conducted to reduce power consumption and increase bandwidth.

기존의 방식으로는, telescopic op-amp, two-stage op-amp, folded cascadeop-amp 등의 기본적인 구조와, 이러한 구조들에 regulated cascade를 적용하거나 class AB output stage 등을 적용한 회로들이 있다. 그런데, 이러한 방식들은 높은 주파수에서도 이득을 높게 유지하려면 많은 전력이 필요하고, 이득이 유지되더라도 출력 swing이 작은 단점이 있다.Conventional methods include basic structures such as telescopic op-amps, two-stage op-amps, and folded cascadeop-amps, and circuits using regulated cascades or class AB output stages. However, these methods require a lot of power to maintain a high gain even at a high frequency, and the output swing is small even if the gain is maintained.

본 발명이 이루고자 하는 기술적 과제는, 소모 전력이 적으면서 gain-bandwidth product와 출력 swing이 큰 연산증폭기를 제공하는 것이다.The technical problem to be achieved by the present invention is to provide an operational amplifier with a low power consumption and a large gain-bandwidth product and output swing.

도 1은 본 발명에 의한 연산증폭기의 회로도이다.1 is a circuit diagram of an operational amplifier according to the present invention.

도 2는 본 발명에 의한 연산증폭기 회로의 open loop gain과 phase를 나타낸 그래프이다.2 is a graph showing the open loop gain and phase of the operational amplifier circuit according to the present invention.

상기 기술적 과제를 이루기 위한 본 발명에 의한 연산증폭기는, 두 개의 입력 신호의 차를 소정의 이득만큼 증폭하는 차동증폭부; 및 공통 모드 귀환을 통해 상기 차동증폭부의 출력 트랜지스터의 바이어스를 제어하는 공통모드귀환부를 포함하는 것이 바람직하다.The operational amplifier according to the present invention for achieving the above technical problem, the differential amplifier for amplifying the difference between the two input signals by a predetermined gain; And a common mode feedback unit controlling the bias of the output transistor of the differential amplifier through common mode feedback.

상기 차동증폭부는 클래스 AB 방식의 증폭을 하는 것이 바람직하다.Preferably, the differential amplifier amplifies the class AB method.

상기 공통모드귀환부는, 상기 차동증폭부의 입력 증폭기의 복사 회로를 포함하며, 상기 복사 회로의 테일 전류를 상기 차동증폭부에 귀환하는 것이 바람직하며, 공통 모드 귀환을 통해 상기 차동증폭부의 출력 트랜지스터의 공통 모드 전류를 정하는 것이 바람직하다.The common mode feedback unit includes a copy circuit of an input amplifier of the differential amplifier, and returns a tail current of the copy circuit to the differential amplifier, and common to the output transistors of the differential amplifier through common mode feedback. It is desirable to determine the mode current.

바람직하게는, 상기 공통모드귀환부는, 상기 차동증폭부의 최종 출력 신호의 공통 모드 전압에 대하여 선형 출력을 생성하는 출력귀환부; 및 상기 출력귀환부의 선형 출력을 기준으로 하는 레퍼런스 전류를 생성하는 기준전류제공부를 포함한다.Preferably, the common mode feedback unit, an output feedback unit for generating a linear output with respect to the common mode voltage of the final output signal of the differential amplifier; And a reference current providing unit generating a reference current based on the linear output of the output feedback unit.

또한, 상기 연산증폭기는 CMOS 집적 회로로 구성되는 것이 바람직하다.In addition, the operational amplifier is preferably composed of a CMOS integrated circuit.

이하, 첨부된 도면들을 참조하여 본 발명에 따른 연산증폭기에 대해 상세히 설명한다.Hereinafter, an operational amplifier according to the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명에 의한 연산증폭기의 회로도이다.1 is a circuit diagram of an operational amplifier according to the present invention.

도 1을 참조하면, 본 발명에 의한 연산증폭기는 차동증폭부(100)와 공통모드귀환부(200)를 포함한다.Referring to FIG. 1, the operational amplifier according to the present invention includes a differential amplifier 100 and a common mode feedback unit 200.

차동증폭부(100)는 두 개의 입력 신호(inm 및 inp)의 차를 소정의 이득만큼 증폭한다.The differential amplifier 100 amplifies the difference between the two input signals inm and inp by a predetermined gain.

공통모드귀환부(200)는 공통 모드 귀환(common mode feedback)을 통해 상기 차동증폭부(100)의 출력 트랜지스터의 바이어스를 제어한다. 이를 위해 공통모드귀환부(200)는 입력 증폭기의 복사 회로(210), 차동증폭부(100)의 최종 출력 신호의 공통 모드 전압에 대하여 선형 출력을 생성하는 출력귀환부(230), 및 출력귀환부(230)의 선형 출력을 기준으로 하는 레퍼런스 전류를 생성하는 기준전류제공부(220)를 포함하는 것이 바람직하다.The common mode feedback unit 200 controls the bias of the output transistor of the differential amplifier 100 through common mode feedback. To this end, the common mode feedback unit 200 includes an output circuit 230 for generating a linear output with respect to a common mode voltage of the copy circuit 210 of the input amplifier, the final output signal of the differential amplifier 100, and output feedback. It is preferable to include a reference current providing unit 220 for generating a reference current based on the linear output of the unit 230.

본 발명에 따른 연산증폭기 회로는, Class AB control을 위해서 공통 모드 귀환(common mode feedback)을 하는 두 개의 차동 증폭기(differential amp)를 사용하였다. mn10, mn8, mn6, 및 mp4를 포함하는 부분이 NMOS input differential amp이고, mp10, mp8, mp6, 및 mn4를 포함하는 부분이 PMOS input differential amp이다.The operational amplifier circuit according to the present invention uses two differential amplifiers having common mode feedback for Class AB control. The part containing mn10, mn8, mn6, and mp4 is an NMOS input differential amp, and the part containing mp10, mp8, mp6, and mn4 is a PMOS input differential amp.

각 amp의 common mode feedback은 복사(replica) 회로(210)를 사용하여 이루어 진다. mn9, mn7, mn5, 및 mp2로 이루어진 회로가 NMOS differential amp의 복사 회로이며, mp9, mp7, mp5, 및 mn2로 이루어진 회로가 PMOS differential amp의 복사 회로이다. 기준전류제공부(220)에 포함된 mp1과 복사 회로(210)에 포함된 mp2의 드레인(drain) 전압이 같도록 op-amp에 의해서 feedback된다. 복사회로(210)의 common mode 출력전압과 차동증폭부(100)의 common mode 출력전압은 같으므로 차동증폭부(100)의 출력단에 포함된 mp3의 게이트(gate)의 common mode 전압이 복사회로(210)에 포함된 mp2의 drain 전압과 같아지게 된다. 결국 mp1에 흐르는 전류(current)가 mp3의 공통 모드 전류(common mode current)로 미러링(mirroring)된다. 마찬가지로 PMOS differential amp의 common mode 출력 전압도 기준전류제공부(220)에 포함된 mn1에 흐르는 current가 차동증폭부(100)의 출력단에 포함된 mn3의 common mode current로 mirroring된다.The common mode feedback of each amp is achieved using a replica circuit 210. The circuit consisting of mn9, mn7, mn5, and mp2 is the copy circuit of the NMOS differential amp, and the circuit consisting of mp9, mp7, mp5, and mn2 is the copy circuit of the PMOS differential amp. The feedback voltage is fed back by the op-amp so that the drain voltage of mp1 included in the reference current providing unit 220 and mp2 included in the radiation circuit 210 are the same. Since the common mode output voltage of the copy circuit 210 and the common mode output voltage of the differential amplifier 100 are the same, the common mode voltage of the gate of mp3 included in the output terminal of the differential amplifier 100 is equal to the copy circuit ( It becomes equal to the drain voltage of mp2 included in 210). As a result, the current flowing to mp1 is mirrored to the common mode current of mp3. Similarly, the common mode output voltage of the PMOS differential amp is mirrored to the common mode current of mn3 included in the output terminal of the differential amplifier 100 at the current flowing in mn1 included in the reference current providing unit 220.

이와 같은 방식으로 차동증폭부(100)의 출력단(output stage)에서 소모하는 common mode current가 결정된다. NMOS differential pair의 출력으로 출력단(output stage)의 PMOS를 구동하고 PMOS differential pair의 출력으로 출력단의 NMOS를 구동한다.In this manner, the common mode current consumed at the output stage of the differential amplifier 100 is determined. The output of the NMOS differential pair drives the PMOS at the output stage and the output of the PMOS differential pair drives the NMOS at the output stage.

본 발명에 의한 연산증폭기는 Class AB 증폭을 하며, differential rail-to-rail 방식의 output op-amp로 작동한다. Class AB 방식으로 출력하므로 적은 전력을 소모하면서도 slew rate가 크고 bandwidth가 넓으며, rail-to-rail 방식으로 output swing도 크다. 그리고, 두 개의 differential amp를 병렬로 사용한 구조이므로 각각의 증폭기의 이득을 합한 정도의 open loop gain을 얻을 수 있다.The operational amplifier according to the present invention performs Class AB amplification and operates as a differential rail-to-rail output op-amp. The output is Class AB method, so it consumes less power and has a larger slew rate, a wider bandwidth, and a rail-to-rail method, which also has a large output swing. In addition, since two differential amps are used in parallel, the open loop gain can be obtained by adding the gains of the respective amplifiers.

또한, 이러한 복사(replica) 회로(210)를 사용하여 mn10, mp10의 gate 전압을 feedback하는 것은 CMRR(Common Mode Rejection Ratio)를 증가시키고 동작 가능한 input common mode 영역을 넓히는 효과가 있다. mn10이나 mp10이 선형 영역에서 동작해도 전체 op-amp의 성능을 유지할 수 있다.In addition, the feedback of the gate voltages of mn10 and mp10 using such a replica circuit 210 has an effect of increasing the common mode rejection ratio (CMRR) and widening the operable input common mode region. Even if mn10 or mp10 operate in the linear region, the overall op-amp performance can be maintained.

최종출력신호(outp 및 outm)의 common mode feedback은 mn11 및 mn12를 포함하는 출력귀환부(230)에서 이루어진다. mn11과 mn12는 선형영역에서 동작한다. 본 회로에서 common mode feedback loop가 안정(stable)하려면 open loop gain이 작은 feedback회로를 사용해야 하므로 이와 같은 구조가 적합하다.Common mode feedback of the final output signals outp and outm is made in the output feedback unit 230 including mn11 and mn12. mn11 and mn12 operate in the linear domain. In this circuit, in order to stabilize the common mode feedback loop, such a structure is suitable because a feedback circuit with a small open loop gain must be used.

도 2는 본 발명에 의한 연산증폭기 회로의 open loop gain과 phase를 나타낸 그래프이다.2 is a graph showing the open loop gain and phase of the operational amplifier circuit according to the present invention.

도 2를 참조하면, 본 발명에 의한 연산증폭기는 적은 전력을 소모하면서도 gain-bandwidth product가 크다. 그리고, class AB 방식으로 differential 출력을 하며, output swing도 rail-to-rail로 크다.Referring to FIG. 2, the operational amplifier according to the present invention consumes little power but has a large gain-bandwidth product. The differential output is done in class AB, and the output swing is also large rail-to-rail.

본 발명은 도면에 도시된 실시예를 참고로 설명되었으나 이는 예시적인 것에 불과하며, 본 기술 분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다. 따라서, 본 발명의 진정한 기술적 보호 범위는 첨부된 등록청구범위의 기술적 사상에 의해 정해져야 할 것이다.Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

본 발명에 의한 연산 증폭기는, 공통 모드 귀환을 하는 두 개의 차동증폭기를 사용하여 출력단의 트랜지스터의 바이어스를 제어함으로써, 적은 전력을 소모하면서도 gain-bandwidth product가 크고 class AB 방식의 differential 출력을 가지며, rail-to-rail 방식의 큰 output swing을 가질 수 있다.The operational amplifier according to the present invention controls the bias of the transistor at the output stage by using two differential amplifiers having common mode feedback, so that the gain-bandwidth product is large and the class AB type differential output is used while consuming little power. It can have a large output swing in the -to-rail manner.

Claims (6)

두 개의 입력 신호의 차를 소정의 이득만큼 증폭하는 차동증폭부; 및A differential amplifier for amplifying a difference between two input signals by a predetermined gain; And 공통 모드 귀환을 통해 상기 차동증폭부의 출력 트랜지스터의 바이어스를 제어하는 공통모드귀환부를 포함하는 것을 특징으로 하는 연산증폭기.And a common mode feedback unit controlling a bias of the output transistor of the differential amplifier through common mode feedback. 제 1 항에 있어서,The method of claim 1, 상기 차동증폭부는 클래스 AB 방식의 증폭을 하는 것을 특징으로 하는 연산증폭기.The differential amplifier is an operational amplifier, characterized in that the amplification of the class AB method. 제 1 항에 있어서, 상기 공통모드귀환부는,The method of claim 1, wherein the common mode feedback unit, 상기 차동증폭부의 입력 증폭기의 복사 회로를 포함하며,A radiation circuit of the input amplifier of the differential amplifier; 상기 복사 회로의 테일 전류를 상기 차동증폭부에 귀환하는 것을 특징으로 하는 연산증폭기.And an operational amplifier returning the tail current of the radiation circuit to the differential amplifier. 제 1 항에 있어서, 상기 공통모드귀환부는,The method of claim 1, wherein the common mode feedback unit, 공통 모드 귀환을 통해 상기 차동증폭부의 출력 트랜지스터의 공통 모드 전류를 정하는 것을 특징으로 하는 연산증폭기.The operational amplifier of claim 1, wherein the common mode current of the output transistor of the differential amplifier is determined through common mode feedback. 제 1 항에 있어서, 상기 공통모드귀환부는,The method of claim 1, wherein the common mode feedback unit, 상기 차동증폭부의 최종 출력 신호의 공통 모드 전압에 대하여 선형 출력을 생성하는 출력귀환부; 및An output feedback unit generating a linear output with respect to a common mode voltage of the final output signal of the differential amplifier; And 상기 출력귀환부의 선형 출력을 기준으로 하는 레퍼런스 전류를 생성하는 기준전류제공부를 포함하는 것을 특징으로 하는 연산증폭기.And a reference current providing unit generating a reference current based on the linear output of the output feedback unit. 제 1 항에 있어서, 상기 연산증폭기는 CMOS 집적 회로로 구성되는 것을 특징으로 하는 연산증폭기.2. The operational amplifier of claim 1, wherein the operational amplifier comprises a CMOS integrated circuit.
KR10-2002-0076523A 2002-12-04 2002-12-04 CMOS operational amplifier with class AB differential output KR100450776B1 (en)

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KR100877626B1 (en) * 2007-05-02 2009-01-09 삼성전자주식회사 Class AB Amplifier and Input stage circuit for the same
US7586373B2 (en) 2007-03-26 2009-09-08 Samsung Electronics Co., Ltd. Fully differential class AB amplifier and amplifying method using single-ended, two-stage amplifier

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US7586373B2 (en) 2007-03-26 2009-09-08 Samsung Electronics Co., Ltd. Fully differential class AB amplifier and amplifying method using single-ended, two-stage amplifier
KR100877626B1 (en) * 2007-05-02 2009-01-09 삼성전자주식회사 Class AB Amplifier and Input stage circuit for the same

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