KR20040044690A - Complementary pass transistor flip-flop circuit using mtcmos technology having initialization function - Google Patents

Abstract

PURPOSE: A CP flip flop circuit by using MTCMOS technology provided with an initial function is provided to allow the circuit to be initialized by generating a logical control signal and a switch control signal. CONSTITUTION: A CP flip flop circuit by using MTCMOS technology provided with an initial function includes a clock delay block(10), a switch block(20), a latch block(30), a buffer block(40), a switching transistor(MN14) and an initial circuit(60). The initial circuit(60) generates a logical control signal and a switch control signal. The CP flip flop circuit allows all of the logic circuits except the latch block(30) to be floated at the sleep mode. And, the CP flip flop circuit allows all of the circuits including the latch block(30) to be floated at the active mode.

Description

CPL flip-flop circuit using MTCMOS technology with initialization function TECHNICAL TECHNOLOGY HAVING INITIALIZATION FUNCTION}

The present invention relates to a CP (Flementary Pass Transistor) flip-flop circuit using MTCMOS technology, and more particularly to a CP flip-flop circuit using MTCMOS technology having an initialization function.

Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) technology enables active mode by connecting a metal oxide semiconductor (MOS) transistor with a relatively high threshold voltage (Vth) between the power supply voltage (or ground voltage) and the logic circuit. In the active mode (power on), the MOS transistor is turned on to supply a power supply voltage (or ground voltage) to a logic circuit having a relatively low Vth, thereby improving the operation speed of the logic circuit, and in the sleep mode (power off), the MOS transistor is turned on. It is a technology to reduce the leakage current (leakage current, sub-threshold current) of the logic circuit by turning off the transistor to cut off the supply voltage (or ground voltage) to the logic circuit. MTCMOS technology is particularly useful for reducing the power consumption of large scale integration (LSI) chips for portable devices, which are much longer than in sleep mode. However, the MTCMOS technology has a problem in that data stored in a latch or flip-flop of a logic circuit is lost at power off, that is, in a sleep mode. Several circuits have been published that solve the problem of data loss in flip-flop circuits using MTCMOS technology. Among them, complementary pass transistor (CP) flip-flops are excellent in area, operation speed, and power consumption on semiconductor chips. 1 is a diagram illustrating a conventional CP flip-flop circuit, which is disclosed in US Patent 2002/0047737 filed by the applicant of the present application. In FIG. 1, only the NOR circuit 16 and the latch circuit 30 are constituted by a high threshold (MOS) MOS transistor, and the remaining portions are constituted by a low threshold (MOS) MOS transistor. The CP flip-flop circuit of FIG. 1 includes a clock delay unit 10, a switch unit 20, a latch unit 30, a buffer unit 40, and a first inverter 50. When the clock signal CLK is in a low state, the NMOS transistors NM10 and NM11 that receive the input data D in the switch unit 20 are in an off state and thus do not receive the input data D. Since the inverted clock signal CLKB, which is the output signal of the clock delay unit 10, is high, the NMOS transistors NM12 and NM13 are in an on state. When the clock signal CLK transitions to the high state, the NMOS transistors NM10 and NM11 are turned on to receive the input data D. FIG. On the other hand, the NMOS transistors NM12 and NM13 are turned off after a certain delay time after the clock signal CLK transitions to a high state. Therefore, when the clock signal CLK transitions from the low state in which the input data D is not received to the high state, all the NMOS transistors NM10 to NM13 of the switch unit 20 are delayed by the delay time of the clock delay unit 10. ) Is in the on state and the input data D determines the state of the latch portion 30 and at the same time determines the output signal of the buffer portion 40. The output signal of the clock delay unit 10 turns off the NMOS transistors NM12 and NM13 when a predetermined delay time elapses after the clock signal CLK transitions to a high state, so the input data D is no longer latched ( 30) or the buffer unit 40 is not affected. At this time, the output signal of the buffer unit 40 is determined by the logic value stored in the latch unit 30. When the clock signal CLK transitions to the low state, since the input data D can no longer be received, the output state of the buffer unit 40 does not change.

The conventional CP flip-flop circuit shown in FIG. 1 is designed using MTCMOS technology to operate the logic circuit at high speed in the active mode and to minimize the leakage current in the sleep mode. In flip-flops using MTCMOS technology, a virtual ground or virtual power supply is placed, and a high threshold MOS transistor is placed between the virtual ground and ground or between the virtual power supply voltage and the power supply voltage. In addition, the inverters 32 and 34 constituting the latch unit 30 use an HT MOS transistor to reduce leakage current and directly connect to the virtual ground (or virtual power supply voltage) so that data can be stored even in the sleep mode. It is connected to ground (or power supply voltage). In addition, since the NOR circuit 16 in the clock delay unit 10 must operate in the sleep mode, the NOR circuit 16 is directly connected to the ground (or the power supply voltage) instead of the virtual ground (or the virtual power supply voltage).

However, in order for the CP flip-flop circuit using the MTCMOS shown in FIG. 1 to operate normally, a function of initializing the logic control signal SCB and the switch control signal SC (not shown) when the sleep mode is activated is provided. need.

CP flip-flop circuit using the MTCMOS technology according to the present invention is a reset terminal of the D-type flip-flop (Power-On-Reset (POR)) signal in order to solve the problems described above The two outputs Q and QB of the D flip-flop were used as the logic control signal SCB and the switch control signal SC.

An object of the present invention is to provide a CP flip-flop circuit using MTCMOS technology having an initialization function.

1 is a diagram illustrating a CP flip-flop circuit using a conventional MTCMOS technology.

2 is a diagram illustrating a CP flip-flop circuit using the MTCMOS technology having an initialization function according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a relationship between a power on reset (POR) signal and a power supply voltage used in the CP flip-flop circuit of FIG. 1.

<Description of the symbols for the main parts of the drawings>

10: clock delay unit 20: switch unit

30 latch portion 40 buffer portion

60: initialization unit

The CP flip-flop circuit using the MTCMOS technology according to the present invention is a CP flip-flop circuit using the MTCMOS technology including a clock delay unit, a switch unit, a latch unit, a buffer unit, and a switching transistor. The controller further includes an initialization circuit for generating a circuit to float all logic circuits except for the latch unit in the sleep mode, and to operate all logic circuits of the CP flip-flop circuit using the MTCMOS technology including the latch unit in the active mode.

The CP flip-flop circuit using the MTCMOS technology according to the present invention includes a first inverter for inverting input data, a second inverter for inverting a clock signal, a third inverter for inverting an output signal of the second inverter, and the third inverter. A clock delay unit having an NOR circuit for receiving an output signal and a logic control signal and performing a non-logical sum, a switching operation under the control of the input signal and an output signal of the first inverter and receiving the clock signal and an output signal of the clock delay unit A switch unit for outputting the input data and the output signal of the first inverter, a first latch terminal connected to the first output terminal of the switch unit, and a second latch terminal connected to the second output terminal of the switch unit; A latch unit for latching a negative output signal and an input terminal connected to the first output terminal of the switch unit And a fourth inverter for generating inverted output data having a phase opposite to the input data and a fifth inverter for generating output data having the same phase as the input data with an input terminal connected to the second output terminal of the switch unit. And a buffer unit configured to receive a power-on reset signal and to generate the logic control signal and the switch control signal, and a switching transistor connected between the virtual ground and the ground to perform a switching operation by the switch control signal.

The initialization unit includes a D flip-flop having a reset terminal for receiving a power-on reset signal and generating the logic control signal as an output terminal and a switch control signal as an inverted output terminal, when the power supply voltage reaches a normal value. The logic control signal goes low and the switch control signal goes high.

Hereinafter, a CP flip-flop circuit using MTCMOS technology according to the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating a CP flip-flop circuit using an MTCMOS technology having an initialization function according to an embodiment of the present invention. In the CP flip-flop circuit using the conventional MTCMOS technology shown in FIG. Added. Also shown in FIG. 2 is a virtual ground (VGND) not shown in FIG. 1, and an HT MOS transistor (MN14) that connects or blocks the virtual ground and ground, and each logic device is shown at the transistor level. The CP flip-flop circuit using the MTCMOS technology of FIG. 1 includes a clock delay unit 10, a switch unit 20, a latch unit 30, a buffer unit 40, a first inverter 50, an initialization unit 60, And a switching transistor MN14.

The first inverter 50 inverts the input data D.

The clock delay unit 10 includes a PMOS transistor MP2 and an NMOS transistor MN2, and includes a second inverter 12 for inverting the clock signal CLK, a PMOS transistor MP3, and an NMOS transistor MN3. The third inverter 14 which inverts the output signal of the second inverter 12 and the NMOS transistors MN4 and MN5 connected in parallel with the PMOS transistors MP4 and MP5 connected in series with each other and the third inverter 14 And an NOR circuit 16 for receiving an output signal and a logic control signal SCB and performing a non-logical sum.

The switch unit 20 includes NMOS transistors MN10 and MN11 for switching under the control of the clock signal CLK, and NMOS transistors MN12 and MN13 for switching under the control of the output signal of the clock delay unit 10. do.

The latch unit 30 has a fourth inverter 32 having an input terminal connected to the source terminal of the NMOS transistor MN12 of the switch unit 20 and an output terminal connected to the source terminal of the NMOS transistor MN13 of the switch unit 20. And a fifth inverter 34 having an input terminal connected to the source terminal of the NMOS transistor MN13 of the switch unit 20 and an output terminal connected to the source terminal of the NMOS transistor MN12 of the switch unit 20. do.

The buffer unit 40 has an input terminal connected to the source terminal of the NMOS transistor MN12 of the switch unit 20 to generate the inverted output data FOUTB having a phase opposite to that of the input data D. 42) and a seventh inverter 44 having an input terminal connected to the source terminal of the NMOS transistor MN13 of the switch section 20 and generating output data FOUT having the same phase as the input data D. do.

The initialization unit 60 has a D flip-flop having a reset terminal CLR for receiving a power-on-reset signal POR and generating a logic control signal SCB and a switch control signal SC. Equipped.

3 is a diagram illustrating a relationship between a power-on-reset (POR) signal and a power supply voltage used in the CP flip-flop circuit of FIG. 1. The POR signal is generated in a POR signal generating circuit (not shown) existing in the semiconductor chip, and is a signal that becomes high when the power supply voltage reaches a normal value VDD.

Hereinafter, an operation of a CP flip-flop circuit using the MTCMOS technology according to the present invention will be described with reference to FIGS. 2 and 3. Since the general operation of the CP flip-flop circuit is the same as that of the conventional CP flip-flop circuit shown in FIG. 1, the description thereof is omitted here.

The CP flip-flop circuit using the MTCMOS technology according to the present invention shown in FIG. 2 has a virtual ground (VGND) and a virtual ground (VGND) in order to reduce the leakage current that may occur in the elements constituting the logic circuit in the sleep mode. The switching transistor MN14 is provided between the ground GND. In the active mode, the switching transistor MN14 is turned on to operate the elements constituting the logic circuit. In the sleep mode, the switching transistor MN14 is turned off to float the elements constituting the logic circuit.

Before the power supply voltage reaches the normal value VDD, the POR signal is low. When the power supply voltage reaches the normal value VDD, the POR signal becomes high.

When the POR signal in the low state is applied to the reset terminal CLR of the D flip-flop 62, the logic control signal SCB in the high state through the output terminal Q of the D flip-flop 62. Is generated and a switch control signal SC in a low state is generated through the inverted output terminal QB of the D flip-flop 62. This state is a sleep mode. Since the switch control signal SC is in a low state, the switching transistor MN14 is turned off, and the virtual ground VGND is disconnected from the ground GND, so that the elements constituting the logic circuit are in a floating state. Since the logic control signal SCB is in a high state, the inverted clock signal CLKB, which is an output signal of the NOR circuit 16, is turned low so that the NMOS transistor MN12 and the NMOS transistor MN13 of the switch unit 20 are turned off. Since the leakage path disappears, the data stored in the latch unit 30 continues to be in the previous state.

When the high POR signal is applied to the reset terminal CLR of the D flip-flop 62, the logic control signal SCB in the low state is generated through the output terminal Q of the D flip-flop 62, and the D flip. The switch control signal SC in a high state is generated through the inverting output terminal QB of the flop 62. This state is the active mode. Since the switch control signal SC is in a high state, the switching transistor MN14 is turned on, and the virtual ground VGND is connected to the ground GND to operate elements constituting a logic circuit. Since the logic control signal SCB is in a low state, the inverted clock signal CLKB, which is an output signal of the NOR circuit 16, becomes high, so that the NMOS transistor MN12 and the NMOS transistor MN13 of the switch unit 20 are turned on. The input data D is transferred to the buffer unit 40.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, the CP flip-flop circuit using the MTCMOS technology according to the present invention includes an initialization circuit to generate a logic control signal and a switch control signal, thereby enabling the circuit to be initialized. Accordingly, the CP flip-flop circuit using the MTCMOS technology according to the present invention can operate stably, reduce leakage current, and operate at high speed.

Claims (4)

In a CP flip-flop circuit using MTCMOS technology comprising a clock delay unit, a switch unit, a latch unit, a buffer unit, and a switching transistor, An initialization circuit for generating a logic control signal and a switch control signal is further provided. In the sleep mode, all logic circuits except for the latch unit are floated. In the active mode, all the logic of the CP flip-flop circuit including the latch unit is included. CP flip-flop circuit using MTCMOS technology, characterized in that the circuit operation. A first inverter for inverting input data; A clock delay unit having a second inverter for inverting a clock signal, a third inverter for inverting an output signal of the second inverter, and an NOR circuit for receiving an output logic and a logic control signal of the third inverter and performing a non-logical sum; A switch unit which receives the input data and the output signal of the first inverter and performs a switching operation under the control of the clock signal and the output signal of the clock delay unit to output the input data and the output signal of the first inverter; A latch unit having a first latch terminal connected to a first output terminal of the switch unit and a second latch terminal connected to a second output terminal of the switch unit to latch an output signal of the switch unit; The fourth inverter having an input terminal connected to the first output terminal of the switch unit and generating inverted output data having a phase opposite to the input data, and the input data having an input terminal connected to the second output terminal of the switch unit; A buffer unit having a fifth inverter for generating output data having a phase equal to that of the buffer; An initialization unit for receiving a power-on reset signal and generating the logic control signal and the switch control signal; And CP flip-flop circuit using the MTCMOS technology characterized in that it comprises a switching transistor connected between the virtual ground and ground and the switching operation by the switch control signal. The method of claim 2, wherein the initialization unit CP flip-flop circuit using a MTCMOS technology characterized in that it comprises a D flip-flop having a reset terminal for receiving a power-on reset signal to generate the logic control signal as an output terminal and a switch control signal to an inverted output terminal. The method of claim 2, wherein the initialization unit And the logic control signal goes low when the power supply voltage reaches a normal value, and the switch control signal goes high.