KR20040040899A - Scan-chain stitching method that can optimize test time in hierarchical design flow - Google Patents

Abstract

PURPOSE: A scan chain stitching method for optimizing a test period of time in a hierarchical design flow is provided to optimize the test period of time by performing correctly a data shifting process between scan blocks. CONSTITUTION: A scan chain includes plural scan chain blocks, which are formed with plural flipflops. The flipflops are operated by different clock signals having clock skews. A double latch lockup cell is formed between a rising-edge-triggered flipflop as the last flipflop of a previous block and a falling-edge-triggered flipflop as the first flipflop of the next block. A data shifting process is performed correctly between scan blocks by forming the double latch lockup cell between the rising-edge-triggered flipflop and the falling-edge-triggered flipflop.

Description

SCAN-CHAIN STITCHING METHOD THAT CAN OPTIMIZE TEST TIME IN HIERARCHICAL DESIGN FLOW} to optimize test time in hierarchical design flows

The present invention relates to a scan chain stitching method, and more particularly to a scan chain stitching method that can optimize test time.

In the hierarchical design flow of the semiconductor chip design, the scan chain design uses a method of stitching at the top level after performing a scan design for each block. Because the scan design is done block by block, timing is achieved by inserting a lockuplatch cell between flip-flops of the same polarity, taking into account clock skews that can occur between two blocks due to different clocks used by each block. Secure a margin. When designing a scan in a hierarchical design flow, make the scan chain length of each block as uniform as possible for scan chain balance at the top level. In general, it is effective to use mixed edges to divide the scan chain evenly. Mixed edges are a way to stitch flip-flops with different polarities into a single chain. When constructing the scan chain for each block using the mixed edge method, the flip-flops with the slower clocks are placed in front of the flip-flops with the faster clocks so that scan path data shifting is achieved within each block. It must be done correctly. There is no problem in scanning design within each block using the mixed edge method, but problems can occur in hierarchical design flows that end scan design within a block and only stitching at the top level. For example, if you design using a Return To Zero (RTZ) clock when data shift is performed from the last flip-flop of the preceding block scan chain to the first flip-flop of the next block scan chain, If the last flip-flop is a rising-edge triggered flip-flop and the first flip-flop of the next block is a falling-edge triggered flip-flop, This method was not used because it would violate the rule of placing flip-flops ahead of flip-flops that use fast clocks to ensure valid data shifting, or incorrect data shifting could occur. Instead, an independent scan chain as shown in FIG. 1 is used, or a no mixed edge method in which the scan chain is composed of only flip-flops having the same polarity as shown in FIG. 2 is used. However, it is not possible to optimize test time because it is difficult to maintain accurate scan chain balance using independent scan chains or using a non-mixed edge method.

In order to solve the above problems, the present invention provides a scan chain by providing a double latch lock-up cell between the last flip-flop of the leading block triggered on the rising edge and the first flip-flop of the trailing block triggered on the falling edge. Shifting of the correct data between blocks is possible, which in turn optimizes the scan test time.

It is an object of the present invention to provide a scan chain stitching method that can optimize test time.

1 is a view for explaining a conventional scan chain design method using an independent scan chain.

2 illustrates a conventional scan chain design method using a single latch lockup cell.

3 is a view illustrating a scan chain design method according to the present invention using a single latch lockup cell and a double latch lockup cell.

4 is a block diagram of a circuit for shifting data by inserting a double latch lockup cell between a test D flip-flop operating on a rising edge and a test D flip-flop operating on a falling edge.

FIG. 5 is a timing diagram illustrating waveforms of main parts when the first clock signal PCLK is earlier than the second clock signal DCLK in FIG. 4.

FIG. 6 is a timing diagram illustrating waveforms of main parts when the second clock signal DCLK is earlier than the first clock signal PCLK in FIG. 4.

<Description of the symbols for the main parts of the drawings>

32, 34, 47: double latch lockup cell

36: single latch lockup cell

41, 42, 45, 46: D flip-flop for test

43, 44: D flip-flop

SC1, SC2, SC3: Scan Chain

Scan chain block: BL11, BL12, BL21, BL22, BL31, BL32

CLK1, PCLK: first clock signal

CLK2, DCLK: second clock signal

SI1, SI2, SI3: Scan input signal

SO1, SO2, SO3: scan output signal

The scan chain stitching method according to the present invention is a hierarchical design flow of a scan chain having scan chain blocks composed of flip-flops operated by different clock signals having a clock skew. By using a double latch lock-up cell between the last flip-flop and the first flip-flop of the next block triggered on the falling edge, correct shifting of data between scan chain blocks is possible.

In the scan chain stitching method according to the present invention, a double latch lock-up cell has a configuration in which a D flip-flop triggered at a rising edge and a D flip-flop triggered at a falling edge are connected in series with each other, and the last block of the leading block triggered at the rising edge is performed. Stitching the first flip-flop of the next block after the trigger on the first flip-flop and the falling edge.

Hereinafter, a scan chain stitching method according to the present invention will be described with reference to the accompanying drawings.

3 is a view illustrating a scan chain design method according to the present invention using a single latch lockup cell and a double latch lockup cell.

If you design a scan using mixed edges, the path from the last end of one block to the first end of the other block will have a rising edge triggered flip-flop to a rising edge triggered flip-flop. There are four cases leading to falling edge trigger flip-flop, leading from falling edge trigger flip-flop to rising edge trigger flip-flop, and falling edge triggered flip-flop to falling edge trigger flip-flop. As such, in order to connect scan chains driven by different clocks to one chain, timing margins should be sufficient in the scan chain between blocks in consideration of clock skew. If the two scan chains consist of only a rising edge or a falling edge flip-flop, a clock margin can be secured simply by using a single latch lockup cell. However, the transition from rising edge triggered flip-flop to falling edge triggered flip-flop between blocks cannot occur in a typical flattened design and is a fast clock with a flip-flop that uses a slower clock during scan ordering. It is against the scan design rules that it must come before a flip-flop that uses s, which makes it difficult to ensure correct data shifting. In this case, since a single latch lockup cell alone is difficult to secure enough timing margin, as shown in FIG. 3, a double latch lockup cell can ensure correct data shifting. Using the scan chain design method according to the present invention shown in FIG. 3 can optimize the balance of the scan chain length to optimize the test time. As shown in Fig. 3, the scan chain SC3 is composed of a block BL31 operated by the clock signal CLK1 and a block BL32 operated by the clock signal CLK2. The double latch lock-up cell 32 connects the last flip-flop (RF, rising edge trigger flip-flop) of the block BL31 and the first flip-flop (FF, falling edge trigger flip-flop) of the block BL32, thereby providing a scan input signal. SI1 is output as the scan output signal SO1. The double latch lock-up cell 34 connects the last flip-flop (RF, rising edge trigger flip-flop) of the block BL31 and the first flip-flop (FF, falling edge trigger flip-flop) of the block BL32, thereby providing a scan input signal. SI2 is output as the scan output signal SO2. The single latch lock-up cell 36 connects the last flip-flop (RF, rising edge trigger flip-flop) of the block BL31 and the first flip-flop (RF, rising edge trigger flip-flop) of the block BL32 to scan input signal. SI3 is output as the scan output signal SO3.

4 is a block diagram of a circuit for shifting data by inserting a double latch lockup cell between a test D flip-flop operating on a rising edge and a test D flip-flop operating on a falling edge. The circuit of FIG. 4 includes a test D flip-flop 41, a first clock signal PCLK, and a first test signal for receiving a first clock signal PCLK and a scan input signal SI and generating a first output signal DO1. A test D flip-flop 42 for receiving a first output signal DO1 and generating a second output signal DO2, a first clock signal PCLK and a second output signal DO2, and receiving a third output signal. D flip-flop 43 for generating DO3, D flip-flop 44 for receiving first clock signal PCLK and third output signal DO3 and generating fourth output signal DO4, second A test D flip-flop 45 for receiving the clock signal DCLK and the fourth output signal DO4 and generating the fifth output signal DO5, and the second clock signal DCLK and the fifth output signal DO5. ) And a test D flip-flop 46 for generating a scan output signal SO.

The test D flip-flops 41 and 42 and the D flip flops 43 and 44 are operated by the first clock signal PCLK, and the test D flip-flops 45 and 46 are operated by the second clock signal. It is operated by (DCLK). The test D flip-flops 41 and 42 and the D flip-flop 44 operate on the rising edge of the clock signal and the test D flip-flops 45 and 46 and the D flip-flop 43 fall the clock signal. It works at the edge. The D flip-flop 43 and the D flip-flop 44 constitute a double latch lock-up cell 47.

FIG. 5 is a timing diagram illustrating waveforms of a main part when the first clock signal PCLK is earlier than the second clock signal DCLK in FIG. 4, and FIG. 6 is a timing diagram showing the second clock signal DCLK in FIG. 4. A timing diagram showing waveforms of main parts when the signal comes before the first clock signal PCLK.

Hereinafter, a scan chain stitching method using a double latch lockup cell according to the present invention will be described with reference to FIGS. 4 to 6.

Without the two latches 43 and 44 constituted by the D flip-flop, the first output signal DO1 to the fifth output signal DO5 may be shifted in one clock cycle to prevent correct data shifting. Also, if only one latch 43 or 44 is present, correct data shifting cannot be performed when there is a clock skew between the first clock signal PCLK and the second clock signal DCLK.

5 and 6 illustrate a case in which a clock signal having a period of 100 ns and a width of 30 ns is applied to the circuit of FIG. 4 and there is 12 ns, or 40% skew, between two clock signals PCLK and DCLK. The waveform is shown as a result of the simulation.

FIG. 5 is a timing diagram when the first clock signal PCLK is faster than the second clock signal DCLK. The rising edge R1 of the first clock signal PCLK changes from the rising edge R1 of the first clock signal PCLK to "high" with respect to the data value "1", and then the falling edge of the second clock signal DCLK ( In the F1), the fifth output signal DO5 of FIG. 5 changes to "high" so that data is shifted only two clocks from the first output signal DO1 of FIG. 4 to the fifth output signal DO5 of FIG. can confirm. For the continuous data value " 0 ", the second output signal DO2 of FIG. 4 is changed to " low " at the rising edge R2 of the first clock signal PCLK, and then the second clock signal DCLK At the falling edge F2, the fifth output signal (DO5 in FIG. 5) changes to "low" so that data is generated in only two clocks from the first output signal (DO1 in FIG. 4) to the fifth output signal (DO5 in FIG. 5). You can see that it is shifting.

FIG. 6 is a timing diagram when the second clock signal DCLK is faster than the first clock signal PCLK, and as shown in FIG. 5, it is understood that correct data is shifted only in two clocks.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, according to the scan chain stitching method according to the present invention, correct data shifting between blocks is possible, thereby optimizing test time.

Claims (4)

In the hierarchical design flow of a scan chain having scan chain blocks composed of flip-flops operated by different clock signals with clock skew, A double latch lock-up cell is provided between the last flip-flop of the leading block triggered on the rising edge and the first flip-flop of the trailing block triggered on the falling edge to ensure correct data shifting between scan chain blocks. Characterized by a scan chain stitching method. The method of claim 1, wherein the double latch lockup cell is The D flip-flop triggered on the rising edge and the D flip-flop triggered on the falling edge have a configuration connected in series with each other, the last flip-flop of the leading block triggered on the rising edge and the first of the trailing block triggered on the falling edge. And stitching the second flip-flop. The method of claim 1 or 2, wherein the scan chain stitching method Further comprising a single latch lockup cell between the last flip-flop of the preceding block triggered on the rising edge and the first flip-flop of the subsequent block triggered on the rising edge. The method of claim 1 or 2, wherein the scan chain stitching method Further comprising a single latch lockup cell between the last flip-flop of the leading block triggered on the falling edge and the first flip-flop of the trailing block triggered on the falling edge.