KR20040040536A - Asic chip - Google Patents

Abstract

PURPOSE: An ASIC(Application Specific Integrated Circuit) chip is provided to change easily an output clock of a PLL module and correct an error of the PLL module by using a PLL register and drawing a clock output pin of the PLL module and a clock input pin of a logic circuit, respectively. CONSTITUTION: An ASIC chip includes a logic circuit(54) and a plurality of PLL modules(52) for providing clocks necessary for the logic circuit(54). The logic circuit is used for storing each parameter value of the PLL modules(52). The logic circuit includes a plurality of PLL registers(10). The PLL registers(10) are connected to the PLL module in order to change the parameter values of the PLL modules. A clock output pin(12) of the PLL module and a clock input pin(14) of the logic circuit are drawn to an outside of an ASIC chip(50).

Description

Application specific integrated circuit chip {ASIC chip}

The present invention relates to an application specific integrated circuit chip, and more particularly, it is possible to easily change the output clock of the phase locked loop module embedded in the application specific integrated circuit, and that the error of the phase locked loop module affects the entire chip. An application specific integrated circuit chip that can be prevented.

Logic circuits designed for application specific integrated circuits (ASICs) usually require more than one clock. In order to receive multiple clocks in this manner, a generally known method is to use multiple oscillators. However, it is difficult to obtain an oscillator with an arbitrary clock, and it is an undesirable method for circuit design to use several oscillators which are relatively expensive.

Thus, most ASIC chips 50 incorporate a number of phase locked loop (PLL) modules 52, as in FIG. The PLL module 52 compares the phase and frequency of a parameter set in itself with respect to a reference clock input from the outside, and outputs a clock required by the logic circuit 54 embedded in the ASIC chip 50. Play a role. The PLL module 52 can be easily used to make a clock of a desired frequency in the ASIC chip 50 by simple parameter setting.

However, after the ASIC chip 50 is completed, the parameter setting value of the PLL module 52 cannot be changed, and changing the reference clock input to the PLL module 52 from the outside of the ASIC chip 50 is a stable clock. Since the generation cannot be guaranteed, the ASIC chip 50 has a problem in that a clock other than the clock determined by the PLL module 52 cannot be used. This places a burden on the user to install an additional oscillator or to replace the ASIC chip 50 when the user needs a higher clock to speed up the operation of the logic circuit 54.

Meanwhile, as shown in FIG. 1, the ASIC chip 50 is connected to the clock output pin of the PLL module 52 and the clock input pin of the logic circuit 54 in the chip 50. Therefore, if an error occurs in the PLL module 52, the logic circuit 54 connected to the PLL module 52 in which the error occurred does not operate normally. If an error occurs in the PLL module 52 that is used as the system clock of the logic circuit 54, a fatal problem is caused that the entire chip cannot be used.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to easily change the clock output from the phase locked loop module and to prevent an error of a specific phase locked loop module from affecting the entire chip. To provide an application specific integrated circuit chip.

1 is a block diagram showing a conventional ASIC chip

2 is a block diagram illustrating an ASIC chip according to the present invention.

3 is a time chart illustrating triggering a software reset in the PLL register of the present invention.

4 is a block diagram illustrating a modified embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10. PLL Register 12. Clock Output Pin of PLL Module

14. Clock input pin of logic circuit 20. PLL mode register

50. ASIC Chip 52. PLL Module

54. Logic Circuit

According to the present invention, in an application specific integrated circuit chip (50) having a logic circuit (54) and a plurality of phase locked loop modules (52) for providing a clock required by the logic circuit (54), The logic circuit 54 stores parameter values of each of the phase-locked loop modules 52 and connects the parameters of the phase-locked loop module 52 connected to the phase-locked loop module 52 and connected to itself by external manipulation. A plurality of phase locked loop registers 10 are provided, and the clock output pins 12 of the phase locked loop module 52 and the clock input of the logic circuit 54 are provided outside the chip 50. An application specific integrated circuit chip is provided, wherein the pin 14 is formed by drawing out.

According to another feature of the invention, the logic circuit 54 is coupled to each phase locked loop register 10 so as to simultaneously set the parameters of each phase locked loop register 10. An application specific integrated circuit chip (20) is provided.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 2 is a block diagram illustrating an application specific integrated circuit chip according to the present invention, FIG. 3 is a time chart illustrating initiating a software reset in a PLL register of the present invention, and FIG. 4 is a modified embodiment of the present invention. The block diagram shown.

Referring to this, the application-specific integrated circuit chip has the same logic circuit 54 and PLL module 52 as in the related art. At this time, the logic circuit 54 is provided with a PLL register 10 for storing the parameters of the PLL module 52, the clock output pin 12 of the PLL module 52 and logic outside the chip 50, The clock input pin 14 of the circuit 54 is pulled out.

The PLL register 10 is connected to correspond to each of the PLL modules 52, and the parameter values of the PLL module 52 are stored in each PLL register 10. As such, the parameters stored in the PLL register 10 may be changed by receiving a control signal from the outside of the ASIC chip 50. The parameter selected by the PLL register 10 by an external signal is transmitted to the PLL module 52, and the PLL module 52 outputs a clock changed according to the reset parameter. At this time, since the output clock value corresponding to the parameter is well known, the user can apply the desired clock to the logic circuit 54 by selecting the parameter in the PLL register 10.

In the PLL module 52, the parameter is changed, and in the process of outputting a new clock, an unstable clock is output for a while, which may cause a malfunction of the logic circuit. Therefore, in the PLL register 10, as in the time chart of FIG. 3, a software reset of 100 ms or more is triggered to compensate for the time taken by the PLL module 52 to output a stable clock. First, when a parameter is changed in the PLL register 10, it is sensed and the notification signal is activated (ST1). When the knotty signal is activated, the S_RES signal for instructing software reset is activated (ST2). When the software reset is activated by the S_RES signal, the knots signal and the S_RES signal are inactive (ST3). After that, a time of 100 ms or more is counted, and the software reset is returned (ST4). This software reset is applied only to the logic circuit 54 using the clock of the PLL module 52 and does not affect the PLL module 52 or the PLL register 10.

The clock output pin 12 of the PLL module 52 and the clock input pin 54 of the logic circuit 54 are each drawn out of the ASIC chip 50. Each pin 12 and 14 drawn out of the chip 50 is interconnected from the outside by the user of the chip 50. As such, the clock output pin 12 of the PLL module 52 and the clock input pin 14 of the logic circuit 54 are designated as external pins of the chip 50 so that an error occurs in a specific PLL module 52. In this case, the clock output pin 12 of the PLL module 52 and the clock input pin 14 of the logic circuit 54 connected thereto are disconnected, and the clock input pin 14 of the logic circuit 54 is disconnected. It can be connected by replacing the external clock. As a result, it is possible to solve the problem that the ASIC chip can no longer be used due to an error in the PLL module 52.

Meanwhile, the PLL mode register 20 is further included in the logic circuit 54 as shown in FIG. 4. This PLL mode register 20 is integrally connected to each PLL register 10 to simultaneously control a plurality of PLL registers 10. Therefore, the user can control only the PLL mode register 20 to obtain a desired clock from each PLL module 52 without having to control each PLL register 10 from the outside. For example, the PLL mode register 20 stores stable parameters, such as [1:50 MHz, 2: 100 MHz, 3: 150 MHz], and the user may select " PLL1: 1, PLL2: 3, PLL3: 2 .. . "May be executed only. As such, the reason for storing only stable parameters in the PLL mode register 20 is that the PLL module 52 operates normally due to unstable parameter settings in a specific PLL register 10 in the process of simultaneously controlling several PLL registers 10. To prevent it from becoming obsolete.

As described above, the ASIC chip according to the present invention may change the clock used by the logic circuit 54 by selecting a parameter of the PLL module 52 stored in the PLL register 10. Accordingly, in order to increase the operation speed of the logic circuit while using the ASIC chip, the output clock of the PLL module 52 may be increased. Also, if the clock output pin 12 of the PLL module 52 and the clock input pin 14 of the logic circuit 54 are drawn out of the chip, and an error occurs in the specific PLL module 52, the corresponding PLL module ( The clock used in 52) can be used by replacing it from the outside. Therefore, there is an advantage that can solve the conventional problem that the entire chip can not be used due to the error of the specific PLL module 52.

As described above, according to the present invention, the clock output from the PLL module can be easily changed by using the PLL register, and the clock output pin of the PLL module and the clock input pin of the logic circuit are drawn out to the outside of the chip, thereby causing errors in the PLL module. It is possible to provide an application-specific integrated circuit chip that can actively cope with the problem.

Claims (2)

In an application specific integrated circuit chip 50 having a logic circuit 54 therein and a plurality of phase locked loop modules 52 that provide a clock required by the logic circuit 54, the logic circuit 54 is provided. The parameter values of each of the phase locked loop modules 52 are stored, and each of the plurality of phase locked loop modules 52 is connected to the phase locked loop module 52 so that the parameters of the phase locked loop module 52 connected to itself by external manipulation can be changed. The phase locked loop register 10 is provided, and the clock output pin 12 of the phase locked loop module 52 and the clock input pin 14 of the logic circuit 54 are external to the chip 50. Application-specific integrated circuit chip, characterized in that the draw is formed. 2. The phase locked loop mode register (20) of claim 1, wherein said logic circuit (54) is integrally connected to each phase locked loop register (10) to enable simultaneous setting of the parameters of each phase locked loop register (10). Application-specific integrated circuit chip characterized in that it is provided.