KR20040036068A - Magnetic random access memory and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A magnetoresistive RAM and its fabrication method are provided to simplify its process and to improve memory characteristics using a JFET(Junction Field Effect Transistor) realized on a SOI(Silicon On Insulator). CONSTITUTION: A JFET(Junction Field Effect Transistor)(24) is formed on an upper part of a SOI(Silicon On Insulator) substrate with a source(27), a drain(28) and a silicon substrate(26). A read word line(21) is formed on the silicon substrate. A contact line(29) is formed on the drain of the JFET. A MTJ(Magnetic Tunnel Junction) cell(20) is stacked on the contact line. A bit line(22) is formed on the MTJ cell and is comprised on an upper side of the read word line. And a write word line(23) is formed on an upper part of the bit line.

Description

Magnetoresistive ram and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetoresistive ram and a method of manufacturing the same, and to a magnetoresistive ram and a method of manufacturing the same to improve the cell structure of the magnetoresistive ram, simplify the process, and improve memory speed.

Currently, most semiconductor memory manufacturers are one of the next generation memory devices, and actively participate in the development of magnetoresistive RAMs using ferromagnetic materials.

The magnetoresistive RAM is a memory device that reads and writes data by forming ferromagnetic thin films in multiple layers and senses the current change according to the magnetization direction of each thin film layer. A device capable of operating a nonvolatile memory such as a memory.

Research on this is currently in its infancy, mainly focused on the formation of multilayer magnetic thin films, and studies on unit cell structures and peripheral sensing circuits are still insufficient.

1 is a cross-sectional view of a MTJ (Magnetic Tunnel Junction) cell as a multilayer magnetic thin film structure in which data is stored in such a conventional magnetoresistive RAM.

In general, the MTJ cell 5 is formed of an anti-ferroelectric thin film 1, a fixed layer ferromagnetic thin film 2, a thin insulating layer 3 through which a tunneling current flows, and a free layer ferromagnetic thin film 4.

Here, the fixed layer ferromagnetic thin film 2 has a magnetization direction fixed in one direction, and the diamagnetic thin film 1 serves to fix the magnetization direction of the fixed layer ferromagnetic thin film 2 unchanged. On the other hand, the magnetization direction of the free layer ferromagnetic thin film 4 is changed by an external magnetic field, and data of "0" or "1" can be stored according to the magnetization direction of this layer.

When a current flows in the direction perpendicular to the MTJ cell 5, a tunneling current through the insulating layer is generated. At this time, if the magnetization directions of the fixed layer ferromagnetic thin film 2 and the free layer ferromagnetic thin film 4 are the same, the magnitude of the tunneling current is large. There is a small tunneling current flowing through it.

This phenomenon is called TMR (Tunneling Magnetoresistance) effect. By detecting the magnitude of this tunneling current, the magnetization direction of the free layer ferromagnetic thin film 4 can be known and the data stored in the cell can be read.

2A illustrates an embodiment in which a cell of a magnetoresistive RAM is implemented using a field effect transistor.

The unit cell of the magnetoresistive RAM includes one horizontal structure field effect transistor (Metal-Oxide-Silicon Field Effect Transistor) 9, an MTJ cell 5, a read word line 6 used for reading data, and a current. Write word line 8 and perpendicular to the MTJ cell 5 to form an external magnetic field upon application of the data to store data in accordance with the change in the magnetization direction of the free layer ferromagnetic thin film 4 in the MTJ cell 5. And a bit line 7 for applying a current in the direction so that the magnetization direction of the free layer ferromagnetic thin film 4 can be known.

The conventional magnetoresistive RAM having such a configuration applies a voltage to the read word line 6 at the time of read operation to operate the field effect transistor 9 and applies a current to the bit line 7 to the MTJ cell 5. Detect the magnitude of the current flowing.

In addition, the MTJ cell 5 free layer is caused by an external magnetic field generated by applying a current to the write word line 8 and the bit line 7 while keeping the field effect transistor 9 in the off state during writing. Changes the magnetization direction.

The reason why the current is simultaneously applied to the bit line 7 and the write word line 8 is that the magnetic field is generated at the point where the two metal lines vertically cross each other, thereby selecting one cell among several cell arrays. Because it can.

FIG. 2B is a cross-sectional view of the magnetoresistive ram corresponding to the conventional magnetoresistive ram cell of FIG. 2A.

The ground line 12 is formed on the source 10 of the horizontal structure transistor 9, the read word line 6 is formed on the gate, and the conductive layer 13 and the contact are formed on the drain 11. The plug 14, the conductive layer 15, and the contact plug 16 are sequentially formed. The connection layer 17 is formed on the write word line 8, and the MTJ cell 5 and the bit line 7 are formed on the connection layer 17 in a stack form.

2C shows an equivalent circuit diagram of a conventional magnetoresistive ram using a field effect transistor.

2C shows the MTJ 5 of FIG. 2A as a variable resistor r according to the stored data, and the current Ids flows between the drain and the source when the gate voltage VG of the field effect transistor 9 is applied.

However, one of the problems of the conventional field effect transistor is that the presence of a capacitor due to the gate oxide causes a delay in the on / off speed of the device, which may degrade the AC characteristics of the magnetoresistive ram. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to improve the memory characteristics while simplifying the process by using a junction field transistor (JFET) implemented in a silicon on insulator (SOI) substrate.

1 is a cross-sectional view of a conventional MTJ cell.

2A, 2B and 2C are schematic, sectional and equivalent circuit diagrams of a magnetoresistive ram using a conventional horizontal field effect transistor;

3A, 3B and 3C are schematic, cross-sectional and equivalent circuit diagrams of a magnetoresistive ram according to the present invention.

4A-4E are process flow diagrams illustrating a method of manufacturing a magnetoresistive ram according to the present invention.

5 is another embodiment of a magnetoresistive RAM according to the present invention using a field effect transistor implemented on an SOI substrate.

6 is another embodiment of a magnetoresistive RAM according to the present invention using a bipolar junction transistor of vertical structure implemented in an SOI substrate.

7 is another embodiment of a magnetoresistive RAM according to the present invention using a bipolar junction transistor of a horizontal structure implemented on an SOI substrate.

The magnetoresistive RAM of the present invention for achieving the above object is a JFET formed of a source, a drain and a silicon substrate on top of the SOI substrate, a read word line formed on the silicon substrate and a contact line formed on the drain of the JFET And a MTJ cell stacked on the contact line, a bit line formed on the read word line, and a write word line formed on the bit line.

In addition, the method of manufacturing a magnetoresistive RAM according to the present invention includes a process of performing active patterning by diffusing impurities or implanting ions into a silicon substrate formed on an insulator, forming a source region and a drain region on the silicon substrate, and Forming a mask layer over the substrate, forming a P + gate region over the silicon substrate, depositing an interlayer insulating film over the silicon substrate, the source and drain regions, and forming an electrode over the interlayer insulating film And forming a contact line, an MTJ cell, a bit line, and a word line on the drain region.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

Figure 3a shows the structure of a magnetoresistive ram according to the present invention.

The magnetoresistive RAM of the present invention includes a junction field effect transistor (JFET) 24 implemented in a silicon on insulator (SOI), an MTJ cell 20, a read word line 21 used for reading data, and a current. The write word line 23 and the perpendicular current to the MTJ cell 20 and the write word line 23 to form an external magnetic field upon application of the data to store data according to a change in the magnetization direction of the free layer ferromagnetic thin film in the MTJ cell 20. It is provided with a bit line 22 to determine the magnetization direction of the free layer ferromagnetic thin film by applying a.

3B is a cross-sectional view of the magnetoresistive ram according to the present invention corresponding to FIG. 3A.

According to the present invention, a JFET 24 formed of a source 27, a drain 28, and a silicon substrate 26 is formed on an insulator 25, and a read word is formed on the silicon substrate 26. Line 21 is formed. The contact line 29 is formed on the drain 28, and the MTJ cell 20 is stacked on the contact line 20.

In addition, a bit line 22 is formed on the MTJ cell 20, and a write word line 23 is formed on the bit line 22.

3C shows an equivalent circuit diagram of a magnetoresistive RAM of the present invention using a JFET implemented in SOI.

3C shows the MTJ of FIG. 3A as a variable resistor r according to the stored data, and uses the JFET 24 implemented in the SOI substrate.

The present invention having such a configuration looks at the voltage applied to the gate of the JFET 24 when using the N-channel JFET 24 as follows.

First, when data is held, a negative value is applied to the gate of the JFET 24. In this case, the channel is depleted in reverse bias so that no current flows to the drain and source terminals of the JFET 24.

In the read / write operation, a voltage of 0 V is applied to the gate of the JFET 24. In this case, the JFET 24 is turned on so that a current flows between the drain and the source according to the data written in the MTJ cell 20.

In the present invention, when the JFET 24 is implemented in a general silicon substrate, reverse leakage current occurs between the channel region and the substrate, and when the junction area is large, problems may occur in the stand-by power supply. . Therefore, in the present invention, since the JFET 24 is implemented using a silicon on insulator (SOI), it is possible to realize high speed and high density of the magnetoresistive ram by reducing the leakage current in the off state.

In addition, the present invention can simplify the process by using a simple JFET forming process, and because the gate insulating film forming process of the MOSFET is excluded, it is possible to improve the operation speed due to the reduction of the capacitance by the gate insulating film.

4A to 4E illustrate a method of manufacturing the magnetoresistive ram according to the present invention.

First, in the processes of FIGS. 4A and 4B, when the JFET 24 of the present invention is an N-channel, N-type impurities are diffused or ions are implanted into the N-type silicon substrate 26 formed on the insulator 25. Active patterning is performed.

In the process of FIG. 4C, the N + source region 27 and the N + drain region 28 are formed on the N-type silicon substrate 26, and the mask layer 30 is formed.

In the process of FIG. 4D, a P + gate region is formed on the N-type silicon substrate 26. In this case, the P + type doped polysilicon or amorphous silicon is deposited with the plug material when forming the gate contact without implanting ions or performing a diffusion process to form the P + gate.

Subsequently, the heat treatment process may simplify the process and may form shallow gate junctions. In addition, the formation of the source 27 and the drain 28 has the same process.

Next, FIG. 4E shows a process of depositing an insulating layer 31, which is an interlayer dielectric (ILD), on the silicon substrate 26, the source 27, and the drain 28. To form. Thereafter, contact line 29, MTJ 20 and bit line 22 and write word line 33 are formed on top of drain 28 of N-channel SOI JFET 24.

In the present invention, only the manufacturing process of the MRAM using the N-channel SOI JFET is described, but the P-channel SOI JFET is equally applicable. In this case, however, the gate voltage is the same as 0 V during the read / write operation, but the channel is depleted only when a positive value is applied to the gate during data retention.

In the present invention, a semiconductor device (transistor / diode, etc.) is fabricated on an SOI substrate and used as a cell switching device as a method for implementing a high performance MRAM cell with a simple process.

In this case, when using an SOI substrate, it is possible to apply a combination of a field effect transistor (JFET), a bipolar junction transistor (BJT), and a field effect transistor (MOSFET) widely used as a switching device. In addition, the combination of these devices in the implementation of peripheral drive circuits enables the fabrication of high-performance MRAMs combining BiCMOS and MTJ.

5 is a cross-sectional view of a magnetoresistive RAM using field effect transistor MOSFETs implemented on an SOI substrate.

In the embodiment of FIG. 5, a horizontal structure transistor including a gate 33, a source 34, and a drain 35 is formed on an insulator 32, and a ground line is formed on the source 34 of the horizontal structure transistor. 36) is formed. The read word line 37 is formed on the gate 33, and the conductive layer 38, the contact plug 39, the conductive layer 40, and the contact plug 41 are formed on the drain 35. It is formed in turn. In addition, the connection layer 42 is formed on the write word line 43, and the MTJ cell 44 and the bit line 45 are formed on the connection layer 42 in a stack form.

6 is a cross-sectional view of a magnetoresistive RAM using a BJT having a vertical structure implemented on an SOI substrate.

In the embodiment of FIG. 6, the N + collector region 47 and the silicon substrate 49 are formed on the insulator 46, and the N-collector region 48 and the N type emitter are formed on the silicon substrate 49. Region 50 is formed. A ground line 52 is formed on the N-type emitter region 50.

In addition, a P-type base region 51 is formed on the N-collector region 48, a contact line 53 is formed on the P-type base region 51, and an upper portion of the contact line 53 is formed. MTJ cells 54 are stacked. The bit line 55 is formed on the MTJ cell 54, and the write word line 56 is formed on the bit line 55.

As described above, there may be difficulty in controlling the junction depth of the emitter in manufacturing the BJT of the vertical structure. Thus, without forming doped emitters by forming shallow emitter junctions, n + doped polysilicon is deposited with a plug material at the time of emitter contact formation, followed by a heat treatment process. Simplified.

FIG. 7 is a cross-sectional view of a magnetoresistive ram using a BJT having a horizontal structure implemented on an SOI substrate.

In the embodiment of FIG. 7, an N + collector region 59, a P type base region 58, and an N type emitter region 60 are formed on the insulator 57.

A P-type base (Base of Bipolar Junction Transistor) region 61 is formed on the P-type base (Base of Lateral Bipolar Junction Transistor) region 58, and a contact line is formed on the P-type base region 61. 63 is formed.

In addition, the MTJ cell 64 is stacked on the contact line 63, the bit line 65 is formed on the MTJ cell 54, and the write word line 66 is formed on the bit line 65. Is formed.

As described above, the present invention is advantageous for the high speed of the memory due to the reduction of the parasitic capacitance of the transistor by the use of the gate oxide capacitance and the SOI substrate, and by simplifying the process by reducing the off-state leakage current of the JFET by using the SOI substrate. It provides the effect of improving memory characteristics.

Claims (9)

A JFET formed of a source, a drain, and a silicon substrate on top of the SOI substrate; A read wordline formed on the silicon substrate; A contact line formed on the drain of the JFET; An MTJ cell stacked on top of the contact line; A bit line formed on the MTJ cell and provided above the read word line; And And a write word line formed on the bit line. The method of claim 1, wherein the JFET And a channel region is formed in the silicon substrate using an ion implantation and diffusion process. The method of claim 1, wherein the JFET Magnetoresistive RAM, which deposits P + doped polysilicon with a plug material when forming a gate contact. The method of claim 1, wherein the JFET A magnetoresistive RAM comprising depositing amorphous silicon with a plug material when forming a gate contact. A field effect transistor formed on the SOI substrate as a source, a gate and a drain region; A read wordline formed in a gate region of the field effect transistor; A ground line formed in the source region of the field effect transistor; A write word line provided above the ground line; A connection layer formed in the drain region of the field effect transistor and disposed above the write word line; And And a MTJ cell interposed between the connection layer and the bit line and disposed above the source region. A BJT having a vertical structure in which an N + collector region and a silicon substrate are formed on the SOI substrate, and the N-collector region and an N-type emitter region are formed on the silicon substrate; A P-type base region formed on the N-collector region; A ground line formed over the N-type emitter region; A contact line formed on the P-type base region; An MTJ cell stacked on top of the contact line; And And a word line formed between the MTJ cell and the bit line. A horizontal structure BJT formed of an N + collector region, a P type base region and an N type emitter region on top of the SOI substrate; A P-type base region of a bipolar junction transistor formed on the P-type base region; A contact line formed on the P-type base region of the bipolar junction transistor; An MTJ cell stacked on top of the contact line; And And a word line formed between the MTJ cell and the bit line. Performing active patterning by diffusing impurities or implanting ions into the silicon substrate formed on the insulator; Forming a source region and a drain region on the silicon substrate, and forming a mask layer on the silicon substrate; Forming a P + gate region on the silicon substrate; Depositing an interlayer insulating film over the silicon substrate, the source and drain regions; Forming an electrode on the interlayer insulating film; And And forming a contact line, an MTJ cell, a bit line, and a word line on the drain region. The method of claim 8, wherein the P + gate forming process is performed. And depositing polysilicon doped with P + type with a plug material and performing heat treatment when forming the gate contact.