KR20040035989A - Method of forming non-volatile memory device - Google Patents

Abstract

PURPOSE: A method for forming a non-volatile memory device is provided to be capable of preventing the characteristic difference between unit cells. CONSTITUTION: A tunnel insulating layer(103) and a lower conductive layer are sequentially formed on a semiconductor substrate(101). Supporter patterns are formed on the lower conductive layer. A spacer is formed at both sidewalls of each supporter pattern. A capping layer(111a) is formed at both sides of each supporter pattern on the lower conductive layer. The lower conductive layer is partially exposed by etching the spacers. The semiconductor substrate is partially exposed by selectively etching the exposed lower conductive layer and the tunnel insulating layer using the supporter pattern and the capping layer as an etching mask. At this time, a plurality of gaps are formed at the resultant structure. A control gate isolating layer is formed at the inner portion of each gap. Then, each gap is completely filled with a control gate electrode(119b).

Description

Method of forming non-volatile memory device

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a nonvolatile memory device.

Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. The volatile memory device is a memory device that loses all data stored in a memory cell when the power supply is interrupted. For example, the DRAM memory device and the SRAM memory device are included. In contrast, the nonvolatile memory device is a memory device that retains data stored in a memory cell even when power supply is interrupted, for example, a flash memory device. The flash memory device includes a floating gate electrode that stores data and a control gate electrode that selects a unit cell or erases or programs data of the floating gate electrode. The flash memory device may be classified into a flash memory device having a split gate structure and a flash memory device having a stacked gate structure.

1 to 3 are cross-sectional views illustrating a method of forming a flash memory device having a conventional split gate structure.

Referring to FIG. 1, a tunnel oxide film 2, a floating gate conductive film 3, and a hard mask film 4 are sequentially formed on a semiconductor substrate 1. The tunnel oxide layer 2 is formed of a thermal oxide layer, and the floating gate conductive layer 3 is formed of a doped polysilicon layer. The hard mask film 4 is formed of a silicon nitride film.

The hard mask film 4 is patterned to form a pair of openings 5 exposing a predetermined region of the floating gate conductive film 3, and the floating gate conductive film exposed to each of the openings 5 ( A capping film 6 is formed on 3). The capping film 6 is formed of a thermal oxide film. At this time, the thermal oxide film 6 becomes thinner toward the edge of the opening 6 due to bird's beak.

2 and 3, the hard mask layer 4 is etched and removed until the floating gate conductive layer 3 is exposed. Using the capping layer 6 as a mask, the floating gate conductive layer 3 and the tunnel oxide layer 2 are sequentially etched and sequentially stacked until the semiconductor substrate 1 is exposed, and the tunnel oxide layer pattern 2a is sequentially stacked. And floating gate electrode 3a.

The control gate insulating film 7 and the control gate conductive film 8 are sequentially formed on the entire surface of the semiconductor substrate 1 having the pair of floating gate electrodes 3a. The control gate insulating film 7 is formed of a silicon oxide film, and the control gate conductive film 8 is formed of a doped polysilicon film.

The photosensitive film pattern 9 is formed on the control gate conductive film 8. The control gate conductive layer 8 and the control gate insulating layer 7 are successively patterned using the photoresist pattern 9 as a mask to form left and right control gate patterns 10a and 10b. Each of the left and right control gate patterns 10a and 10b is disposed on an upper surface of the semiconductor substrate 1 and the floating gate electrode 3a. Surfaces of the semiconductor substrate 1 under the left and right control gate patterns 10a and 10b correspond to the left and right control gate channels 11a and 11b, respectively. The left gate pattern 10a includes a left control gate pattern 7a and a left control gate electrode 8a that are sequentially stacked, and the right gate pattern 10b is a right control gate insulating layer pattern 7b that is sequentially stacked, and It consists of the right control gate electrode 8b. The common source region 12 is formed by implanting impurity ions into the semiconductor substrate 1 between the pair of floating gate electrodes 3a.

The left and right control gate patterns 10a and 10b are symmetrically arranged with each other. In other words, the left and right control gate channels 11a and 11b are disposed on opposite sides of the pair of floating gate electrodes 3a on which the common source region 12 is disposed.

In the above-described conventional technique, when misalignment occurs when the photoresist pattern 9 is formed, the channel lengths k1 and k2 of the left and right control gate channels 11a and 11b may be changed. In particular, the left and right control gate channels 11a and 11b may be symmetrically disposed so that the difference between the channel lengths k1 and k2 may be further increased. For example, if the photoresist pattern 9 has a 0.1um misalignment leftward, the channel length k1 of the left control gate channel 11 decreases by 0.1um, whereas the right control gate channel 11 The channel length (k2) of increases by 0.1um. As a result, the difference in the channel length between the left and right channel lengths k1 and k2 may be 0.2 um so that the amount of current flowing through the left and right control gate channels 11a and 11b may vary. As a result, a characteristic difference between the left and right cells having the left and right control gate channels 11a and 11b may occur.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of forming a nonvolatile memory device capable of preventing a difference in characteristics of unit cells caused by misalignment of a photoresist pattern.

1 to 3 are cross-sectional views illustrating a method of forming a flash memory device having a conventional split gate structure.

4 through 9 are cross-sectional views illustrating a method of forming a nonvolatile memory device according to an exemplary embodiment of the present invention.

To provide a method of forming a nonvolatile memory device for solving the above technical problem. The method includes the steps of sequentially forming a tunnel insulating film and a lower conductive film on a semiconductor substrate. Supporter patterns are formed on the lower conductive layer, and spacers are formed on both sidewalls of the supporter patterns, respectively. A capping layer is formed on the lower conductive layer on both sides of the supporter pattern having the spacers, and the spacer is removed by an etching process to expose the lower conductive layer under the spacer. The exposed lower conductive layer and the tunnel insulating layer are etched using the supporter pattern and the capping layer as a mask until the semiconductor substrate is exposed to form a first lower conductive layer pattern below the supporter pattern and a second lower portion below the capping layer. A gap is formed between the conductive layer pattern and the first and second lower conductive layer patterns. A control gate insulating film is formed on sidewalls and bottoms of the gap, and a control gate electrode is formed on the control gate insulating film.

Specifically, the lower conductive layer may be formed of a doped polysilicon layer, and the supporter pattern may be formed of a material layer having an etching selectivity with respect to the lower conductive layer. The spacer may be formed of a material layer having an etching selectivity with respect to the supporter pattern and the lower conductive layer pattern.

A preferred method of forming the control gate electrode includes forming an upper conductive film filling the gap on the entire surface of the semiconductor substrate. The upper conductive layer is planarized until the supporter pattern is exposed to form an upper conductive layer pattern on the capping layer. The upper conductive layer pattern, the capping layer, and the second lower conductive layer pattern are successively patterned to form a floating gate electrode, a capping layer pattern, and a control gate electrode which are sequentially stacked.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

4 through 9 are cross-sectional views illustrating a method of forming a nonvolatile memory device according to an exemplary embodiment of the present invention.

4 and 5, the tunnel insulating film 103, the lower conductive film 105, and the supporter film 107 are sequentially formed on the semiconductor substrate 101. The tunnel insulating film 103 may be formed of a thermal oxide film. The lower conductive layer 105 may be formed of a conductive layer, for example, a doped polysilicon layer. The supporter layer 107 may be formed of a material layer having an etching selectivity with respect to the lower conductive layer 105, for example, a silicon oxide layer. Alternatively, the supporter layer 107 may be formed of a stacked silicon oxide layer and a silicon nitride layer. The supporter layer 107 is patterned to form the supporter patterns 107a until the lower conductive layer 105 is exposed. Spacers 109 are formed on both sidewalls of the supporter pattern 107a. The spacer 109 is formed in a general manner. That is, a spacer film (not shown) is formed on the entire surface of the semiconductor substrate 101 having the supporter pattern 107a, and the spacer film is anisotropically etched to form the spacer 109 on both sidewalls of the supporter pattern 1007a. To form. The spacer 109 may be formed of a material film having an etching selectivity with respect to the supporter pattern 107a and the lower conductive film 105, for example, a silicon nitride film. A capping layer 111 is formed on the lower conductive layer 105 on both sides of the supporter pattern 107a having the spacer 109. The capping film 111 may be formed of a thermal oxide film.

6 and 7, the spacer 109 is etched and removed from the semiconductor substrate 101 having the capping layer 111. In this case, the lower conductive layer 105 under the spacer 109 is exposed. Using the supporter pattern 107a and the capping layer 111 as a mask, the exposed lower conductive layer 105 and the tunnel insulating layer 103 are continuously etched until the semiconductor substrate 101 is exposed. Accordingly, a first lower conductive layer pattern 113 and a second lower conductive layer pattern 115 under the capping layer 111 are formed under the supporter pattern 107a. In this case, a gap G is formed between the first and second lower conductive layer patterns 113 and 115. The width of the gap G is determined due to the lower width of the spacer 109. For this reason, the widths of the gaps G may be formed to be constant. A control gate insulating layer 117 is formed on inner walls and bottoms of the gap G, that is, sidewalls of the first and second lower conductive layer patterns 113 and 115 and the exposed semiconductor substrate 101. The control gate insulating film 117 is preferably formed of a thermal oxide film. The control gate insulating layer 117 also serves to heal the inner wall and the bottom of the gap G damaged by an etching process when the first and second lower conductive layer patterns 113 and 115 are formed. An upper conductive layer 119 is formed on the entire surface of the semiconductor substrate 101 having the control gate insulating layer 117 to fill the gap G. Preferably, the upper conductive layer 119 is formed to have a sufficient thickness so as to fill all of the supporter patterns 107a. The upper conductive layer 119 may be formed of a conductive layer, for example, a doped polysilicon layer.

The upper conductive layer 119 is planarized until the supporter pattern 107a is exposed to form the upper conductive layer pattern 119a. The upper conductive layer pattern 119a is interposed between the supporter patterns 107a and covers the second lower conductive layer pattern 115 and the capping layer 111. That is, the upper conductive layer pattern 119a fills the pair of gaps G disposed on both sides of the second lower conductive layer pattern 115. Between the upper conductive layer pattern 119a and the first lower conductive layer pattern 113, between the upper conductive layer pattern 119a and the second lower conductive layer pattern 115 and the upper conductive layer pattern 119a. The control gate insulating layer 117 is interposed between the semiconductor substrate 101 and the semiconductor substrate 101.

8 and 9, in the semiconductor substrate 101 having the upper conductive layer pattern 119a, the supporter pattern 107a is etched and removed until the first lower conductive layer pattern 113 is exposed. do. The exposed first lower conductive layer pattern 113 is removed by isotropic etching until the tunnel insulating layer 103 is exposed to form the first exposed region 120. The first exposed area 120 is an area between the upper conductive layer patterns 119a. The control gate insulating layer 117 formed on the sidewalls of the tunnel insulating layer 103 and the first lower conductive layer pattern 113 in the first exposure area 120 may be etched and removed. A portion of the upper conductive layer pattern 119a may be etched while the first lower conductive layer pattern 113 is etched and removed.

The photosensitive film pattern 121 is formed on the semiconductor substrate 101 having the first exposure area 120. The photoresist layer pattern 121 exposes a predetermined region of the upper conductive layer pattern 119a positioned above the center portion of the capping layer 111. In other words, the photoresist pattern 121 covers the upper conductive layer pattern 119a and the first exposed region 120 filling the gaps G and the upper sides of the capping layer 111.

The exposed upper conductive layer pattern 119a, the capping layer 111, and the second lower conductive layer pattern 115 are continuously patterned until the tunnel insulating layer 103 is exposed to form a second exposed region 122. To form. A pair of gate patterns 130 are formed at both sides of the second exposed region 122. The gate pattern includes a floating gate electrode 117a, a capping layer pattern 111a, and a control gate electrode 119b that are sequentially stacked. In this case, the upper conductive layer pattern 119a is formed of the control gate electrode 119b, the capping layer 111 is formed of the capping layer pattern 111a, and the second lower conductive layer pattern 115 is formed. Is formed of the floating gate electrode 115a.

The pair of gate patterns 130 has a symmetrical structure with respect to the second exposed region 122. That is, one side wall of the gate pattern 130 adjacent to the second exposure area 122 includes the floating gate electrode 115a, the capping layer pattern 111a, and the control gate electrode 119b. Unlike this, the other side wall of the gate pattern 130 adjacent to the first exposure area 120 is configured of the control gate electrode 119b.

The channel region of the control gate electrode 119a is determined by the gap G. The gaps G are determined by the bottom width of the spacer 109 on both sidewalls of the supporter pattern 107a of FIG. 5. Accordingly, the difference between the channel lengths L1 and L2 of the pair of control gate electrodes 119a disposed on the left and right sides of the second exposure region 122 can be minimized. In other words, in determining the channel length L1 or L2 of the control gate electrode 130a, no longitudinal photosensitive film pattern is required. As a result, it is possible to prevent a phenomenon in which the channel length of the control gate electrodes is increased or decreased due to the misalignment of the conventional photoresist pattern. As a result, characteristic differences between unit cells of the nonvolatile memory device due to the difference in the channel lengths L1 and L2 can be prevented.

Gate spacers 123 are formed on both sidewalls of the gate pattern 130. Impurity ions are selectively implanted into the semiconductor substrate 101 of the first and second exposure regions 120 and 122 to form first and second impurity diffusion layers 125a and 125b, respectively. The first impurity diffusion layer 125a may correspond to a drain region and the second impurity diffusion layer 125b may correspond to a source region. The first and second impurity diffusion layers 125a and 125b may be simultaneously formed. Alternatively, the first and second impurity diffusion layers 125a and 125b may be sequentially formed.

As described above, according to the present invention, the photosensitive film pattern for determining the channel region of the control gate electrode is not required. In other words, a supporter pattern and spacers on both sidewalls of the supporter pattern are used to define the channel region of the control gate electrode. As a result, it is possible to prevent a phenomenon in which channel lengths of the control gate electrodes are different due to the misalignment of the conventional photoresist pattern. As a result, the characteristic difference between unit cells due to the channel length difference can be minimized.

Claims (7)

Sequentially forming a tunnel insulating film and a lower conductive film on the semiconductor substrate; Forming supporter patterns on the lower conductive layer; Forming spacers on both sidewalls of the supporter patterns; Forming a capping layer on the lower conductive layer on both sides of the supporter pattern having the spacers; Removing the spacers by an etching process to expose the lower conductive layer under the spacers; The exposed lower conductive layer and the tunnel insulating layer are etched using the supporter pattern and the capping layer as a mask until the semiconductor substrate is exposed to form a first lower conductive layer pattern below the supporter pattern and a second lower portion below the capping layer. Forming a gap between the conductive layer pattern and the first and second lower conductive layer patterns; Forming a control gate insulating layer on sidewalls and bottoms of the gap; And Forming a control gate electrode filling the gap on the control gate insulating film. The method of claim 1, And the lower conductive layer is formed of a doped polysilicon layer. The method of claim 1, And the supporter pattern is formed of a material film having an etch selectivity with respect to the lower conductive film. The method of claim 1, The spacer is formed of a material film having an etch selectivity with respect to the supporter pattern and the lower conductive layer pattern. The method of claim 1, And the capping film is formed of a thermal oxide film. The method of claim 1, Forming the control gate electrode, Forming an upper conductive film filling the gap on the entire surface of the semiconductor substrate; Planarizing the upper conductive layer until the supporter pattern is exposed to form an upper conductive layer pattern on the capping layer; And sequentially patterning the upper conductive layer pattern, the capping layer, and the second lower conductive layer pattern to form a floating gate electrode, a capping layer pattern, and a control gate electrode that are sequentially stacked. Formation method of the device. The method of claim 6, Before patterning the upper conductive film pattern, And removing the supporter pattern and the first lower conductive layer pattern by etching.