KR20040035214A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to reduce a layout area by reducing a track area occupied by a data line. CONSTITUTION: A plurality of bit line groups comprise a plurality of bit line pairs respectively. A plurality of data line groups comprise a plurality of data line pairs respectively. A plurality of memory cells are connected to the plurality of bit line pairs and a plurality of word lines and a plurality of scan word lines and scan lines. Data driving units(31,32) generate data by driving input data and then transmit the data to the plurality of data lines(dl1,dl2,dl3,dl4) of the plurality of data line groups. Inversion data driving units invert transmitted data and then transmit the inverted data to each of the plurality of inversion data lines(ndl1,ndl2,ndl3,ndl4). A multiplexer(34) transmits the data and the inversion data transmitted from the plurality of data line groups to the plurality of bit line pairs in response to each of a plurality of selection signals. And a scan data output part(35) outputs the data transmitted through the scan line as scan data.

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, which reduces the area overhead of a track portion through which a data line of a semiconductor memory passes, thereby reducing the layout of the entire semiconductor memory device.

Here, the data line refers to a path for transmitting write data. The area of the track through which the data line passes is determined by the number of data lines, and the area overhead of the semiconductor memory is determined by the track area.

FIG. 1 shows the structure of a conventional semiconductor memory device, and is composed of write drivers 11 and 12, multiplexer 14, and scan data output unit 15. FIG.

FIG. 1 shows a plurality of multiplexers (mux1), a third multiplexer (mux3), and a second multiplexer for responding to the plurality of multiplexer signals mux signal1 and mux signal2 for each write driver 11 and 12. (mux2) and the fourth multiplexer mux4 are arranged adjacent to each other, so that the plurality of memory cells are also the first memory cells mc1-1 to mc1-n and the third memory cells mc3-1 to mc3-n. ), Second memory cells mc2-1 to mc2-n, and fourth memory cells mc4-1 to mc4-n.

The operation of the semiconductor memory device arranged as described above is as follows.

The write drivers 11 and 12 generate inverted data ndata1 and ndata2 through the first inverters I1 and I3 when the input data DI [1] and DI [2] are transmitted, and the second inverters I2, Through data I4), data data1 and data2 are generated. The plurality of data data1 and data2 and the inverted data ndata1 and ndata2 are transmitted through the data lines dl1, dl2, dl3 and dl4 and the inverted data lines ndl1, ndl2, ndl3 and ndl4, respectively.

The multiplexer 14 may transmit data (data1, data2) and inverted data (ndata1) transmitted through a plurality of data lines (dl1, dl2, dl3, and dl4) and a plurality of inverted data lines (ndl1, ndl2, ndl3, and ndl4). , ndata2 is transmitted to a plurality of bit line pairs bl1, nbl1 to bl4, nbl4 selected according to the multiplexer selection signal values mux signal1 and mux signal2.

The plurality of memory cells mc1-1 to mc4-n write the transferred data data1 and data2 and the inverted data ndata1 and ndata2 to the memory cells in response to the selection signal of the word line WL. The value of the stored memory cell is output to the scan output unit 15 through the scan lines sl1, sl2, sl3, sl4 in response to the selection signal of the scan word line SWL.

As described above, in the case of the conventional example semiconductor memory device, the multiplexers mux1 and mux3 (mux2) for responding to the multiplexer signals mux signal1 and mux signal2 for each write driver 11 and 12. , mux4) are arranged adjacent to each other so that only the number of tracks for passing the data lines as many as the input data (DI [1], DI [2]) is required, so that the area overhead of the track 13 for passing the data lines is large. not.

However, when such a structure is applied to an LDI memory that requires a scan operation, the scan data output unit 15 of FIG. 1 receives the first scan output data sdout1, the third scan output data sdout3, and the second scan output from the left side. The data is output in the order of the data sdout2 and the fourth scan output data sdout4.

That is, in order to apply such an array structure to the LDI memory, there is a problem in that data must be modified and input before input to the write driver with a separate circuit.

In order to solve this problem, a conventional configuration of another example of the semiconductor memory device is adopted.

In the arrangement of the multiplexer of the semiconductor memory device of FIG. 2, a plurality of multiplexers are separately arranged in multiplexer signal units for responding to the multiplexer signal so as not to provide a separate circuit before input to the write driver. Therefore, in FIG. 2, the first multiplexer and the second multiplexer, the third multiplexer and the fourth multiplexer are arranged in order from the left side.

Accordingly, the arrangement of the plurality of memory cells includes first memory cells mc1-1 to mc1-n, second memory cells mc2-1 to mc2-n, and third memory cells mc3-1 to mc3-n. In order of the fourth memory cells mc4-1 to mc4-n. The scan data is also output in the order of the first scan data sdout1, the second scan data sdout2, the third scan data sdout3, and the fourth scan data sdout4. In other words, the plurality of scan data may be output in a sequential order and may be suitably applied to an LDI memory requiring a scan operation.

Therefore, in the case of the LDI memory requiring a scan operation, an arrangement structure according to the configuration of another conventional semiconductor memory device has been applied.

However, in this arrangement structure, the multiplexers are arranged in units of a plurality of multiplexers for responding to each multiplexer signal, so that a plurality of data (data1, data2) and a plurality of inverted data (ndata1, A plurality of data lines dl1, dl2, dl3 and dl4 for ndata2 and a plurality of inverted data lines ndl1, ndl2, ndl3 and ndl4 are horizontally increased in length to reach the multiplexer 24.

Therefore, the data lines are densely arranged in the data lines on the tracks 23 for passing, so that the area of the tracks 23 must be widened by the width of the data lines vertically in order for the data lines to pass. That is, the track 23 through which the data line passes in the circuit of FIG. 2 requires twice as much track area as the track 13 through which the data line passes through the circuit of FIG.

The case described above with reference to FIG. 2 is a case of a structure having bpw (bit per word) = 2, and when bpw = 62 with a lot of input data, an area equal to the vertical width of the track for passing 128 data lines is required. As a result, the area overhead of another conventional semiconductor memory device cannot be ignored.

That is, the semiconductor memory device of FIG. 2 does not need an additional circuit for transforming data before inputting input data to the write driver, but the layout of the semiconductor memory device is increased due to an area overhead of a track through which data passes. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a conventional problem, and to provide a semiconductor memory device which reduces the layout area by reducing the track area occupied by data lines.

The semiconductor memory device of the present invention for achieving the above object is a data driver for driving the input data to generate data and to transmit the data to a plurality of data lines of a plurality of data line group, and a plurality of data of the plurality of data line group An inverted data driver for inverting data transmitted by connecting to the lines, respectively, and transmitting inverted data to each of the inverted data lines of the plurality of data line groups, and a plurality of data line groups each having a plurality of data line pairs And a plurality of bit line pairs of each of the plurality of bit line groups, a plurality of word lines, a plurality of memory cells connected to the plurality of scan word lines and the scan lines, and the plurality of data line groups. Select a plurality of data and the inversion data A multiplexer for transmitting to a plurality of bit line pairs of each of the plurality of bit line groups in response to calls, a plurality of bit line groups each having a plurality of bit line pairs, and data transmitted through a scan line It characterized in that it comprises a scan data output unit for outputting the scan data.

1 illustrates a configuration of a conventional semiconductor memory device.

Fig. 2 shows the structure of another conventional semiconductor memory device.

3 shows the configuration of a semiconductor memory device of a preferred embodiment of the present invention.

<Description of main parts of drawing>

11, 12, 21, 22: light driver

13, 23, 33: Tracks through which data lines pass

14, 24, 34: multiplexer

15, 25, 35: scan data output unit

30: Invert data write driver

31, 32: data write driver

Hereinafter, a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

The semiconductor memory device of FIG. 3 includes data drivers 31 and 32, inverted data drivers 31a, 31b, 32a, and 32b, a data line group, a multiplexer 34, a bit line group, memory cells, The scan data output section 35 is configured.

In FIG. 3, in order to reduce an area overhead of a track through which a data line passes, an inversion data driver is added to the front of the multiplexer to invert each data transmitted through a plurality of data lines of a plurality of data line groups, thereby inverting a plurality of inversion data. A plurality of inverted data lines of the data line group are transmitted.

The function of the circuit shown in Fig. 3 is as follows.

The data drivers 31 and 32 are composed of two inverters I1 and I2 and I3 and I4, respectively, to buffer the input data DI [1] and DI [2], respectively. Is generated and transmitted to two data lines dl1, dl2, dl3, and dl4 of two data line groups.

Inverting data driver 30 is composed of two inverters (I7, I8, I9, I10) is connected to the data lines (dl1, dl2, dl3, dl4) of each of the two data line groups data (data1) , data2 generates inverted data ndata1 and ndata2 through two inverters I7, I8, I9 and I10. The inverted data ndata1 and ndata2 thus generated are transmitted to two inverted data lines ndl1, ndl2, ndl3 and ndl4 of two data line groups.

One data line group includes two data lines dl1 and dl2 for transmitting data data1 generated through one data write driver 31 to two multiplexers mux1 and mux3, and two data lines. Two inverted data lines ndl1 and ndl2 for transmitting inverted data ndata1 generated through the inverters I7 and I8 of the inverted driver connected to the signals dl1 and dl2 to the multiplexers mux1 and mux3, respectively. It is composed of

In this manner, another data line group of the data write driver 32 is also generated.

The multiplexer 34 is composed of one inverter I5, I6 and two CMOS (C1, C2) (C3, C4). The first multiplexer mux1 and the second multiplexer mux2 respond to the first multiplexer signal mux signal1, and the third multiplexer mux1 and the fourth multiplexer mux2 respond to the second multiplexer signal mux signal1. do.

When the 'high' level signal is input to the first multiplexer signal mux signal1, the signal is inverted to a 'low' signal through the inverter I5 of the first multiplexer mux1 and the second multiplexer mux2, and the signal is inputted. The two CMOSs C1 and C2 are turned 'on' and the data (data1 and data2) transmitted through the data lines dl1 and dl3 and the inverted data lines ndl1 and ndl3 of the two data line groups. The inversion data ndata1 and ndata2 are transferred to the bit line pairs bl1, nbl1, bl2 and nbl2 of the data bit line group.

In this manner, the third multiplexer mux3 and the fourth multiplexer mux4 that respond to the second multiplex signal mux signal2 operate in the same manner.

One bit line group includes bit line pairs bl1, nbl1, bl2, and nbl2 of two multiplexers mux1 and mux2 that respond to one multiplexer signal mux signal1. In this manner, a data line group is also generated in response to the second multiplexer signal mux signal2.

The memory cells mc1-1 to mc4-n are composed of three NMOSs N1, N2, and N3 and a latch L1, and are connected to a bit line pair, a word line WL, and a scan word line SWL. .

In operation, a high level signal is input to a word line during the write operation, and two NMOSs N1 and N2 are 'on' so that data (data1, data2) and inverted data (ndata1) transmitted from pairs of bit lines are transmitted. , ndata2) is written to the latch L1.

In the scan operation, a high level signal is input to the scan word line SWL, and the NMOS N3 is 'on' according to the selection signal of the data, and the data stored in the memory cell is stored in the scan lines sl1, sl2, sl3, sl4. It is transmitted to the scan data output unit 35 through. All memory cells operate in this manner.

The scan data output unit 35 outputs scan data sdout1, sdout2, sdout3, and sdout4 transmitted through two scan lines sl1, sl2, sl3, and sl4.

The operation of the semiconductor memory device shown in FIG. 3 will now be described.

If the input data DI [1] and DI [2] are input as' 01 ', the word line selection signals WL1, WL2 ..., WLn are '10 ..0', and the multiplex signal mux Assuming that signal1 and mux signal2) occur as '10', the operation will be described as follows.

The first input data is buffered '0' through the first data write driver and transmitted to the data lines dl1 and dl2 of the first data line group, and the second input data is '1' through the second data write driver. Is buffered and transmitted to the data lines dl3 and dl4 of the second data line group.

The inversion driver inverts the data of the data lines dl1 and dl2 of the first data line group to generate the inversion data '1' and transmits the inverted data lines ndl1 and ndl2 of the first data line group. The data of the data lines dl3 and dl4 of the second data line group is inverted to generate inverted data '0' and transmitted to the respective inverted data lines ndl3 and ndl4 of the second data line group.

The first multiplexer mux1 and the second multiplexer responding to the first multiplexer selection signal by the multiplexer selection signal '10' are 'enabled' so that two data lines dl1 and dl3 and two of the two data line groups are enabled. The data (data1, data2) and inverted data (ndata1, ndata2) transmitted through the inverted data lines (ndl1, ndl3) of the two bit line pairs (bl1, nbl1, bl2, nbl2) of one bit line group, respectively. The data is stored in the latch L1 of the memory cells mc1-1 and mc2-1.

In this state, when the multiplexer selection signal '01' is input, the third multiplexer mux3 and the fourth multiplexer mux4 responding to the second multiplexer selection signal are 'enabled', thereby providing two data of two data line groups. Two bit line pairs of data (data1, data2) and inverted data (ndata1, ndata2) transmitted through lines (dl2, dl4) and two inverted data lines (ndl2, ndl4), respectively, in one bit line group. The data is transferred to (bl3, nbl3, bl4, nbl4) to store data in the latch L1 of the memory cells mc3-1 and mc4-1.

As described above, the scan word line selection signals SWL1, SWL2 ..., and SWLn are set to '10 ... 'while data is stored in the two memory cells mc1-1, mc2-1, mc3-1, and mc4-1. Assuming that 0 'is generated, the following operation is described.

During the scan operation, the scan word lines of the two memory cells mc1-1, mc2-1, mc3-1, and mc4-1 are 'enabled' by the scan word line selection signal '10 ... 0 '. Data stored in the latches L1 of the memory cells mc1-1, mc2-1, mc3-1, and mc4-1 are transferred to the scan data output unit 35 through the scan lines sl1, sl2, sl3, and sl4. Is sent.

The semiconductor memory device of FIG. 3, which operates as described above, generates inverted data through an inverted data driver connected to data lines of a plurality of data line groups, unlike a circuit of another conventional semiconductor memory device of FIG. 2. The over and inverted data lines are prevented from being densely arranged in the tracks through which the data lines pass.

That is, the area of the track 33 through which the data line of FIG. 3 passes is reduced by 50% compared to the area of the track 23 through which the data line of FIG. 2 passes.

This is an effect that the layout of the semiconductor memory device can be sufficiently reduced even in consideration of the area overhead caused by arranging a plurality of inverters of the inverted data write driver in front of the multiplexer.

Table 1 is a table showing the effect of applying the semiconductor memory device proposed in the present invention to the 0.25㎛ process previously developed.

bpw (bit / word) bpw 12 bpw 16 bpw 18 bpw 64 bpw 74 Conventional PERI Height 320 (100%) 329 (100%) 333 (100%) 405 (100%) 421 (100%) Reduced height 20 (6%) 25 (7%) 28 (8%) 80 (20%) 90 (21%) PERI height according to the invention 300 (94%) 304 (93%) 305 (92%) 325 (80%) 331 (79%)

Here, PERI means the remaining blocks excluding a plurality of memory cells among the blocks of the semiconductor memory device.

Referring to Table 1, in the case of a semiconductor memory device having a small bpw, the area of the PERI block of about 6 to 8% can be reduced, and in the case of a large bpw, the area of the PERI block of about 20% can be reduced. This can reduce the size of the semiconductor memory device from 1.44 μm 2 to 1.22 μm 2 when the LDI memory is applied, thereby reducing the average layout of the semiconductor memory device by about 10%.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Therefore, the semiconductor memory device of the present invention reduces the area of the track through which the data line passes by 50%, thereby reducing the average layout of the semiconductor memory device by about 10%.

Claims (2)

A plurality of bit line groups each having a plurality of bit line pairs; A plurality of data line groups each having a plurality of data line pairs; A plurality of memory cells connected to a plurality of bit line pairs and a plurality of word lines and a plurality of scan word lines and scan lines, respectively, of the plurality of bit line groups; Data driving means for driving input data to generate data and to transmit the data to a plurality of data lines of a plurality of data line groups; Inversion data driving means for inverting data transmitted by connecting to each of the plurality of data lines of the plurality of data line groups and transmitting inverted data to each of the plurality of inverted data lines of the plurality of data line groups; A multiplexer for transmitting the data and the inverted data transmitted from the plurality of data line groups to a plurality of bit line pairs of each of the plurality of bit line groups in response to a plurality of selection signals, respectively; And And a scan data output unit configured to output data transmitted through the scan line as scan data. The inverting data drive means according to claim 1, A plurality of inverters, the plurality of inverters are arranged in a line, inverted the data transmitted by being connected to the plurality of data lines of the plurality of data line groups, and each of the plurality of inverted data lines of the plurality of data line groups And transmitting the inverted data to the semiconductor memory device.