KR20040031397A - Liquid crystal display panel and fabricating method thereof - Google Patents

Abstract

PURPOSE: An LC panel and a method for fabricating the same are provided to reduce the masking steps by forming contact holes simultaneously with data patterns, thereby reducing the fabricating cost and improving the fabricating yield. CONSTITUTION: An LC panel includes an active layer formed on a substrate(31) via a buffer film(32), a gate insulating film covering the active layer, and gate electrodes(36) formed on the gate insulating film. A plurality of insulating films cover the gate electrodes. Source and drain electrodes(38,40) contact source and drain areas(44S,44D) of the active layer via through holes(34S,34D). The through holes have a first width penetrating a first insulating film(46) and a nitride layer(58) among the plurality of insulating films and a second width penetrating the other films-a second insulating film(48) and the gate insulating film, wherein the first width is larger than the second one. A protecting film covers the source and drain electrodes. Pixel electrodes are formed on the protecting film.

Description

Liquid crystal display panel and manufacturing method therefor {LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel using polysilicon, and more particularly, to a liquid crystal display panel and a method of manufacturing the same, which can improve yield by reducing the number of masks.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal display panel. In the liquid crystal display panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area allocated by the intersection of the gate lines and the data lines. The liquid crystal display panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line. The driving circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially supplies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel by one line. The data driver supplies a video signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

The thin film transistor used in the liquid crystal display device uses amorphous silicon or poly silicon as the semiconductor layer. Amorphous-type liquid crystal display device has an advantage that the amorphous silicon layer has a relatively uniform and stable characteristics, but has a disadvantage that it is difficult to improve the pixel density due to the small charge mobility. On the contrary, the polysilicon liquid crystal display has an advantage of increasing pixel density as the polysilicon layer has a high charge mobility. In addition, it is possible to reduce the manufacturing cost by mounting the driving circuits that require a relatively fast response speed on the liquid crystal display panel.

1 is a cross-sectional view illustrating a lower substrate of a conventional polysilicon liquid crystal display device.

Referring to FIG. 1, a lower substrate 1 of a conventional polysilicon liquid crystal display device includes a thin film transistor formed at an intersection of a gate line (not shown) and a data line 26, and a drain electrode 10 of the thin film transistor. ) And a pixel electrode 22 in contact with it.

The thin film transistor includes a source formed on both sides of the active layer 14 formed on the buffer film 2, the gate electrode 6 formed on the gate insulating film 12, the gate electrode 6 interposed therebetween, Drain electrodes 8 and 10 are provided.

The active layer 14 is formed of polysilicon on the lower substrate 1 with the buffer film 2 interposed therebetween. The gate electrode 6 is formed to overlap the active layer 14 with the gate insulating film 12 therebetween. The source electrode 8 and the drain electrode 10 are formed to be insulated from the gate electrode 6 with the interlayer insulating layer 16 interposed therebetween, and penetrate the first and second interlayer insulating layers 16 and the gate insulating layer 12. The source contact hole 4S and the drain contact hole 4D are formed to contact the source region 14S and the drain region 14D of the active layer 14, respectively.

The pixel electrode 22 is formed of a transparent conductive material on the passivation layer 20 formed to cover the source and drain electrodes 8 and 10.

2A to 2F are cross-sectional views illustrating a method of manufacturing a lower substrate of the polysilicon liquid crystal display panel illustrated in FIG. 1.

First, a buffer film 2 made of an insulating material such as SiO ₂ is deposited on the lower substrate 1, and then an amorphous silicon film is deposited thereon. Subsequently, the amorphous silicon film is crystallized by a laser to form a polysilicon film, and the polysilicon film is patterned to form the active layer 14 as shown in Fig. 2A.

The gate insulating film 12 is entirely deposited on the buffer film 2 on which the active layer 14 is formed, and a gate metal layer is deposited thereon. As the gate metal layer is patterned, the gate electrode 6 is formed as shown in Fig. 2B.

Thereafter, the source region 14S, the drain region 14D, and the channel region 14C are formed by implanting impurities and activating the implanted impurities by a self-aligning method using the gate electrode 6. The source and drain regions 14S and 14D are formed by implanting n + or p + ions into both exposed active layers and irradiating a laser beam to activate impurities.

As shown in FIG. 2C, the first and second interlayer insulating layers 16 and 18 are entirely deposited and patterned on the gate insulating layer 12 having the gate electrode 6 formed thereon, so as to form the first and second interlayer insulating layers 16 and 18. ) And a source contact hole 4S and a drain contact hole 4D penetrating through the gate insulating film 12 are formed.

A source / drain metal layer is then deposited and patterned to form data line 26 and source electrode 8 and drain electrode 10 as shown in FIG. 2D. Here, each of the source electrode 8 and the drain electrode 10 is in contact with the source region 14S and the drain region 14D of the active layer 14 through the source contact hole 4S and the drain contact hole 4D. do.

As shown in FIG. 2E, the passivation layer 20 is entirely deposited and patterned on the first and second interlayer insulating layers 16 and 18 having the data line 26 and the source and drain electrodes 8 and 10 formed therein. Pixel contact holes 24 exposing 10 are formed.

A transparent conductive material is deposited and patterned on the passivation layer 38 to form a pixel electrode 22 connected to the drain electrode 10 as shown in FIG. 2F.

As described above, a conventional polysilicon liquid crystal display panel and a method of manufacturing the same include a semiconductor process and require at least six mask processes, resulting in a complicated manufacturing process and causing a rise in manufacturing cost of the liquid crystal display panel. In particular, one mask process includes many processes such as a deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process. In order to solve this problem, the liquid crystal display panel is developing in a direction of reducing the number of mask processes.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the same, which can improve the yield by reducing the number of masks.

1 is a cross-sectional view schematically showing the configuration of a lower substrate of a conventional poly liquid crystal display panel.

2A through 2F are cross-sectional views illustrating a method of manufacturing a lower substrate of the polyliquid crystal panel shown in FIG. 1.

3 is a cross-sectional view schematically showing a configuration of a lower substrate of a poly liquid crystal display panel according to the present invention.

4A to 4E are cross-sectional views illustrating a method of manufacturing a lower substrate of the polyliquid crystal panel shown in FIG. 3.

5A to 5F are cross-sectional views illustrating in detail a third mask process and a CMP process in the liquid crystal display panel shown in FIG. 4C.

<Description of Main Parts of Drawing>

1,31: lower substrate 2,32: buffer film

6,36 gate electrode 8,38 source electrode

10,40 drain electrode 12,42 gate insulating film

14,44 active layer 16,18,46,48 interlayer insulating film

20,50: protective film 22,52: pixel electrode

24,54: Pixel contact hole 26,56: Data line

58: nitride layer

In order to achieve the above object, the liquid crystal display panel according to the present invention is an active layer formed on a substrate with a buffer film interposed therebetween, a gate insulating film formed to cover the active layer, a gate electrode formed on the gate insulating film; A plurality of insulating films formed to cover the gate electrodes, a through hole having a first width penetrating the uppermost layers of the plurality of insulating films larger than a second width penetrating the plurality of insulating films except the uppermost layer and the gate insulating film, and a through hole Source and drain electrodes in contact with the active layer, a protective film formed to cover the source and drain electrodes, and a pixel electrode formed on the protective film.

The first and second widths are formed to overlap.

The active layer is characterized in that made of polysilicon.

The plurality of insulating films may include a first interlayer insulating film formed to cover the gate electrode, a nitride layer formed on the first interlayer insulating film, and a second interlayer insulating film formed on the nitride layer.

And a data line formed on the nitride layer and connected to the source electrode.

In order to achieve the above object, a liquid crystal display panel according to the present invention comprises the steps of forming an active layer on the substrate using a first mask with a buffer layer therebetween, and using a second mask on the substrate on which the active layer is formed. Forming a gate electrode with a gate insulating film interposed therebetween; and implanting impurities by a self-aligning method using the gate electrode to activate the implanted impurities to form a p + or n + layer or an n + or p + layer; After depositing a plurality of insulating films on a substrate on which a gate electrode is formed, a first width penetrating the top layers of the plurality of insulating films using a third mask is greater than a second width penetrating the plurality of insulating films and the gate insulating film except for the top layer. Forming a wide through hole, depositing a data metal layer on the top layer of the plurality of insulating films, and then forming an intermediate layer of the plurality of insulating films. Performing a chemical vapor polishing process to form a source electrode, a drain electrode, and a data line until a pixel is formed, and forming a protective film on the lower substrate on which the source electrode, the drain electrode, and the data line are formed, and then using a fourth mask. Forming a contact hole, and forming a pixel electrode on the passivation layer using a fifth mask.

The first and second widths are formed to overlap.

The active layer is characterized in that made of polysilicon.

The plurality of insulating films may include a first interlayer insulating film formed to cover the gate electrode, a nitride layer formed on the first interlayer insulating film, and a second interlayer insulating film formed on the nitride layer.

The nitride layer is formed of SiNx or the like.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 5F.

3 is a cross-sectional view illustrating a lower substrate of a polysilicon liquid crystal display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a thin film transistor formed on the lower substrate 31 of the polysilicon liquid crystal display panel according to the present invention, a pixel electrode 52 connected to the drain electrode 40 of the thin film transistor, and a thin film transistor And a data line 56 connected to the source electrode 38 of the electrode.

The thin film transistor includes an active layer 44 formed on the buffer layer 32, a gate electrode 36 formed to overlap the active layer 44, a source contact hole 34S and a drain contact hole 34D. Source and drain electrodes 38 and 40 respectively contact the source region 44S and the drain region 44D of the active layer.

The source electrode 38 is in contact with the source region 44S of the active layer through the source contact hole 34S through the first interlayer insulating film 46, the nitride layer 58, and the second interlayer insulating film 48. The drain electrode 40 is in contact with the drain region 44D of the active layer through the drain contact hole 34D penetrating through the first interlayer insulating film 46, the nitride layer 58, and the second interlayer insulating film 48.

The source contact hole 44S and the drain contact hole 44D penetrate the first interlayer insulating film 46 and the nitride layer 58 with the first width, and the second interlayer insulating film 48 is wider than the first width. It will penetrate through the width.

The data line 56 is in contact with the nitride layer 58 through the data contact hole 34L passing through the second interlayer insulating layer 48.

The lower substrate of the liquid crystal display panel having such a configuration is formed by a five mask process. A method of manufacturing a lower substrate of a liquid crystal display panel according to the present invention using a five mask process includes a first mask process for forming the active layer 44, a second mask process for forming the gate electrode 36, and a source. A third mask process for forming the contact hole 34S, the drain contact hole 34D, the data contact hole 34L, the data line 56, the source electrode 38 and the drain electrode 40, and the pixel contact hole. A fourth mask process for forming the protective film 50 having a 54 and a fifth mask process for forming the pixel electrode 52 are included.

4A through 4E are cross-sectional views illustrating a method of manufacturing a lower substrate of a liquid crystal display panel according to the present invention.

Referring to FIG. 4A, the active layer 44 is formed on the lower substrate 31 with the buffer layer 32 interposed therebetween.

To this end, a buffer film 32 made of an insulating material such as SiO ₂ is deposited on the lower substrate 31, and then an amorphous silicon film is deposited thereon. Subsequently, the amorphous silicon film is crystallized by a laser to form a polysilicon film. Thereafter, the polysilicon film is patterned by a photolithography process and an etching process using a first mask to form an active layer 44 on the lower substrate 31.

Referring to FIG. 4B, the gate electrode 36 is formed on the lower substrate on which the active layer 44 is formed with the gate insulating layer 42 interposed therebetween.

To this end, the gate insulating layer 42 and the gate metal layer are formed on the buffer layer 32 on which the active layer 44 is formed through a deposition method such as PECVD or sputtering. As the gate insulating film 42, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. Aluminum (Al), an aluminum alloy, or the like is used as the gate metal. Subsequently, the gate metal layer is patterned by the photolithography process and the etching process using the second mask to form the gate electrode 36 on the lower substrate 31.

Thereafter, the source region 44S, the drain region 44D, and the channel region 44C are formed by implanting impurities and activating the implanted impurities by a self-aligning method using the gate electrode 36. The source and drain regions 44S and 44D are formed by implanting n + or p + ions into both exposed active layers and irradiating a laser beam to activate impurities.

Referring to FIG. 4C, the first and second interlayer insulating films 46 and 48, the nitride layer 58, the data line 56, the source and drain electrodes are formed on the lower substrate 31 on which the gate electrode 36 is formed. 38,40 are formed.

To this end, the first interlayer insulating film 46, the nitride layer 58, and the second interlayer insulating film 48 are sequentially formed on the lower substrate 31 on which the gate electrode 36 is formed. As the nitride layer 58, SiNx or the like is used.

Subsequently, the first interlayer insulating film 46, the nitride layer 58, and the second interlayer insulating film 48 are patterned by a photolithography process using a third mask, which is a diffraction mask or a semi-transmissive mask, and a wet etching process and a dry etching process. Thus, the source contact hole 34S, the drain contact hole 34D, and the data contact hole 34L are formed.

The source contact hole 34S and the drain contact hole 34D pass through the first interlayer insulating film 46 and the nitride layer 58 to have a first width, and the second interlayer insulating film 48 is wider than the first width. Penetrate to have 2 widths. The source contact hole 34S and the drain contact hole 34D expose the active layer. The nitride contact layer 58 is exposed by the data contact hole 34L passing through the second interlayer insulating film 48 to have a predetermined width.

Thereafter, after depositing a data metal layer on the second interlayer insulating film 48, the surface of the lower substrate 31 is planarized by using a CMP process, thereby making the source electrode 38, the drain electrode 40, and the data line ( 56) is formed.

Each of the source electrode 34 and the drain electrode 38 comes into contact with the active layer 44 through the source contact hole 34S and the drain contact hole 34D. The data line 34 is in contact with the nitride layer 58 through the data contact hole 34L.

The third mask process and the CMP process will be described later in detail.

Referring to FIG. 4D, a passivation layer 48 is formed on the lower substrate 31 on which the data line 56, the source electrode 38, and the drain electrode 40 are formed.

To this end, the protective film 50 is formed by depositing an insulating material on the lower substrate 31 on which the data line 56, the source electrode 38, and the drain electrode 40 are formed. Thereafter, the passivation layer 50 is patterned through a photolithography process and an etching process using a fourth mask to form the pixel contact hole 54. The pixel contact hole 54 penetrates the passivation layer 50 to expose the drain electrode 40.

Referring to FIG. 4E, the pixel electrode 52 is formed on the lower substrate 31 on which the passivation layer 50 is formed.

To this end, a transparent conductive material is deposited on the lower substrate 31 on which the passivation layer 50 is formed. Subsequently, the pixel electrode 52 is formed by patterning the transparent conductive material through a photolithography process and an etching process using a fifth mask. The pixel electrode 52 is electrically connected to the drain electrode 40 through the pixel contact hole 54.

5A through 5F are cross-sectional views illustrating in detail the third mask process and the CMP process in the liquid crystal display panel shown in FIG. 4C.

Referring to FIG. 5A, a first interlayer insulating layer 46, a nitride layer 58, and a second interlayer insulating layer 48 are sequentially formed on the lower substrate 31 on which the gate electrode 36 is formed. After the photoresist 72 is completely coated, the third mask MS, which is a partial exposure mask, is aligned on the lower substrate 31.

The third mask MS may include a blocking layer 62 formed in the blocking region S1 of the transparent mask substrate 60, a partial transmissive layer 64 formed in the partial exposure region S2, and a front exposure region ( And a transmission layer formed in S3). The third mask MS is formed such that the transparent mask substrate 60 is exposed as it is in the front exposure area S3.

Referring to FIG. 5B, a photoresist pattern 70 is formed on the second interlayer insulating layer 48 by a photolithography process using a third mask MS, which is a partial exposure mask.

That is, all of the photoresist exposed through the front exposure area S3 of the third mask MS is removed by the photolithography process using the third mask MS, and the blocking area S1 and the partial exposure area are removed. An unexposed or partially exposed photoresist pattern 70 is formed through S2.

The second photoresist pattern 70B partially exposed by the partially transmissive layer 64 of the third mask MS is formed at a first height and is not exposed by the blocking layer 62 of the third mask MS. The first photoresist pattern 70A has a second height higher than the first height.

Referring to FIG. 5C, in the partially exposed second photoresist pattern 70B, a part of the second interlayer insulating film 48 is patterned by a dry etching process to expose a part of the second interlayer insulating film 48, and the entire exposure area is exposed. (S3) The entirety of the second interlayer insulating film 48 and the nitride layer 58 and the part of the first interlayer insulating film 46 are patterned by a dry etching process to expose a part of the first interlayer insulating film 46.

Referring to FIG. 5D, a portion of the partially exposed second interlayer insulating film 48 is exposed, and the second interlayer insulating film 48 is patterned by a wet etching process to expose the nitride layer 58, and the front exposed material. A portion of the first interlayer insulating film 46 is exposed in the first interlayer insulating film 46 and the gate insulating film 42 are patterned by a wet etching process so that the active layer is exposed to expose the source contact hole 34S and the drain contact hole 34D. ) And a data contact hole 34L are formed. At this time, the nitride layer 58 is an etch-stopper. The active layer 44 is formed in the region where the active layer 44 is formed, and the nitride layer 58 is formed in the region where the active layer 44 is not formed. ) Is patterned to be exposed.

5E and 5F, the data metal layer 39 is entirely deposited on the lower substrate 31 on which the second interlayer insulating layer 48 is formed by a deposition method such as sputtering. As the data metal layer 39, molybdenum (Mo) / aluminum neodium (AlNd) or the like is used.

This data metal layer 39 is planarized by a chemical mechanical polishing process. In the chemical mechanical polishing process, the lower substrate 31 on which the data metal layer 39 is deposited is placed on the rotating plate, the surface of the data metal layer 39 is brought into contact with the pad of the polishing machine, and the slurry is supplied. The pad is rotated to perform the polishing process of the data metal layer 39. That is, the slurry flows between the pad and the data metal layer 39 formed on the lower substrate 31 to polish the data metal layer 39 by mechanical friction caused by the surface projections of the pad and the abrasive particles in the slurry. Chemical removal is performed by a chemical reaction between the chemical component and the data metal layer 39. Here, the nitride layer 58 located below the data metal layer 39 is used as a stop layer of the chemical mechanical polishing process.

As such, the chemical mechanical polishing process is performed until the nitride layer 58 is exposed to form the source electrode 38, the drain electrode 40, and the data line 56 on the lower substrate.

As described above, the liquid crystal display panel according to the present invention and a manufacturing method thereof include a data pattern including a source electrode, a drain electrode and a data line, a source contact hole, a drain contact hole, and a data by a partial exposure mask and a chemical mechanical polishing process. Contact holes including contact holes are formed at the same time. Accordingly, one mask process can be reduced from the conventional six mask processes to five mask processes, thereby reducing manufacturing cost and improving manufacturing yield.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

An active layer formed on the substrate with the buffer film interposed therebetween, A gate insulating film formed to cover the active layer; A gate electrode formed on the gate insulating film; A plurality of insulating films formed to cover the gate electrode; A through hole having a first width penetrating through the uppermost layers of the plurality of insulating films greater than a second width penetrating through the plurality of insulating films except the uppermost layer and the gate insulating film; Source and drain electrodes in contact with the active layer through the through holes; A protective film formed to cover the source and drain electrodes; And a pixel electrode formed on the passivation layer. The method of claim 1, And the first width and the second width overlap each other. The method of claim 1, And the active layer is made of polysilicon. The method of claim 1, The plurality of insulating films A first interlayer insulating film formed to cover the gate electrode; A nitride layer formed on the first interlayer insulating film; And a second interlayer insulating film formed on the nitride layer. The method of claim 4, wherein And a data line formed on the nitride layer and connected to the source electrode. Forming an active layer on the substrate using a first mask therebetween with a buffer film therebetween; Forming a gate electrode on the substrate on which the active layer is formed with a gate insulating film interposed therebetween by using a second mask; Implanting impurities using the gate electrode to activate the implanted impurities to form a channel; After depositing a plurality of insulating films on the substrate on which the gate electrode is formed, a first width penetrating the uppermost layers of the plurality of insulating films using a third mask is a second width penetrating the plurality of insulating films and the gate insulating film except for the uppermost layer. Forming a wider through hole, Forming a source electrode, a drain electrode, and a data line by depositing a data metal layer on an uppermost layer of the plurality of insulating films and then performing a chemical vapor polishing process until the intermediate layers of the plurality of insulating films are exposed; Forming a protective layer on the lower substrate on which the source electrode, the drain electrode, and the data line are formed, and then forming a pixel contact hole using a fourth mask; And forming a pixel electrode on the passivation layer by using a fifth mask. The method of claim 6, And the first width and the second width overlap each other. The method of claim 6, The active layer is a method of manufacturing a liquid crystal display panel, characterized in that made of polysilicon. The method of claim 6, The plurality of insulating films A first interlayer insulating film formed to cover the gate electrode; A nitride layer formed on the first interlayer insulating film; And a second interlayer insulating film formed on the nitride layer. The method of claim 9, And the nitride layer is formed of SiNx or the like.