KR20040029526A - Heterojunction bipolar transistor and method for manufacturing the same - Google Patents
Heterojunction bipolar transistor and method for manufacturing the same Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 68
- 229920005591 polysilicon Polymers 0.000 claims abstract description 68
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 43
- 239000012535 impurity Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 claims description 69
- 239000010409 thin film Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 description 7
- 238000011065 in-situ storage Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
- H01L29/1008—Base region of bipolar transistors of lateral transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
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Abstract
Description
본 발명은 이종 접합 바이폴라 트랜지스터(Heterojunction bipolar transistor : 이하 HBT) 및 그 제조방법에 관한 것으로, 보다 구체적으로는 이종 접합 바이폴라 트랜지스터의 에미터 구조 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to heterojunction bipolar transistors (hereinafter referred to as HBTs) and a method of manufacturing the same. More particularly, the present invention relates to an emitter structure of a heterojunction bipolar transistor and a method of manufacturing the same.
Si-Ge 반도체는 실리콘(Si)과 게르마늄(Ge)으로 구성된 재료로서, 에너지 밴드(energy band)와 캐리어(carrier)의 이동도 등의 물리적 특성을 원하는 대로 조절할 수 있다는 장점을 갖는다. SiGe 헤테로 소자 관련 기술은 최근에 들어 급속히 발전하였으며, 그중에서도 HBT는 무선 통신 및 광통신에 요구되는 RF 회로 등 광범위한 용도 및 주파수 영역에서 상용화하는 단계에 이르고 있다. 이러한 SiGe HBT와 일반적인 BJT의 차이점으로는 베이스층을 SiGe 에피층으로 형성하는 점에서 차이가 있다.Si-Ge semiconductor is a material composed of silicon (Si) and germanium (Ge), and has the advantage that physical properties such as energy band and carrier mobility can be adjusted as desired. The technology related to SiGe hetero devices has been rapidly developed in recent years, and among them, HBT has reached a commercial stage in a wide range of applications and frequency domains such as RF circuits required for wireless communication and optical communication. The difference between the SiGe HBT and the general BJT is that the base layer is formed of a SiGe epi layer.
도 1은 일반적인 SiGe HBT를 나타낸 단면도이다.1 is a cross-sectional view showing a general SiGe HBT.
도 1을 참조하여 SiGe HBT를 설명하면, 반도체 기판(10), 예를들어 n형의 실리콘 기판상에 n형의 에피택셜층(12, 콜렉터 에피택셜층)을 성장한다. 그후, n형의 에피택셜층(12)의 소정 부분에 공지의 방식으로 소자 분리막(14)을 형성한다. 소자 분리막(14)에 의하여 한정된 액티브 영역에 SiGe 베이스층(16)을 성장한다음, SiGe 베이스층(16) 상부에 n형의 불순물이 도핑된 폴리실리콘막을 증착한다. 이때, 도핑된 폴리실리콘막은, 불순물이 도핑되지 않은채로 폴리실리콘막을 증착하고 불순물을 이온 주입후 활성화시키는 이온 주입 방식으로 형성하거나, 증착과 불순물 도핑이 동시에 진행되는 인 시튜(in situ) 방식으로 증착할 수 있다.Referring to Fig. 1, SiGe HBT is described. An n-type epitaxial layer 12 (collector epitaxial layer) is grown on a semiconductor substrate 10, for example, an n-type silicon substrate. Thereafter, the device isolation film 14 is formed on a predetermined portion of the n-type epitaxial layer 12 in a known manner. After growing the SiGe base layer 16 in the active region defined by the device isolation film 14, a polysilicon film doped with n-type impurities is deposited on the SiGe base layer 16. In this case, the doped polysilicon film is formed by an ion implantation method in which a polysilicon film is deposited without an impurity, and an impurity is ion implanted and activated, or an in situ method in which deposition and impurity doping proceed simultaneously. can do.
그후, 도핑된 폴리실리콘막을 소정의 패턴 형태로 식각하여 에미터층(18)을 형성한다. 에미터층(18) 및 SiGe 베이스층(16) 상부에 절연막(20)을 증착한다음, SiGe 베이스층(16) 및 에미터층(18)의 소정 부분이 노출될 수 있도록 절연막(20)을 식각한다. 노출된 에미터층(18) 및 SiGe 베이스층(16)과 각각 콘택되도록 금속 배선(22,24)을 형성하여, 에미터 전극(E) 및 베이스 전극(B)을 형성한다. 이때, 반도체 기판(10)은 콜렉터 전극(C)이 된다.Thereafter, the doped polysilicon film is etched into a predetermined pattern to form the emitter layer 18. After the insulating film 20 is deposited on the emitter layer 18 and the SiGe base layer 16, the insulating film 20 is etched to expose a predetermined portion of the SiGe base layer 16 and the emitter layer 18. . The metal wires 22 and 24 are formed to contact the exposed emitter layer 18 and the SiGe base layer 16, respectively, to form the emitter electrode E and the base electrode B. As shown in FIG. At this time, the semiconductor substrate 10 becomes the collector electrode C. FIG.
그러나, 상기한 종래의 SiGe HBT는 에미터층을 도핑된 폴리실리콘막으로 형성함에 따라, 박막화를 달성할 수 있을 뿐만 아니라, 소수 캐리어(minority carrier)에 의한 누설 전류를 제한할 수 있다는 장점이 있는 반면, 다음과 같은 문제점 또한 내재하고 있다.However, the above-described conventional SiGe HBT has the advantage that it is possible to achieve thinning as well as to limit the leakage current due to minority carriers by forming the emitter layer as a doped polysilicon film. The following problems are also inherent.
먼저, 이온 주입 방식에 의하여 도핑된 폴리실리콘막을 형성하는 방법은, 도핑되지 않은 폴리실리콘막 증착, 불순물 이온 주입 및 어닐링 공정등 다수의 공정이 요구된다. 특히, 불순물 이온 주입은 두께에 따라 균일한 농도를 가질 수 있도록 에너지 레벨을 달리하여 여러번 이온 주입 공정을 실시하여야 하므로, 공정이 번거럽고, 폴리실리콘막 자체에 부담이 가중된다.First, a method of forming a doped polysilicon film by an ion implantation method requires a number of processes such as undoped polysilicon film deposition, impurity ion implantation, and annealing processes. In particular, the impurity ion implantation has to be carried out several times by varying the energy level so as to have a uniform concentration according to the thickness, and the process is cumbersome, and the burden on the polysilicon film itself is increased.
한편, 인시튜 방식에 의한 도핑된 폴리실리콘막을 형성하는 방법은 증착과 동시에 불순물이 도입되므로 공정이 단순한 측면은 있으나, 증착 온도에 따라 폴리실리콘막의 결정립계(grain boundary) 사이즈의 변화가 커서, 도핑 레벨 조절이 어렵다. 즉, 고온에서 인시튜 도핑된 폴리실리콘막을 증착하는 경우에는, 증착률이 증대되어 두께 조절이 어렵고, 가스 플로우(gas flow)에 따른 도핑 농도 변화 역시 크다.On the other hand, the method of forming the doped polysilicon film by the in-situ method has a simple process since impurities are introduced at the same time as the deposition, but the grain boundary size of the polysilicon film is large according to the deposition temperature, and thus the doping level is increased. Difficult to adjust That is, in the case of depositing the in-situ doped polysilicon film at a high temperature, the deposition rate is increased, so that it is difficult to control the thickness, and the doping concentration change according to the gas flow is also large.
그러므로, 현재에는 인시튜 도핑된 폴리실리콘막을 저온에서 증착하고 있는다. 이때, 저온에서 도핑된 폴리실리콘막을 증착하면, 아몰포스 실리콘 상태와 가깝게 폴리실리콘 막내에 큰 사이즈의 결정립계(grain boundary)가 형성되어, 후속의 열 공정시 도핑된 폴리실리콘막의 재결정화(re-crystalize)가 발생된다. 그러나, 이러한 재결정화 공정으로 인하여, 큰 사이즈의 결정립계는 작은 사이즈의 결정립계로 변형되고, 이 과정에서 도핑된 폴리실리콘막 하부의 SiGe 베이스층(18)에 심각한 스트레스를 전달하게 되어, SiGe 베이스층(18)의 결정성이 저하되어, 베이스 누설 전류를 유발할 수 있다.Therefore, an in-situ doped polysilicon film is currently deposited at low temperature. At this time, deposition of the doped polysilicon film at low temperature forms a large grain boundary in the polysilicon film close to the amorphous silicon state, thereby re-crystallizing the doped polysilicon film during the subsequent thermal process. ) Is generated. However, due to this recrystallization process, a large grain boundary is transformed into a small grain boundary, and in this process, a significant stress is transmitted to the SiGe base layer 18 under the doped polysilicon film, thereby causing a SiGe base layer ( The crystallinity of 18) is lowered, which may cause the base leakage current.
따라서, 본 발명이 이루고자 하는 기술적 과제는 SiGe 베이스층에 스트레스 인가 없이, 작은 사이즈의 결정립계를 갖는 도핑된 폴리실리콘막을 에미터층으로 하는 HBT를 제공하는 것이다.Accordingly, a technical object of the present invention is to provide an HBT having a doped polysilicon film having a small grain size as an emitter layer without applying stress to the SiGe base layer.
또한, 본 발명이 이루고자 하는 다른 기술적 과제는 상기한 HBT의 제조방법을 제공하는 것이다.In addition, another technical problem to be achieved by the present invention is to provide a method of manufacturing the HBT.
도 1은 일반적인 HBT의 단면도이다.1 is a cross-sectional view of a general HBT.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 HBT의 제조방법을 설명하기 위한 각 공정별 단면도이다.2A to 2D are cross-sectional views of respective processes for explaining a method of manufacturing HBT according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
100 : 반도체 기판 110: 콜렉터 에피택셜층100 semiconductor substrate 110 collector epitaxial layer
130 : SiGe 베이스층 140 : 비도핑 폴리실리콘막130: SiGe base layer 140: undoped polysilicon film
150 : 에미터용 도핑된 폴리실리콘막 160 : 에미터층150 doped polysilicon film for emitter 160 emitter layer
상기한 본 발명의 기술적 과제를 달성하기 위하여, 본 발명의 HBT는, 소정의 불순물을 포함하며 콜렉터 역할을 하는 반도체 기판과, 상기 반도체 기판상에 형성되는 SiGe 베이스층, 및 상기 SiGe 베이스층 상에 형성되는 도핑된 폴리실리콘막으로 형성되는 에미터층을 포함하며, 상기 SiGe 베이스층과 에미터층 사이에 에미터층의 결정립계를 결정하는 씨드층이 개재되는 것을 특징으로 한다.In order to achieve the above technical problem of the present invention, the HBT of the present invention, including a predetermined impurity and serves as a collector, a SiGe base layer formed on the semiconductor substrate, and the SiGe base layer And an emitter layer formed of a doped polysilicon film to be formed, wherein a seed layer for determining a grain boundary of the emitter layer is interposed between the SiGe base layer and the emitter layer.
또한, 본 발명의 다른 견지에 따른 HBT 제조방법은, n형의 불순물을 포함하는 반도체 기판상에 SiGe 베이스층을 형성하고, 상기 SiGe 베이스층 상부에 씨드층을 형성한다. 그후, 상기 씨드층의 결정립계를 따라 불순물이 도핑된 폴리실리콘막을 증착하고, 상기 도핑된 폴리실리콘막을 패터닝하여 에미터층을 형성한다.In addition, the HBT manufacturing method according to another aspect of the present invention, a SiGe base layer is formed on a semiconductor substrate containing n-type impurities, and a seed layer is formed on the SiGe base layer. Thereafter, a polysilicon film doped with impurities is deposited along the grain boundary of the seed layer, and the doped polysilicon film is patterned to form an emitter layer.
상기 씨드층은 불순물이 도핑되지 않은 비도핑 폴리실리콘막일 수 있으며,상기 비도핑 폴리실리콘막은 상대적으로 작은 결정립계를 갖도록 600 내지 700℃의 온도에서 증착함이 바람직하다.The seed layer may be an undoped polysilicon film that is not doped with impurities, and the undoped polysilicon film is preferably deposited at a temperature of 600 to 700 ° C. to have a relatively small grain boundary.
아울러, 상기 비도핑 폴리실리콘막의 두께는, 에미터층내의 불순물이 확산되더라도 에미터층용 도핑된 폴리실리콘막의 불순물 농도 변화에 지장이 없을 정도의 충분한 박막, 예를들어, 10 내지 500Å으로 형성할 수 있다.In addition, the thickness of the undoped polysilicon film may be formed to a sufficient thin film, for example, 10 to 500 kPa so that the impurity concentration of the emitter layer doped polysilicon film does not interfere even when impurities in the emitter layer are diffused. .
또한, 상기 에미터층을 형성하는 도핑된 폴리실리콘막은 500 내지 600℃의 온도에서 성장하는 것이 바람직하다.In addition, the doped polysilicon film forming the emitter layer is preferably grown at a temperature of 500 to 600 ℃.
본 발명의 목적과 더불어 그의 다른 목적 및 신규한 특징은, 본 명세서의 기재 및 첨부 도면에 의하여 명료해질 것이다.Other objects and novel features as well as the objects of the present invention will become apparent from the description of the specification and the accompanying drawings.
(실시예)(Example)
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 설명하도록 한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되어지는 것이다. 따라서, 도면에서의 요소의 형상 등은 보다 명확한 설명을 강조하기 위해서 과장되어진 것이며, 도면상에서 동일한 부호로 표시된 요소는 동일한 요소를 의미한다. 또한, 어떤 층이 다른 층 또는 반도체 기판의 "상"에 있다라고 기재되는 경우에, 어떤 층은 상기 다른 층 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는, 그 사이에 제 3의 층이 개재되어질 수 있다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, a layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. Can be done.
첨부한 도면 도 2a 내지 도 2d는 본 발명의 실시예를 설명하기 위한 각 공정별 단면도이다.2A to 2D are cross-sectional views of respective processes for describing an exemplary embodiment of the present invention.
도 2a를 참조하여, n형의 불순물을 포함하는 반도체 기판(100), 예를 들어, 실리콘 기판을 준비한다. 이러한 n형의 반도체 기판(100)을 상압 화학 기상 증착(APCVD) 방식으로 에피택셜 성장시킨 후, 예를 들어 n형의 불순물을 주입하여, 콜렉터 에피택셜층(110)을 형성한다. 이때, 반도체 기판(100) 및 콜렉터 에피택셜층(110)은 HBT의 콜렉터의 역할을 한다. 이어서, 콜렉터 에피택셜층(110)이 형성된 반도체 기판상(100)에 공지의 LOCOS 방식으로 소자 분리막(120)을 형성한다.Referring to FIG. 2A, a semiconductor substrate 100 including an n-type impurity, for example, a silicon substrate is prepared. After the n-type semiconductor substrate 100 is epitaxially grown by atmospheric chemical vapor deposition (APCVD), n-type impurities are implanted, for example, to form the collector epitaxial layer 110. At this time, the semiconductor substrate 100 and the collector epitaxial layer 110 serve as a collector of the HBT. Subsequently, the device isolation layer 120 is formed on the semiconductor substrate 100 on which the collector epitaxial layer 110 is formed by a known LOCOS method.
그리고 나서, 콜렉터 에피택셜층(110) 상부에 SiGe 베이스층(130)을 성장한다. SiGe 베이스층(130)은 예를들어, Si 씨드(seed)층, SiGe 에피택셜층, 및 Si 캡층의 적층 구조를 가질 수 있으며, SiGe 에피택셜층을 성장시킬 때 인시튜로 도핑을 실시한다. 이러한 SiGe 베이스층(130)은 Ge의 조성이 5% 이상으로 균일하거나, 농도가 점차 변화될 수 있다. 또한, SiGe 베이층(130)의 계면에는 탄소(C)와 산소(O)의 양이 적어야 하며 도핑 농도를 정확히 조절하여야 한다.Then, the SiGe base layer 130 is grown on the collector epitaxial layer 110. The SiGe base layer 130 may have a stacked structure of, for example, a Si seed layer, a SiGe epitaxial layer, and a Si cap layer, and doping in situ when growing the SiGe epitaxial layer. The SiGe base layer 130 may have a uniform composition of Ge of 5% or more, or the concentration may be gradually changed. In addition, the amount of carbon (C) and oxygen (O) should be small at the interface of the SiGe bay layer 130 and the doping concentration should be accurately controlled.
다음으로, 도 2b를 참조하여, SiGe 베이스층(130) 상부에 씨드층으로서 불순물이 도핑되지 않은 폴리실리콘층(140, 이하, 비도핑 폴리실리콘막)을 소정 두께로 증착한다. 이때, 비도핑 폴리실리콘막(140)은 충분히 작은 결정립계 사이즈를 갖도록 고온, 예를들어, 600 내지 700℃의 온도 범위에서 증착한다. 이때, 비도핑 폴리실리콘막(140)에는 불순물이 포함되어 있지 않은 박막이므로, 고온에서 증착되더라도 공정 시간이 짧아 도핑 레벨이 변화되지 않는다. 아울러, 비도핑폴리실리콘막(140)의 두께는, 이후 에미터층용 도핑된 폴리실리콘막을 증착한 후, 열적 부담(thermal budget)으로 인하여 에미터용 도핑된 폴리실리콘막내의 불순물이 비도핑 폴리실리콘막(140)으로 확산되어도 에미터용 도핑된 폴리실리콘막의 불순물 농도 변화에 지장이 없을 정도의 박막임이 바람직하다. 예를 들어, 비도핑 폴리실리콘막(140)은 10Å 내지 500Å 두께로 형성될 수 있다.Next, referring to FIG. 2B, a polysilicon layer 140 (hereinafter, undoped polysilicon film) having no impurities as a seed layer is deposited on the SiGe base layer 130 to a predetermined thickness. At this time, the undoped polysilicon film 140 is deposited at a high temperature, for example, a temperature range of 600 to 700 ° C. to have a sufficiently small grain boundary size. At this time, since the undoped polysilicon film 140 is a thin film containing no impurities, even when deposited at a high temperature, the process time is short and doping level does not change. In addition, the thickness of the undoped polysilicon film 140, after depositing the doped polysilicon film for the emitter layer, the impurities in the doped polysilicon film for the emitter due to the thermal budget (thermal budget) is undoped polysilicon film Even if diffused to 140, it is preferable that the film is thin enough that the impurity concentration change of the doped polysilicon film for the emitter does not interfere. For example, the undoped polysilicon film 140 may be formed to a thickness of 10 kV to 500 kV.
그후, 비도핑 폴리실리콘막(140) 상부에 에미터층용 도핑된 폴리실리콘막(150)을 형성한다. 이때, 에미터층용 도핑된 폴리실리콘막(150)은 증착과 동시에 불순물이 주입되는 인시튜 방식으로 형성된다. 에미터층용 도핑된 폴리실리콘막(150)은 두께 제어가 용이하도록 저온, 예를들어 500 내지 600℃의 온도에서 증착한다. 본 실시예의 에미터층용 도핑된 폴리실리콘막(150)은 비록 저온에서 증착된다 하더라도, 하부의 작은 사이즈의 결정립계를 갖는 비도핑 폴리실리콘막(140)을 씨드층으로 하여 성장하게 되므로, 하부의 비도핑 폴리실리콘막(140)과 같은 작은 사이즈의 결정립계를 갖게된다. 이에따라, 에미터용 도핑된 폴리실리콘막(150)은 저온 성장에 의하여 도핑 레벨 조절이 용이할 뿐만 아니라, 하부의 비도핑 폴리실리콘막(140)에 의하여 작은 사이즈의 결정립계를 갖도록 성장된다. 따라서, 후속의 재결정화시, 에미터용 도핑된 폴리실리콘막(150)의 결정립 변형이 최소화되어, 하부의 SiGe 베이스층(130)으로 스트레스를 인가되는 것이 최소화된다.Thereafter, the doped polysilicon film 150 for the emitter layer is formed on the undoped polysilicon film 140. In this case, the doped polysilicon film 150 for the emitter layer is formed in an in-situ manner in which impurities are injected at the same time as the deposition. The doped polysilicon film 150 for the emitter layer is deposited at a low temperature, for example 500-600 ° C., to facilitate thickness control. Although the doped polysilicon film 150 for the emitter layer of the present embodiment is deposited at a low temperature, the doped polysilicon film 140 having a small grain size at the bottom is grown as a seed layer, so that the lower ratio The grain size of the same size as the doped polysilicon layer 140 is obtained. Accordingly, the doped polysilicon film 150 for the emitter is not only easy to control the doping level by low temperature growth, but also grown to have a small grain boundary by the lower undoped polysilicon film 140. Thus, upon subsequent recrystallization, grain deformation of the doped polysilicon film 150 for the emitter is minimized, thereby minimizing stress on the underlying SiGe base layer 130.
도 2c에 도시된 바와 같이, 에미터층용 도핑된 폴리실리콘막(150) 및 비도핑 폴리실리콘막(140)을 소정 부분 패터닝하여, 패턴 형상을 갖는 에미터층(160)을 형성한다. 그후에, 반도체 기판(100) 결과물 상부에 절연막(170)을 증착한다.As shown in FIG. 2C, the doped polysilicon film 150 and the undoped polysilicon film 140 for the emitter layer are partially patterned to form an emitter layer 160 having a pattern shape. Thereafter, an insulating film 170 is deposited on the semiconductor substrate 100 product.
도 2d를 참조하여, SiGe 베이스층(130) 및 에미터층(160)의 소정 부분이 노출될 수 있도록 절연막(170)을 식각한다. 다음, 노출된 에미터층(160) 및 SiGe 베이스층(130)과 각각 콘택되도록 금속 배선(180,190)을 형성하여, 에미터 전극(E) 및 베이스 전극(B)이 형성된다. 이때, 기판(100)은 콜렉터 전극(C)이 된다.Referring to FIG. 2D, the insulating layer 170 is etched to expose a predetermined portion of the SiGe base layer 130 and the emitter layer 160. Next, the metal wires 180 and 190 are formed to contact the exposed emitter layer 160 and the SiGe base layer 130, respectively, so that the emitter electrode E and the base electrode B are formed. At this time, the substrate 100 becomes the collector electrode (C).
이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, SiGe 베이스층(130)과 에미터층을 형성하기 전에 고온에서 비도핑 폴리실리콘막을 박막으로 증착한다. 고온에서 증착된 비도핑 폴리실리콘막은 상대적으로 작은 사이즈의 결정립계를 가지게 되고, 이후 형성되는 에미터층(에미터용 도핑된 폴리실리콘막)의 씨드층으로 작용하게 된다. 이에따라, 후속의 에미터용 도핑된 폴리실리콘막은 저온에서 증착되더라도 하부 비도핑 폴리실리콘막에 의하여 작은 사이즈의 결정립계를 가지게 되어, 이후 열공정에 의하여 재결정화가 발생되더라도 결정립 사이즈가 변화되지 않는다. 따라서, 하부의 SiGe 베이스층으로 스트레스가 전달이 최소화되어, 베이스 누설 전류를 방지할 수 있다.As described in detail above, according to the present invention, the undoped polysilicon film is deposited as a thin film at a high temperature before the SiGe base layer 130 and the emitter layer are formed. The undoped polysilicon film deposited at a high temperature will have a relatively small grain size and serve as a seed layer of the emitter layer (doped polysilicon film for emitter) formed thereafter. Accordingly, the subsequent doped polysilicon film for the emitter has a small grain boundary by the lower undoped polysilicon film even when deposited at a low temperature, so that the grain size does not change even if recrystallization occurs by the thermal process. Therefore, transfer of stress to the lower SiGe base layer is minimized, thereby preventing base leakage current.
이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러가지 변형이 가능하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .
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