KR20040021524A - Image forming device easy to remodeling and method for placing image forming device on PCB - Google Patents

Abstract

PURPOSE: An image forming apparatus easily redesigned and a method of arranging components of the image forming apparatus are provided to reduce manufacturing costs of the image forming apparatus. CONSTITUTION: An image forming apparatus includes an engine mechanism, a video processor(110), and an engine controller(120). The engine mechanism performs a printing operation with respect to print data. The video processor converts the print data to image data recognized by the engine mechanism. The engine controller controls the engine mechanism to carry out a printing operation with respect to the image data. The engine controller and the video processor are arranged on a single PCB(100) divided into the first and second regions(110a,120a), respectively. A circuit element shared by the engine controller and the video processor is arranged in the second region.

Description

Image forming device easy to remodeling and method for placing image forming device on PCB}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus, and more particularly, to an image forming apparatus and a method for arranging parts of an image forming apparatus, which can be easily redesigned when adding a print processing performance or a new function.

Image forming apparatuses such as laser printers, in addition to a function of reproducing printing data applied from an information processing apparatus such as a personal computer, on a printing medium such as paper, have tended to be configured as a multifunction machine in conjunction with a fax machine and a copier. As a result, upgrade cycles of molds and printed circuit boards (hereinafter referred to as "PCBs") of image forming apparatuses, such as laser printers, are accelerating, but the mold design takes more time than the design of electronic circuit boards. This requires a reliability test of the designed mold. Therefore, the image forming apparatus typically has a design cycle of three to five years after the reliability test, and redesigns the electronic circuit board mainly when adding a new function.

On the other hand, according to the above design features, the mold design and the electronic circuit board design are often made independently by different companies. In this case, the mold has various motors for driving the image forming apparatus and electronic circuit boards for controlling the motors. In general, the motor and the electronic circuit board for controlling the motor are often sold as a set, and when designing the image forming apparatus, the electronic circuit board for driving the motor is verified, so it is required for reliability testing. Can reduce the time. However, when the mold and the electronic circuit board for driving the mold is purchased separately and the image forming apparatus is to be designed, a separate processor, a random access memory, and a program for driving the processor are included in the electronic circuit board included in the mold. The flash ROM (or mask ROM, EPROM, etc.) to be stored must be mounted, and the designer cannot easily change the design of this part.

Figure 1 shows a block diagram of a conventional laser printer.

The illustrated laser printer has an image processing unit 20, a power supply unit (SMPS) 30, an engine control unit 40, a high pressure generation unit (HVPS) 50, and an engine mechanism 60.

The image processing unit 20 converts the print data applied from the host computer 10 into image data that can be processed by the engine control unit 40, for example, a bit map format. The power supply unit (SMPS) 30 generates power for driving the image processing unit 20, the engine control unit 40, the high pressure generation unit 50, and the engine mechanism 60. The engine controller 40 controls the driving of the engine mechanism 60 in accordance with the image data applied from the image processor 20. The engine mechanism 60 is driven by the engine control unit 40 to implement a predetermined image on a print medium such as paper, and mechanical such as a motor, a roller, and an organic photo conductor. It consists of a device. Here, the engine controller 40 includes a processor (not shown), a random access memory (not shown), and a flash ROM (or mask ROM, EPROM, etc., etc.) in which a program for driving the processor is stored. In response to the image data, it controls the operation of mechanical devices such as motors, rollers, and photosensitive drums.

2A and 2B show internal block diagrams of the image processing unit 20 and the engine control unit 40 shown in FIG. 1, respectively.

First, the image processing unit 20 illustrated in FIG. 2A includes a processor (CPU) 23 and a processor which generally control the interface unit 21 to receive print data from the host computer 10, and the image processing unit 20. (ROM) 22, which stores a control program for driving the (CPU) 23 and various application programs, data according to a program execution result of the processor (CPU) 23, and which is applied from the host computer 10 And a random access memory (RAM) 24 for temporarily storing data generated in the process of processing print data, and an EEPROM 25 for storing initial conditions, control setting values, and the like of the image processing unit 20.

Next, the engine control unit 40 shown in FIG. 2B has a ROM 41 (ROM) for loading the control program to the processor (CPU) 42 which the engine control unit 20 executes initially upon turn-on or reset. Random access for storing temporary data according to the execution of the program of the processor (CPU) 42 and the processor (CPU) 42 according to the program stored in the ROM 41 (ROM). Memory (RAM) 43, EEPROM 44 for storing control data of the engine mechanism 60 and setting values for setting the operating state, and an interface between the engine mechanism 60 and the processor (CPU) 42 It has an engine interface unit 45 to provide.

As described above, the conventional engine control unit 40 and the image processing unit 20 are formed on independent electronic circuit boards, and each of the electronic circuit boards has processors 23 and 42 and ROMs 22 and 41. , Random access memories 24, 43, and EEPROMs 25, 44. Accordingly, a separate interface circuit (not shown) is required for data transmission between the processor 23 and the processor 42. For example, when the processors 23 and 42 support different input / output interfaces, an interface circuit for converting the data format between the two processors 23 and 42 is necessary. Such an interface circuit increases the manufacturing cost of the image forming apparatus and has a problem of reducing the data transfer speed between the processors 23 and 43.

3 shows a schematic cross-sectional view of the engine mechanism 60 shown in FIG. 1.

The illustrated engine mechanism 60 has a layer that can be electrically charged and has a photosensitive drum 61 and a charging section 62 for charging the photosensitive drum 61 where a potential difference is generated at the place where it is charged by exposure of a light source. And converts the electrical signal of the image data to be formed into an optical signal and scans the photosensitive drum 61 to the exposure unit (LSU) 63 and the photosensitive drum 61 for forming an electrostatic latent image due to an electric potential difference. The developing unit 64 for supplying and developing the toner for each color in sequence, the transfer unit 65 for transferring the toner image formed on the photosensitive drum 61 to the printing paper P, and the toner transferred to the printing paper P. And a fixing unit 66 for fixing the image to the printing paper P.

The developing unit 64 includes four toner reservoirs 64a to 4 that are developed by sequentially supplying color toners of four colors yellow (Y), magenta (M), cyan (C), and black (B) to the photosensitive drum 61. 64 d), and the color toner stored in the toner reservoirs 64a to 64d is supplied to the photosensitive drum 61 by a rotational motion. Reference numeral 64e denotes a developing roller for applying yellow color toner to the photosensitive drum 61, and is provided in the color toners 64b to 64d one by one.

The transfer unit 65 transfers the transfer belt 65a to be a moving medium of the toner image formed on the photosensitive drum 61, and the first transfer roller 65b to transfer the toner image of the photosensitive drum 61 to the transfer belt 65a. And a second transfer roller 65c for transferring the toner image of the transfer belt 65a to the printing paper P. FIG.

In the image forming apparatus configured as described above, the electrostatic latent image is formed on the photosensitive drum 61 by scanning the laser beam by the exposure unit 63 to the photosensitive drum 61 charged at a constant potential by the charging unit 62. .

Next, the electrostatic latent image is developed by the developing unit 64. In this case, each of the color toners 64a to 64d in order of the colors of yellow, magenta, cyan and black is applied to the rotation of the developing unit 64. Accordingly, the developing operation is performed while being sequentially applied to the photosensitive drum 61.

The visible color image formed on the photosensitive drum 61 by the above developing process is superimposed on the transfer belt 65a, and the image of the transfer belt 65a is transferred to the transfer belt 65a and the second transfer roller 65c. Is transferred to the printing paper P passing through).

The printing paper on which the image has been transferred continues through the fixing unit 66, where the image is fixed on the printing paper P and then discharged.

4 shows a harness arrangement diagram of the image forming apparatus including the image processing unit 20, the engine control unit 40, and the engine unit 60 shown in FIGS. 1 to 3.

As shown, the photosensitive drum 61, the charging unit 62, the exposure unit (LSU) 63, the developing unit 64, the transfer unit 65, and the fixing unit constituting the engine mechanism 60 ( The harness guide 70 for protecting the wires and the signal lines supplied to the 66 is disposed at the edges of the image processing unit 20 and the PCBs 20a and 40a of the engine control unit 40. The PCB 20a of the image processing unit 20 and the PCB 40a of the engine control unit 40 are designed and arranged in two, considering the convenience of upgrading and designing the image processing unit 20, and the image processing unit 20. ) And the PCBs 20a and 40a of the engine control unit 40 are provided with a processor (CPU), a random access memory (RAM), and a ROM (ROM) required for each control.

As described above, the image processing unit 20 and the engine control unit 40 are formed on separate PCBs 20a and 40a, respectively, and the image processing unit 20 and the engine control unit 40 are each a microprocessor (CPU), Random access memory (RAM), ROM, and EEPROM. By forming the image processing unit 20 and the engine control unit 40 on separate PCBs 20a and 40a as described above, functions of an image forming apparatus such as a laser printer (for example, increase resolution / print speed, add a copy function, and add a fax function, etc.) In the case of adding and upgrading, it can be solved by replacing only the PCB in which the image processing unit 20 is embedded, but when performing the function addition and upgrading in this manner, the image processing unit 20 and the engine control unit 40 Since a separate PCB having a processor (CPU), a random access memory (RAM), and a ROM has to be redesigned, the manufacturing cost of the image forming apparatus increases. In addition, when the engine controller 40 is upgraded, a problem arises in that the image processor 20 interfacing with the engine controller 40 must be redesigned accordingly. In this case, after redesigning the engine control unit 40 and the image processing unit 20, the reliability test should be performed on each of the PCBs 20a and 40a, and the electromagnetic wave safety verifier for the two PCBs 20a and 40a. Since the EMI test needs to be additionally performed, there is a problem in that the time and cost for the redesign are increased. In addition, since the PCBs 40a and 20a of the engine control unit 40 and the image processing unit 20 have independent processors 42 and 23, respectively, a separate interface circuit (not shown) for interfacing them should be provided. . In order to transmit a simple control command or exchange information such as status information between the engine control unit 40 and the image processing unit 20, a low speed serial bus may be used, but control for print data and print control transmitted from the image processing unit to the printing engine unit. The signal is preferably transmitted at a very high speed. Moreover, in the case of the color image forming apparatus, it is required that the transmission speed of print data and control signals for print control be higher.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to increase the print processing performance of an image forming apparatus or to reduce the time and cost required for redesign when adding a new function. The present invention provides a PCB design method and an image forming apparatus. In addition, another object of the present invention is to provide an image forming apparatus and a PCB arrangement method of the image forming apparatus that can increase the data transfer speed between the engine control unit and the image processing unit.

1 is a block diagram of a conventional laser printer,

2A and 2B are internal block diagrams of the image processing unit and the engine control unit shown in FIG. 1;

3 is a cross-sectional view of the engine mechanism shown in FIG.

4 is a layout diagram of a harness of the image forming apparatus including the image processing unit, the engine control unit, and the engine mechanism shown in FIGS. 1 to 3;

5 is a conceptual diagram for conceptually explaining the present invention;

6 is a view for explaining a preferred PCB arrangement of the image processing unit and the engine control unit shown in FIG.

7 is a view for explaining a connection relationship between the processor and the engine control unit implemented in the ASIC shown in FIG.

8 is a flow chart according to a preferred embodiment of the PCB arrangement method of the image forming apparatus according to the present invention, and

9 is a flow chart according to another embodiment of the PCB arrangement method of the image forming apparatus according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: PCB 110: image processing unit

110a: Zone 1 111: Processor

112: random access memory 113: flash ROM

114: EEPROM 120: engine control unit

120a: Zone 2 130, 140, 150: Connector

According to the present invention, an engine mechanism for performing a print operation on print data, an image processing unit for converting the print data into a form of image data recognizable by the engine mechanism, and a print job for the image data are executed. And an engine control unit for controlling the engine mechanism to be performed, wherein the engine control unit and the image processing unit are respectively disposed on a single PCB divided into a first zone and a second zone, and the engine control unit is disposed in the first zone. The image processing unit is arranged in the second zone, and the engine control unit and the circuit elements shareable by the image processing unit are arranged in the second zone.

Preferably, the image processing unit and the engine control unit are connected by a bidirectional parallel bus.

Preferably, the image processing unit includes one processor, and the engine control unit is driven by the control of the processor.

The engine control unit is preferably implemented as a custom integrated circuit.

Advantageously, said processor and said application specific integrated circuit are disposed opposite each other.

The engine control unit may include at least one connector for interfacing with the engine mechanism, and the connector may be disposed to face the connection pins provided in the application specific integrated circuit in a vertical and horizontal direction.

The sharable circuit element is preferably at least one of a random access memory, a flash ROM, and a ROM.

Preferably, the engine controller shares at least one or more of the random access memory, the flash ROM, and the ROM by the image processor.

Preferably, the engine control unit shares at least one or more of the random access memory, the flash ROM, and the ROM with the image processing unit.

The image processing unit may further include a connector for receiving the print data, and the connector may be disposed to face the connection pins provided in the image processing unit in the vertical and horizontal directions.

The above object is, according to the present invention, an engine mechanism for performing a print job for the print data, an image processing unit for converting the print data into a form of image data recognizable by the engine mechanism, and a print job for the image data And an engine control unit for controlling the engine mechanism to perform an operation, wherein the engine control unit and the image processing unit are each implemented as a processor and an application specific integrated circuit, wherein the processor and the application specific integrated circuit are directly connected by a bidirectional bus. Implemented by the device.

Preferably, the application specific integrated circuit generates a control signal for driving the engine mechanism in response to the image data applied from the image processing unit.

Advantageously, said application specific integrated circuit further comprises a memory for storing state information of said engine mechanism.

The processor reads the state information stored in the memory, checks the state of the engine mechanism, and then controls the application specific integrated circuit to transmit the image data to the engine control unit to perform a print job.

Preferably, the bidirectional bus includes at least one of an address bus, a data bus, and a control bus, and is implemented as a parallel bus.

Preferably, the processor and the application specific integrated circuit are directly connected by the bidirectional bus and disposed to face each other.

The image processing unit and the engine control unit are each disposed on a single PCB having at least one divided area, and are preferably directly connected by the bidirectional bus on the single PCB.

The engine control unit may include at least one connector for connecting with the engine mechanism, and the connector may be disposed to face the connection pins provided in the application specific integrated circuit in horizontal and vertical directions.

The above object is, according to the present invention, an engine mechanism for performing a print job for the print data applied from an external device, an image processing unit for converting the print data applied from the external device into the form of image data, and the image A method of arranging an image forming apparatus on a single PCB comprising an engine control unit for controlling the engine mechanism to perform a print operation on data, the method comprising: dividing the PCB into a first zone and a second zone; and A processing unit and the engine control unit are disposed in the first zone and the second zone, respectively, and the circuit elements shareable by the image processing unit and the engine control unit are achieved by disposing in the first zone.

Advantageously, disposing in said first zone further comprises installing a connector in said first zone for interfacing with said engine mechanism.

The connector is preferably disposed at at least one of the edges of the PCB corresponding to the first zone.

It is preferable that the circuit element which can be used jointly is at least one or more of random access memory, flash ROM, and ROM.

Preferably, the engine control unit shares at least one or more of the random access memory, flash ROM, and ROM with the image processing unit.

The image processing unit may be disposed in the second zone and include a connector for interfacing with the external device, and the connector for interfacing with the external device may be disposed to face the image processing unit.

The above object is, according to the present invention, an engine mechanism for performing a print job for the print data applied from an external device, an image processing unit for converting the print data applied from the external device into the form of image data, and the image In the PCB arrangement method of the image processing unit and the engine control unit in the image forming apparatus including an engine control unit for controlling the engine mechanism to perform a print job for the data, the image processing unit and the engine control unit to arrange the single PCB And connecting the image processing unit and the engine control unit arranged on the single PCB to a bidirectional parallel bus.

Preferably, the image processing unit and the engine control unit are implemented as processors and application specific integrated circuits.

Preferably, the image processing unit and the engine control unit are disposed to face each other.

Hereinafter, the present invention will be described in detail with reference to the drawings.

5 is a conceptual diagram for conceptually explaining the present invention.

Referring to Figure 5 briefly look at the concept of the present invention.

The image forming apparatus according to the present invention includes an image processing unit 110 for converting print data applied from an information processing device such as a host computer (not shown) into image data in a bitmap format, and image data from the image processing unit 110. It is controlled by the engine control unit 120 to control the engine mechanism (not shown) to implement a predetermined image on a printing medium such as paper, the image processing unit 110 and the engine control unit 120 is a single PCB When placed on a printed circuit board (hereinafter referred to as "PCB") 100, a single PCB is divided into two zones according to the required area of the image processing unit 110 and the engine control unit 120 in the step of designing the PCB 100. It divides into (110a, 120a). Connectors 130, 140, and 150 for data transmission between the engine control unit 120 and an engine mechanism (not shown) are disposed at an edge of the area 120a in which the engine control unit 120 is disposed among the divided areas. Here, the engine control unit 120 is an application specific integrated circuit (ASIC) for controlling mechanical devices such as a motor, a roller, and an organic photo conductor for driving the image forming apparatus. Integrated Circuit), and the input / output connection pins provided in the integrated circuit may face the connectors 130, 140, and 150 provided at the edges. Accordingly, the input and output connection pins (not shown) and the connectors 130 to 150 provided in the engine control unit 120 are connected at the shortest distance and thus have strong characteristics against external noise. Similarly, the engine control unit 120 and the image processing unit 110 may be disposed to face each other so as to be less affected by external noise. In this case, by implementing the engine controller 120 as a custom integrated circuit, there is no need to provide a separate interface circuit for interfacing between the processor 111 and the engine controller 120 included in the image processor 110, and the engine controller. The 120 and the processor 111 may be connected by a bidirectional parallel bus. This increases the amount of data transmission per unit time and can reduce the space and material costs for building a separate interface circuit.

When the engine controller 120 is implemented as an application specific integrated circuit (hereinafter, referred to as an "ASIC"), the engine controller 120 may include a separate processor, a random access memory, and a flash ROM in which a program for driving the processor is stored. Or a mask ROM, EPROM, etc.), and the engine controller 120 implemented as an ASIC shares what is provided in the image processor 110.

On the other hand, the image processing unit 110 includes a processor (CPU) 111, a random access memory (RAM) 112, a flash ROM 113, and an EEPROM 114, and includes a processor (CPU) ( The random access memory (RAM) 112, the flash ROM 113, and the EEPROM 114 except for the 111 are shared with the engine controller 120 implemented as an ASIC. That is, the engine controller 120 is implemented with only a minimum of circuit elements for directly controlling a mechanical device such as a motor, a roller, and an organic photo conductor (OPC) drum, and random access memory (RAM). The 112, the flash ROM 113, and the EEPROM 114 are configured to share what is provided in the image processing unit 110. Accordingly, when increasing the image display capability of the image processing unit 110, only the image processing unit 110 needs to be redesigned without having to redesign the engine control unit 120, and reliability tests such as EMI verification have already been performed. Since the engine control unit 120 in the completed state can be reused as it is, the time and cost required for the redesign are reduced. In addition, since the engine controller 120 shares the random access memory (RAM) 112, the flash ROM 113, and the EEPROM 114 with the image processing unit 110, components of the image processing apparatus are reduced. Has an effect.

6 is a view for explaining a preferred PCB arrangement of the image processing unit 110 and the engine control unit 120 shown in FIG.

As shown, the PCB arrangement of the present image processing apparatus receives the print data output from an information processing apparatus such as a personal computer (not shown), and processes the image data into a bitmap format image data. Is disposed in the zone A, and the engine control unit 220 is disposed in the zone B in response to the image data output from the image processing unit 210 to cause the engine mechanism to implement a predetermined image on a print medium such as paper.

The image processor 210 includes a processor 211, a random access memory (RAM) 212, a flash ROM 213, and an EEPROM 214. The processor 211 includes an input / output controller 211a, And a CPU core 211b, an image data generation unit (PVC) 211c, and an engine interface unit 211d.

The image processing unit 210 receives the print data applied from the information processing apparatus such as a personal computer from the IEEE 1284 port (parallel printer port) 210b from the input / output control unit 211a and receives the image data generation unit (the CPU core 211b). PVC) 211c to generate image data in a format such as a bitmap.

At this time, the image data generation unit (PVC) 211c needs a predetermined memory space for image processing, generates temporary data in the random access memory (RAM) 212 via the CPU core 211b, The final processed temporary data is again output to the engine interface 211d via the image data generation unit (PVC) 211c. Here, the data transfer path for image processing is performed by the CPU core 211b according to the control program stored in the flash ROM 213.

The EEPROM 214 stores an initial condition or control setting value of the image processing unit 210, a setting value for setting control data or an operation state of the engine control unit 220. That is, all of the initial values and the set values required by the image processing unit 210 and the engine control unit 220 are stored.

The engine control unit 220 is composed of a single application specific integrated circuit (ASIC), the ASIC is the engine interface unit 220a, the ASIC core 220b, the pattern generator 220c, the laser scanning unit 220d, the motor controller ( 220e) and an analog-to-digital converter (ADC) 211f.

The engine controller 220 receives image data output from the engine interface 211d of the image processor 210 through the engine interface 220a and interprets the image data in the ASIC core 220b. According to the analysis result of the ASIC core 220b, the pattern generator 220c generates a pattern for an image to be generated by an engine mechanism (not shown) and drives the laser scanning unit 220d based on the pattern generator 220c. The laser scanning unit 220d forms an electrostatic latent image on the photosensitive drum according to the result generated by the pattern generator 220c (see FIG. 4).

The motor controller 220e controls the motor driving the image forming apparatus according to the analysis result of the ASIC core 220b. In this case, an analog sensor (not shown) for monitoring the operation of the motor is typically provided in the engine mechanism, and the analog-to-digital converter (ADC) 211f senses this and feeds it back to the ASIC core 220b. The feedback sensing result is stored in the register 220g via the ASIC core 220b. The sensing result stored in the register 220g is applied to the processor 211 by the ASIC core 220b in response to the call of the processor 211.

Meanwhile, the engine control unit 220 implemented as an ASIC is disposed to face the connectors 220h, 220i, and 220j disposed on the edge of the PCB. For example, the motor controller 220e is connected to the connector 220h in the vertical direction, the analog-digital converter (ADC) 220f is connected to the connector 220i in the horizontal direction, and the laser scanning unit 220d is connected to the connector ( 220j) in the vertical direction. That is, the connector for interfacing the engine control unit 220 and the engine mechanism is disposed to face the input and output connection terminals provided in the engine control unit 220 having an ASIC in the vertical and horizontal directions. Accordingly, the engine controller 220 may be connected to the connectors 220h, 220i, and 220j in the shortest distance. In addition, when the image processor 210 needs to be redesigned to increase the performance of the image forming apparatus, for example, print resolution, and speed, it is necessary to redesign the engine controller 220 having only a function of controlling the engine mechanism. This can be achieved by redesigning only the image processor 210. Therefore, since the redesign process for the engine controller 220 whose EMI characteristics have already been verified can be omitted, the time and cost required to redesign the image forming apparatus can be reduced. In addition, since the engine controller 220 shares the random access memory (RAM) 212, the flash ROM 213, and the EEPROM 214 included in the image processor 210, image forming according to the present invention. The PCB of the device is smaller in size and can be implemented at a lower cost than the PCB of the conventional image forming apparatus.

FIG. 7 is a diagram illustrating a connection relationship between the processor (CPU) 211 and the engine control unit 220 implemented with the ASIC shown in FIG. 6.

As shown, the processor (CPU) 211 is connected by a random access memory (RAM) 212, a Flash Rom 213, and a parallel bus composed of N bits with the EEPROM 214, The engine control unit 220 is also connected to the N-bit parallel bus. The engine control unit 220 is implemented as an ASIC (Aplication Specific Integrated Circuit) controlled by a processor rather than a separate processor, and thus has a characteristic close to a passive device. Therefore, a separate interface circuit is not required between the engine control unit 220 and the processor (CPU) 211 implemented as an ASIC. The processor (CPU) 211 and the engine control unit 220 implemented as an ASIC are connected to an N-bit address bus addr, a data bus, and a control bus ctrl. As such, the signal transmission speed between the engine control unit 220 and the processor 211 implemented by the ASIC by the N-bit parallel bus is much faster than a method using a separate interface circuit. The difference in the transmission speed is apparent in the image forming apparatus for color printing rather than the image forming apparatus for black and white printing, and the difference in printing speed becomes larger as the print data to be printed by the image forming apparatus increases. Here, the address bus (Addr) and the data bus (data) formed between the processor (CPU) 211 and the engine control unit 220 implemented as an ASIC for the engine mechanism from the register 221 provided in the engine control unit 220. Required to get status information. The register 221 responds to an address and a read command applied from the processor 221 to the engine controller 220 implemented as an ASIC, and the state information stored in the register 221 is transmitted through a data bus. It is fed back to the processor (CPU) 221.

On the other hand, according to the above-described configuration, since the circuit elements such as the CPU core 211b, the Flash Rom 213, and the EEPROM 214 are all disposed in the A zone, the image forming apparatus according to the present invention. System diagnostics is very simple compared to the conventional features. In the image forming apparatus according to the present invention, the rest of the image forming apparatus except for the engine controller 220 for driving the engine mechanism is disposed in an area A where the image processor 210 is located, except for an error generated in the engine controller 220. All errors may be determined to occur in the area A, and since the random access memory (RAM) 212, the flash ROM 213, and the EEPROM 214 are not included in the engine controller 220, Compared to a conventional image forming apparatus having a processor, a random access memory, and a flash ROM in each of the image processor 210 and the engine controller 220, the time required for system diagnosis is shortened.

In the above description based on a PCB divided into two regions, the present invention is not limited to the described embodiment, and the same applies to a single PCB that is not divided. For example, when the image processing unit 210 and the engine control unit 220 are disposed on a single non-divided PCB, the image processing unit 210 and the engine control unit 220 disposed on the single non-divided PCB are disposed to face each other. It may be connected by a bidirectional parallel bus. In this case, the image processing unit 210 and the engine control unit 220 formed on the non-divided PCB also have the above-described characteristics, for example, an increase in data transmission speed due to bidirectional parallel connection between the image processing unit 210 and the engine control unit 220. , A characteristic that does not require an additional interface circuit between the image processing unit 210 and the engine control unit 220, and the image processing unit 210 and the engine control unit 220 provide a random access memory (RAM) 212 and a flash ROM. Rom) 213 and the EEPROM 214, such as a circuit element can be shared. However, by dividing a single PCB into two areas (A area and B area), it is possible to further reduce design time and reliability test time when designing an image forming apparatus. Since the description thereof is substantially overlapped with those described in FIGS. 5 and 6, it will be omitted below.

8 is a flow chart according to a preferred embodiment of the PCB arrangement method of the image forming apparatus according to the present invention.

First, the image processing unit 210 converts print data applied from an information processing apparatus such as a host computer into image data in a bitmap format, and is controlled by the image data from the image processing unit 210 to control paper and paper. When the engine control unit 220 for controlling the engine mechanism (not shown) for implementing a predetermined image on the same print medium is formed on a single PCB 200, the PCB 200 is divided into two zones, namely, A zone and B zone. In step S410, the image processing unit 110 and the engine control unit 120 are arranged for each zone (S420).

Next, it is determined whether there is a circuit element that can be shared by the image processing unit and the engine control unit disposed in the A and B zones, respectively (S430). As a result of the determination, a circuit element that can be shared by the engine control unit 220 and the image processing unit 210, for example, a random access memory (RAM) 212, a flash ROM 213, and an EEPROM 214 is formed into an image processing unit ( 210 is to be placed in the zone A is located (S440). The engine controller 220 includes a processor including a random access memory (RAM) 212, a flash ROM 213, and an EEPROM 214 connected to the image processor 210 in the image processor 210. A random access memory (RAM) 212, a flash ROM 213, and an EEPROM 214 are disposed in an ASIC type engine control unit 220 disposed in a zone B by accessing the CPU 211. When redesigning the image forming apparatus, the engine control unit 220 whose reliability test, such as EMI, has been verified can be reused, thereby reducing the time and cost required for the redesign.

The engine control unit 220 implemented in the form of an ASIC is directly connected to the processor (CPU) 211 by an address bus (Addr), a data bus (data), and a control bus (ctrl). Accordingly, since the separate interface circuit for interfacing the engine control unit 220 and the processor (CPU) 211 is not disposed on the PCB, the space of the PCB can be used more efficiently.

Next, elements that are not shared between the engine controller 220 and the image processor 210 are disposed in respective regions (S450). Finally, a connector (for example, 220h, 220i, and 220j) for interfacing between the engine mechanism and the engine control unit 220 is disposed in the zone B, and is disposed at the edge of the PCB allocated to the zone B (S460). At this time, the connector is preferably disposed to face in the vertical or horizontal direction with the input and output connection pin provided in the engine control unit 220 implemented as an ASIC. That is, the input / output connecting pins and the connector terminals (not shown) of the ASIC are preferably connected in a straight line. This wiring method simplifies the form of the metal wiring connected between the engine control unit 220 and the connectors 220h, 220i, and 220j, which are implemented as an ASIC, so that when a failure occurs in the image forming apparatus, diagnosis and repair are easy. There is an advantage, and it is easy to reduce noise generated between metal wirings. For example, when the metal wiring connected between the engine control unit 220 implemented as an ASIC and the connectors 220h, 220i, and 220j has a predetermined spacing and pattern, the ground plane is opposite to the surface of the PCB on which the metal wiring is located. By forming a ground plate, each metal wire has the effect of being shielded by the ground plane, and has a strong resistance to noise from the outside.

On the other hand, the image processing unit 210 is disposed in zone A, and the image processing unit 210 having a form of a system-on-chip (SOC) is disposed to face the engine control unit 220 implemented as an ASIC. The pin direction of 220 and the pin direction of the image processor 210 are disposed to face each other in a horizontal or vertical direction, so that the image controller 210 and the engine controller 220 may be connected to each other in the shortest distance.

9 is a flow chart according to another embodiment of the PCB arrangement method of the image forming apparatus according to the present invention.

First, the image processor 210 and the engine controller 220 are disposed on a single PCB, but the image processor 210 and the engine controller 220 are disposed to face each other (S510). Next, it is determined whether the input / output connection pins provided in the image processing unit 210 and the engine control unit 220 disposed on the PCB can be directly wired in the vertical or horizontal direction (S520). As a result of the determination, the image processing unit ( 210 and the engine control unit 220 are connected to the bi-directional parallel bus (S530). At this time, the parallel bus is a data bus (data), an address bus (Addr), and a control bus (ctrl) consisting of N bits, it is possible to transmit a signal faster than the conventional serial bus. Conventionally, since each of the image processor 210 and the engine controller 220 includes a separate processor, an interface circuit for interfacing between processors is required, and a serial protocol (for example, a serial bus such as RS232) provided in the processor is used. However, in the present embodiment, by implementing the engine control unit 220 as an ASIC, a separate interface circuit is not required. Finally, a connector for interfacing between the engine mechanism and the engine controller 220 is disposed to face the input / output connecting pin provided in the engine controller 220 in the vertical or horizontal direction (S540). Accordingly, the PCB arrangement method according to the present embodiment can reduce the number of circuit elements required compared to the conventional arrangement method of forming the engine control unit 220 and the image processing unit 210 on a separate PCB, a single PCB The high speed bidirectional parallel bus can be connected between the engine controller 220 and the image processor 210. This PCB arrangement method is not meaningful to simply reduce the two PCBs for arranging the engine control unit 220 and the image processing unit 210 to one sheet, and by adopting a high-speed parallel bus on a single PCB in the future, the engine control unit ( A design method that can cope with an increase in the amount of data between the 220 and the image processor 210 is provided.

Although the image forming apparatus and the PCB arrangement method described above have been described mainly for black and white and color laser printers, this is to help the understanding of the present invention, in addition to the inkjet, bubble jet printer, fax and scanner including a motor The same applies to other image forming apparatuses including a mechanical driving unit and an image processing unit. Therefore, the present invention should not be limited according to the embodiment described above.

As described above, the present invention reduces the time and cost required to redesign the engine control unit and the image processing unit when upgrading the function of the image forming apparatus or adding a new function. In addition, the present invention can reduce the manufacturing cost of the image forming apparatus by sharing the random access memory (RAM), flash ROM, and EEPROM provided in the image processing unit in the engine control unit, the engine control unit purely engine Redesigning the image processing unit by controlling only the mechanism does not require redesign of the engine control unit. The present invention can also cope with an increase in the amount of data between the engine control unit and the image processing unit in the future by arranging the image processing unit and the engine control unit on a single PCB and connecting the arranged image processing unit and the engine control unit with bidirectional parallel buses. In addition, the present invention simplifies the wiring between the engine control unit, the image processing unit, and the connector to increase resistance to noise from the outside or the inside.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the present invention is not limited to the specific embodiments of the present invention without departing from the spirit of the present invention as claimed in the claims. Anyone of ordinary skill in the art can make various modifications, as well as such changes are within the scope of the claims.

Claims (27)

An engine mechanism for performing a print job on the print data; An image processing unit converting the print data into a form of image data recognizable by the engine mechanism; And And an engine control unit controlling the engine mechanism to perform a print job on the image data. The engine controller and the image processor are respectively disposed on a single PCB divided into a first zone and a second zone, the engine controller is disposed in the first zone, and the image processor is disposed in the second zone. And a circuit device in which the engine control unit and the image processing unit can be shared are disposed in the second zone. The method of claim 1, And the image processing unit and the engine control unit are connected by a bidirectional parallel bus. The method of claim 1, And the image processor comprises one processor, and wherein the engine controller is driven by control of the processor. The method of claim 3, The engine control unit, An image forming apparatus, characterized in that implemented on demand integrated circuit. The method of claim 4, wherein And the processor and the application specific integrated circuit are disposed to face each other. The method of claim 5, The engine control unit, And at least one connector for interfacing with the engine mechanism, wherein the connector is disposed to face the connection pins provided in the application specific integrated circuit in a vertical and horizontal direction. The method of claim 1, The shareable circuit device, And at least one of a random access memory, a flash ROM, and a ROM. The method of claim 7, wherein The engine control unit, And at least one of the random access memory, the flash ROM, and the ROM is shared by the image processing unit. The method of claim 1, The image processing unit, And a connector for receiving the print data, wherein the connector is disposed to face the connection pins provided in the image processing unit in the vertical and horizontal directions. An engine mechanism for performing a print job on the print data; An image processing unit converting the print data into a form of image data recognizable by the engine mechanism; And And an engine control unit controlling the engine mechanism to perform a print job on the image data. And the engine control unit and the image processing unit are each implemented as a processor and an application specific integrated circuit, and the processor and the application specific integrated circuit are directly connected by a bidirectional bus. The method of claim 10, The application specific integrated circuit, And a control signal for driving the engine mechanism in response to the image data applied from the image processing unit. The method of claim 10, The application specific integrated circuit, And a memory for storing state information of the engine mechanism. The method of claim 12, The processor, And reading the state information stored in the memory to check the state of the engine mechanism, and controlling the application-specific integrated circuit to transmit the image data to the engine control unit to perform a print job. The method of claim 10, The bidirectional bus, An image forming apparatus comprising at least one of an address bus, a data bus, and a control bus, and implemented as a parallel bus. The method of claim 14, The processor and the application specific integrated circuit, And are directly connected by the bidirectional bus and disposed to face each other. The method of claim 10, The image processing unit and the engine control unit, And are respectively disposed on a single PCB having at least one divided area, and directly connected by the bidirectional bus on the single PCB. The method of claim 10, The engine control unit, At least one connector for connecting with the engine mechanism, And the connector is disposed to face the connection pins provided in the application specific integrated circuit in horizontal and vertical directions. An engine mechanism for performing a print job on print data applied from an external device, an image processing unit converting the print data applied from the external device into a form of image data, and performing a print job on the image data; In the method for arranging an image forming apparatus including an engine control unit for controlling the engine mechanism on a single PCB, Dividing the PCB into a first zone and a second zone; And And arranging the image processing unit and the engine control unit in the first zone and the second zone, respectively, wherein the circuit elements shareable by the image processing unit and the engine control unit are arranged in the first zone. PCB placement method of the image forming apparatus. The method of claim 18, Placement in the first zone, And installing a connector for interfacing with the engine mechanism in the first zone. The method of claim 18, The connector, And at least one of the edges of the PCB corresponding to the first zone. The method of claim 18, The circuit element that can be used jointly, At least one of a random access memory, a flash ROM, and a ROM. The method of claim 18, The engine control unit, And at least one of the random access memory, the flash ROM, and the ROM is shared with the image processor. The method of claim 18, The image processing unit, And a connector for interfacing with the external device, wherein the connector for interfacing with the external device is disposed to face the image processing unit. An engine mechanism for performing a print job on print data applied from an external device, an image processing unit converting the print data applied from the external device into a form of image data, and performing a print job on the image data; In the image forming apparatus including an engine control unit for controlling an engine mechanism, the image processing unit and the PCB control method of the engine control unit, Disposing the image processing unit and the engine control unit on a single PCB; And And connecting the image processing unit and the engine control unit arranged on the single PCB to a bidirectional parallel bus. The method of claim 24, The image processing unit and the engine control unit, PCB placement method of an image forming apparatus, characterized in that each is implemented by a processor and a custom integrated circuit. The method of claim 24, The image processing unit and the engine control unit, PCB placement method of the image forming apparatus, characterized in that disposed opposite to each other. The method of claim 26, The engine control unit, And installing a connector for interfacing with the engine mechanism at any one end of the single PCB.