KR20040019485A - refresh type semiconductor memory device having refresh circuit for minimizing refresh fail at high speed operation - Google Patents

Abstract

PURPOSE: A refresh type semiconductor memory device having a refresh circuit is provided to minimize refresh fail at high speed operation. CONSTITUTION: According to the refresh type semiconductor memory device performing data input/output as performing a refresh operation internally without an external command, a main pulse generator(320) disables a refresh request operation block signal in response to a signal responding to active transition of a write enable signal and a dummy refresh signal generated during a read operation, in order to prevent refresh fail which is generated during a continuous write operation. The signal responding to the active transition of the write enable signal and the dummy refresh signal are pulse signals.

Description

Refresh type semiconductor memory device having a refresh circuit for minimizing refresh fail in high speed operation {refresh type semiconductor memory device having refresh circuit for minimizing refresh fail at high speed operation}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a refresh type semiconductor memory device having a refresh circuit for minimizing refresh fail in high speed operation.

In general, random access memory (RAM) stores input data in an array of individually addressable reservoirs known as memory cells. Two basic memory cells are commonly used, one is a DRAM cell and the other is an SRAM cell. The SRAM cell has a static latch structure that can store data indefinitely while power is applied, such as six transistors or four transistors and two resistors.

The DRAM cell has one access transistor and one storage capacitor. Since charge leakage occurs in capacitors, DRAM cells are characterized by the inability to permanently store data. Discharge of the charge charged in the capacitor results in data loss. In order to prevent such data loss, DRAM cells require periodic refresh operations. In other words, the charge charged in the capacitor of the memory cell must be recharged before the discharged to a certain amount. This periodic refresh operation is performed for each cell several times per second by the refresh circuit to prevent data loss.

Despite the operational features requiring refresh, DRAMs have other advantages over SRAMs. That is the size of the memory cell, which is much smaller than the SRAM memory cells fabricated through similar processes. The reduced size makes the device less expensive and allows more data to be stored in the same area. Therefore, it is desirable to develop DRAMs that can replace SRAM without imposing additional external operating conditions on the peripheral circuits.

BACKGROUND ART A refresh type semiconductor memory device that uses a DRAM cell requiring refreshing and performs the same timing operation as an SRAM product has been disclosed in several prior arts. Such refresh type semiconductor memory devices have been variously referred to in the art as PRAM (Pseudo SRAM), VSRAM (Virtual SRAM), UtRAM (Unit transistor RAM), or pseudo static memory device. The memory device is often mounted in a portable electronic device in the form of a multi-chip package.

As one of the prior arts related to a refresh type semiconductor memory device, application number 09 / 609,200, which was invented by Kim Chang-rae et al. And filed with the US Patent Office on June 30, 2000, has zero light recovery time and maximum light cycle. Disclosed are a semiconductor memory device capable of performing both a refresh operation and a read / write operation such that there is no time limit, and a method of operating the same.

1A shows the configuration of a semiconductor memory device 90 described in the patent. In the apparatus 90, the memory cell array 200 is composed of refresh type memory cells such as DRAM cells, word lines WL, and bit lines BL. Each memory cell is connected to one word line and one bit line. The row decoder 140 and the column decoder 150 designate addresses of specific memory cells. During access, the row decoder 140 selects a word line according to the row address signal when the main pulse generator 320 generates a PWLb pulse after the bit line BL is precharged. The selected word line turns on an access transistor inside each memory cell connected thereto so that the storage node of each memory cell and the particular bit line connected to this memory cell share charge. Then, the sense amplifier S / A: 410 is operated by PSA pulses. Each sense amplifier measures the voltage on the bit line to detect whether the memory cell currently connected to a particular bit line is charging or discharging. This detection signal is amplified and refreshed in the memory cell.

In a read or write operation, a read or write operation is performed in one or more cells. When the main pulse generator 320 generates the PCSL pulse, the column decoder 150 selects the column select line CSL according to the column address signal. Each column select line connects one or more corresponding bit lines to the input / output circuitry of the device 90 to allow reading and writing to memory cells connected to a predetermined word line.

Access to the device 90 of the external memory is started by read and write commands. These commands are initiated by signal transitions occurring in one or more external inputs of the address signal ADDi, the chip enable (also referred to as " chip select ") signal CE #, and the external inputs for inputting the write enable signal WE #. For example, a read command is initiated when a new address signal appears in ADDi or CE # is activated (WE # is deactivated in two cases).

Similarly, write commands are initiated in several ways. One way is to activate the WE # signal while the CE # signal is active. Similarly, the write command is initiated even if the CE # signal is activated while the WE # signal is activated. Finally, with both the CE # and WE # signals active, shifting the address on the ADDi can give a new write command.

The address buffer and the address circuit 100 receive and buffer the external signals ADDi and CE #. When one of these signals transitions (and the final state of CE # is enabled), the ATD (Address Transition Detector: 330) generates a short pulse PATD in response to the transition of ADDi and CE #.

The write enable buffer / write circuit 300 receives and buffers the external signals WE # and CE #. WE # is supplied to the read / write pulse control circuit 310 as the buffer signal WEb. If either CE # or WE # transitions and the other is already active, the write enable buffer circuit 300 generates a pulse SPGL_WE. When the WE # change is deactivated, the write enable buffer circuit 300 generates a pulse SPGH_WE.

The read / write pulse control circuit 310 generates internal control signals for operating the multiplexer 130, the main pulse generator 320, and the refresh control circuit 510. The input signals of the control circuit 310 are PATD, WEb, SPGL_WE and SPGH_WE, and PRFH (refresh pulse generated by the refresh control circuit 510). The control circuit 310 generates the refresh select signal RFHTD during the refresh period, generates the write select signal PWTD during the write cycle, and generates the read select signal RATD during the read cycle. In addition, the control circuit 310 controls the refresh control circuit 510 by generating a refresh request operation cutoff signal NERFH when the refresh is disabled.

The multiplexer 130 selects one of three possible address signals when the input address Ai is input to the row decoder 140 and the column decoder 150 using the refresh select signal RFHTD, the write select signal PWTD, and the read select signal RATD. Among them, the first address signal is the internal address Ai_R. When a new address is input to the external address line ADDi, the address buffer circuit 100 stores this address and outputs the stored address to Ai_R when the address corresponds to a read command or a write command. The second address signal is the write address Ai_W. The write address register 110 stores Ai_R during a write cycle and then outputs the stored value to Ai_W until another value is stored during the next write cycle. The third address signal is the refresh address Ai_cnt. In general, the multiplexer 130 selects Ai_R while reading the array 200, selects Ai_W while writing the array 200, and selects Ai_cnt while refreshing the array 200.

The refresh circuit of the device 90 consists of a refresh timer 500, a refresh control circuit 510, a refresh address counter 520, and a read / write pulse control circuit 310.

The refresh timer 500 generates a pulse on the refresh request line SRFHB at regular time intervals. The time interval is adjusted so that the refresh rate can prevent data loss.

The refresh control circuit 510 receives the SRFHB pulse if NERFH is allowed. If NERFH is not allowed, the refresh control circuit 510 does not receive SRFHB pulses.

The refresh address counter 520 counts addresses in a manner that addresses each word line in a predetermined order. When the PRFH is input, the refresh address counter 520 changes the output Ai_cnt.

The read / write pulse control circuit 310 generates the refresh control signals RFHTD and NERFH in response to the input. RFHTD allows for refresh operations. NERFH prohibits refresh operation requests during pulse read and pulse write operations.

In addition, the semiconductor memory device 90 accurately processes write operations such as the write address register 110, the comparator 120, the bypass control circuit 160, the data input register 440, and the data output multiplexer 430. It includes a circuit for performing. The write address register 110 stores the value of Ai_R according to the pulse signal input to SPGH_WE (that is, the end of the external write cycle). At the same time (and in accordance with SPGH_WE), data input register 440 stores data input information in current data input buffer 460. Registers 110 and 440 continue to output these stored values until the next SPGH_WE pulse is input.

FIG. 1B is a timing diagram illustrating a normal read operation for the device of FIG. 1A, and FIG. 1C is a timing diagram illustrating a normal write operation.

Referring first to FIG. 1B, a pulse read operation is triggered when ADDi transitions (to address A0). The ATD circuit 330 generates a short pulse PATD. Within the read / write pulse control circuit 310, the pulse spreader generates an ATDD pulse of length tF and responds to the PATD pulse. The ATDD pulse, also known as "dummy refresh," provides a period of time during which a pending refresh operation can be completed during a normal read cycle. The ATDD pulse also activates NERFH high, preventing the request for a new refresh operation.

At the end of the dummy refresh pulse, a short pulse RATD is generated to start the pulse read operation. This pulse selects Ai_R (including address A0) as the output address Ai of the address multiplexer. The RATD pulse causes the array address pulse PWLb to be generated for read access, thereby allowing WL0 to be selected during a time of predetermined pulse width starting at t1. When the data DQA0 is output from the data output buffer, the pulse read operation ends immediately.

In a pulse read operation, the pulse spreader in the read / write pulse control circuit 310 generates a normal read request (NRR) pulse. The NRR pulse provides enough time to complete the pulse read operation. At the end of the NRR pulse, NERFH is disabled and a refresh request is possible. Here, the section in which refreshing is prohibited has a time tACCESS equal to the sum of the length of the dummy refresh pulse and the length of the normal read request pulse.

Referring to FIG. 1B, three SRFHBs on the SRFHB including SRFHB1, which occurs just before ADDi transitions to A0, SRFHB2, which occurs during NERFH activation, and SRFHB3, which occur during the same external read cycle but after the end of pulse read operation. A refresh request signal with branch timing is shown.

Referring now to FIG. 1C, two external write operations W1 and W2 are described following read operation R3. As the timing diagram starts, the external write operation W0 ends immediately.

External write operation W1 transitions from ADDi to address A1 and begins with write enable WE # going low. Immediately before, WE # transitions high to signal the end of the external write operation W0, and a pulse of SPGH_WE is triggered. Due to this pulse, Ai_W stores A0 from Ai_R, and Din0 is stored in Din.

When the external write operation W1 is started, a pulse write operation is triggered to write Din0 to the cell array at the address corresponding to A0. When WE # goes low, the SPGL_WE pulse is triggered. The read / write pulse control circuit 310 generates a spread pulse WTDD in the dummy refresh section as in the dummy refresh section. At the end of the dummy refresh period, the read / write pulse control circuit 310 generates a short pulse PWTD and generates a spread pulse NWR in response thereto. The end point of the spread pulse defines the end point of the pulse write command. When the PWTD pulse is input, the address multiplexer selects Ai_W (ie A0 in this embodiment) as the address Ai and sends it to the row decoder and column decoder. The PWTD pulse also initiates the write pulse sequence of the main pulse generator to select word line WL0 at time t1. While WL0 is selected, Din0 is written to the memory cell array 200 via the write driver 420.

At the end of the pulse light cycle, the device resumes the refresh operation until an external signal (eg high transition of WE #) signals the end of the external light cycle. When the external signal transitions high, the pulses of SPGH_WE store A1 and Din1 and indicate these values in Ai_W and Din_W, respectively.

The external light cycle W2 follows immediately after the external light cycle. The processing of W2 is similar to the processing of W1 and includes a pulse write operation of writing A1 to the memory cell array. The refresh operation of FIG. 1C is similar to the refresh operation of FIG. 1B described above.

Through the long description so far, we have examined the normal operation and the refresh operation of the refresh type semiconductor memory device having DRAM cells.

Since the semiconductor memory device 90 is recognized as an SRAM by an external system such as a microprocessor, all operations must be performed externally regardless of the refresh operation. Therefore, since the normal active period and the refresh operation period must be guaranteed together during one active cycle, some of the one active cycles are set as the refresh period, and the others are set as the normal active operation period. The refresh blocking window is required to enable such a distinct operation. That is, in the above description, the refresh blocking operation named as the refresh request operation blocking signal NERFH is prohibited from entering the refresh in the high-in period, and the refresh is enabled only in the low-in period, thereby allowing the normal active operation and the refresh operation during one active cycle. This is done together.

It will be fully understood from the above description that the refresh request operation blocking signal NERFH is generated in the read / write pulse control circuit 310 belonging to the refresh circuit of the apparatus 90. However, since the read / write pulse control circuit 310 has the configuration as shown in FIG. 2, it has been observed by the present inventors that the higher the active cycle, the higher the probability of generating a refresh fail. In the following, a reason why a refresh fail is likely to occur without any intention other than intended to provide a more thorough understanding of the present invention described below will be described.

The conventional block configuration of the read / write pulse control circuit 310 of the device configuration of FIG. 1A is shown in FIG. 2.

Referring to FIG. 2, the first refresh access control circuit 311 internally includes a pulse expander that extends a PATD pulse to generate a dummy refresh pulse ATDD. ATDD is applied to the normal read access control circuit 312. The circuit 312 generates a short pulse RATD to initiate a read operation in response to a polling edge of the dummy refresh pulse. In addition, a long pulse NRR is generated to block the refresh operation during the read operation. The NOR gate 313 combines the ATDD and NRR to generate a signal NERFHR. Thus, NERFHR lasts for the sum of the lengths of the ATDD pulses and the NRR pulses (ie, the pulse read access time tACCESS).

The second refresh access control circuit 314 internally includes a pulse spreader for extending the SPGL_WE pulse to generate the dummy refresh pulse WTDD. The WTDD is connected to the normal light access control circuit 315 as an input. Circuit block 315 generates a short pulse PWTD to initiate a write operation in response to the falling edge of the dummy refresh pulse. In addition, a long pulse NWR is generated to interrupt the refresh operation during the write operation. NOR gate 316 combines WTDD and NWR to generate signal NERFHW. Thus, NERFHW lasts for the sum of the lengths of the WTDD and NRW pulses (ie, pulse write access time tACCESS).

The NERFHR and NERFHW are combined by the NOR gate 317 and then make the signal NERFH through the inverter 319. The signal NERFH is a refresh request blocking operation signal and is activated during read and write operations.

3 and 4 are operation timing diagrams related to FIG. 2 and show a case of a long write cycle and a short write cycle, respectively. In the figure, tWC, tWP denotes a light cycle and a light command pulse width.

The device 90 recognizes the operation mode as write operation when WEB (or WE #) is low and read operation when high. Compared to the case of FIG. 3, when the operating frequency increases as shown in FIG. 4, the intervals of tWC and tWP decrease. In the case where the interval decreases more and more, the low interval of NERFH shown in FIG. 3 gradually decreases to finally form a low interval as shown in FIG. 4. After all, due to lack of margin between NERFHW and NERFHR, NERFH remains high without having a low section. If this phenomenon occurs during the continuous write operation, the entry to the refresh operation is blocked, and thus the refresh of the memory cell is not performed. Therefore, the refresh fail is more likely to occur as the operating frequency of the device is higher. When a refresh fail occurs, loss of data stored in the memory cell occurs, thereby degrading the reliability of the semiconductor memory device.

Accordingly, an object of the present invention is to provide a refresh type semiconductor memory device having a refresh circuit for minimizing refresh fail in high speed operation by solving the above-mentioned conventional problems.

Another object of the present invention is to provide a refresh type semiconductor memory device capable of minimizing the probability of occurrence of refresh fail in successive write cycles.

Another object of the present invention is to provide a refresh circuit and a method of generating a refresh request cutoff signal of a refresh type semiconductor memory device capable of improving write cycle time.

In order to achieve most of the above objects, according to an aspect of the present invention, a refresh type semiconductor memory device performing input / output of data while performing a plurality of refresh type memory cells and a refresh operation internally without an external command. In order to prevent a refresh fail that may occur during continuous write operations, the refresh request operation cutoff signal may be disabled in response to a signal in response to an active transition of the write enable signal and a dummy refresh signal generated in a read operation. By providing a refresh circuit having a forced refresh request signal generation unit, the write cycle time is improved and the refresh fail is minimized.

1A to 1C are views provided to explain the structure and operation of a conventional refresh type semiconductor memory device.

FIG. 2 is a detailed detailed block diagram of the read / write pulse control circuit 310 of FIG. 1A.

3 and 4 are operation timing diagrams related to FIG. 2.

5 is a detailed block diagram of a refresh circuit according to an embodiment of the present invention.

6 to 9 are operation timing diagrams related to FIG. 5.

Hereinafter, a refresh circuit of a semiconductor memory device according to an embodiment of the present invention will be described with reference to the accompanying drawings. Although shown in different drawings, components having the same or similar functions are represented by the same or similar reference numerals.

5 is a detailed block diagram of a refresh circuit according to an exemplary embodiment of the present invention. The configuration of FIG. 5 has a circuit block 320 in addition to the configuration of FIG. The circuit block 320 will be referred to as a forced refresh request signal generator in this embodiment for convenience. The forced refresh request signal generator 320 may read a pulse signal SPGL_WE and a read operation in response to an active transition of the write enable signals WEB and WE # in order to prevent a refresh failure that may occur during continuous write operations. The refresh request operation blocking signal NERFH is disabled in response to the dummy refresh pulse signal ATDD.

The forced refresh request signal generator 320 may transmit a dummy refresh pulse signal ATDD in response to the pulse signal SPGL_WE, and an inverter I1 that inverts the pulse signal SPGL_WE. An inverter latch L1 for latching the dummy refresh pulse signal ATDD output from the transfer gate PG1, an inverter I4 for inverting the output of the inverter latch L1, and an output of the inverter I4. And a NAND gate NAN1 for generating a NAND response by combining the pulse signal SPGL_WE, and an inverter IN5 for inverting the output of the NAND gate NAN1.

The forced refresh request signal output through the inverter IN5 is applied to the input of the NOA gate 330 to disable the refresh request operation blocking signal NERFH.

6 to 9 are operation timing diagrams related to FIG. 5. First, referring to FIGS. 6 and 7, the signals NERFHR and the signals NERFHW respectively generated during the read operation and the write operation are shown. The signal NERFHR is generated by the NOR gate 313 in FIG. 5, and the signal NERFHW is generated by the NOR gate 316 in FIG. 5.

In a relatively long cycle as shown in the timing diagram shown in FIG. 8, the waveform of the refresh request operation cutoff signal NERFH has a low period as indicated by the symbol?. That is, the row period indicated by the symbol ① is generated by orgating the signal NERFHR and the signal NERFHW. In an operation cycle shorter than FIG. 8 as shown in the timing diagram of FIG. 9, there may not be a section in which both the signal NERFHR and the signal NERFHW go low, so the signal NERFH does not have a low section as shown in FIG. 4. You may not. As a result, there is a possibility of a refresh fail. However, in the embodiment of the present invention, even when the continuous write operation is performed in the high speed operation cycle, as shown in FIG. This is achieved by the operation of the forced refresh request signal generator 320. Since the forced refresh request signal generator 320 receives the signals SPGL_WE and ATDD described through the above description, the forced refresh request signal generator 320 operates from the second write operation section during the continuous write operation to generate a low pulse to generate a noah gate ( 319). As a result, the generated low pulse period is the same as the shape in response to the write enable signal.

As shown in the signal NERFH, the row sections indicated by the symbols ②, ③, and ④ are signals generated by the forced refresh request signal generator 320. Accordingly, even in the high-speed operation cycle, the row sections indicated by the symbols ②, ③, and ④ are forcibly displayed even though the row sections indicated by the symbol ① do not appear.

As described above, when the NERFH continues to be in a high state without having a low section due to a lack of margin between NERFHW and NERFHR in the high speed operation, the NERFH has a low section by the operation of the forced refresh request signal generator 320. do. Therefore, the refresh operation can be performed in the continuous write cycle operation section, thereby minimizing the probability of occurrence of the refresh fail, and performing the fast write operation, thereby improving the write cycle time.

It will be understood by those skilled in the art that the concepts presented herein may be applied in a variety of different ways to a particular application.

In addition, the disclosed internal timing signals represent some of the operating methods according to the present invention, and there may be many other methods that are more efficient and available to circuit designers. Accordingly, specific implementations thereof are intended to be included within the invention and do not depart from the scope of the claims.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the appended claims, but also by those equivalent to the claims.

According to the refresh type semiconductor memory device of the present invention having a refresh circuit for minimizing the refresh fail in the high speed operation as described above, the refresh fail is prevented in the continuous write operation cycle and the write cycle time is improved.

Claims (6)

A refresh type semiconductor memory device in which a plurality of refresh type memory cells and a refresh operation are performed internally and without refreshing, while performing a refresh operation. In order to prevent a refresh fail that may occur during successive write operations, a forced refresh that disables the refresh request operation blocking signal in response to a signal in response to an active transition of the write enable signal and a dummy refresh signal generated in a read operation. And a refresh circuit having a request signal generator. 2. The refresh type semiconductor memory device according to claim 1, wherein the signal in response to the active transition of the write enable signal and the dummy refresh signal generated during the read operation are pulse signals, respectively. The data transmission method of claim 1, wherein the forced refresh request signal generation unit comprises: a transmission gate configured to output the dummy refresh signal in response to a signal in response to an active transition of the write enable signal, and the dummy refresh signal output from the transmission gate; A refresh type semiconductor comprising: an inverter latch for latching, an inverter for inverting an output of the inverter latch, and an ora gate for generating an ora response by combining an output of the inverter and a signal in response to the active transition. Memory device. A refresh type semiconductor memory device in which a plurality of refresh type memory cells and a refresh operation are performed internally and without refreshing, while performing a refresh operation. A read / write pulse control circuit configured to generate a refresh request operation cutoff signal by arranging a read refresh request operation cutoff signal and a write refresh request operation cutoff signal, and apply the generated signal to the refresh control circuit; In order to prevent a refresh fail that may occur during continuous write operations, the refresh request operation blocking signal may be disabled in response to a signal in response to an active transition of the write enable signal and a dummy refresh signal generated in a read operation. Refresh request signal generator, The refresh type semiconductor memory device, characterized in that it has a refresh circuit. The data transmission method of claim 4, wherein the forced refresh request signal generation unit comprises: a transmission gate outputting the dummy refresh signal in response to a signal in response to an active transition of the write enable signal, and the dummy refresh signal output from the transmission gate. An inverter latch for latching a signal; an inverter for inverting the output of the inverter latch; a NAND gate for generating a NAND response by combining the output of the inverter and the signal in response to the active transition; and inverting the output of the NAND gate. A refresh type semiconductor memory device comprising an inverter. A method of guaranteeing a refresh period in a semiconductor memory device having a dummy period during read / write in order to perform a refresh operation internally using a refresh entry blocking signal among semiconductor memory devices having a DRAM cell structure and performing an SRAM interface: When a read operation has a read dummy section and a read operation section, a write operation section has a write dummy section and a write operation section, and the sum of the read / write dummy section and the operation section is defined as a refresh blocking section. And generating a separate refresh entry signal by a signal generated when a next write operation is performed in the read dummy section to ensure a refresh section.