KR20040017129A - method for forming a capacitor - Google Patents

Abstract

PURPOSE: A method for forming a capacitor is provided to be capable of obtaining a cylinder type storage node having a double mode. CONSTITUTION: A BPSG(BoroPhosphorSilicate Glass) structure(22) is formed at the upper portion of a substrate(10). At this time, the BPSG structure is formed by alternately depositing a plurality of BPSG layers(22a,22b) having a different concentration. A TEOS(Tetra Ethyl Ortho Silicate) layer(18) is deposited on the BPSG structure. A storage node hole(20) is formed at the predetermined portion of the resultant structure by sequentially etching the TEOS layer and the BPSG structure. A storage node(24) is formed at the inner portion of the storage node hole. A dielectric layer and a plate electrode are formed at the upper portion of the storage node.

Description

Method for forming a capacitor

The present invention relates to a method of forming a capacitor, and more particularly, to a method of forming a capacitor in a semiconductor device in which the area of a storage electrode is easily expanded.

In recent years, as the semiconductor memory device becomes more integrated, the area of a unit cell decreases and the cell storage capacity also decreases. In particular, a DRAM having a capacitor and a switching transistor has a problem in that a read out capability is lowered and a soft error is increased due to a decrease in a capacitor's accumulation capacity due to a decrease in cell area. .

Therefore, as a method for increasing the storage capacity of the capacitor, methods for extending the surface area of the storage electrode, which is the lower electrode of the capacitor, reducing the thickness of the dielectric film, or using a high dielectric film having a high dielectric constant are proposed. have. However, the method of reducing the thickness of the dielectric film has a problem that the leakage current is increased or the breakdown voltage is reduced. In addition, the method of using the high dielectric film is still limited in commercialization because the research is currently in progress. Therefore, at present, a method of expanding the surface area of a capacitor is mainly used.

As an example of a method of extending the surface area of the capacitor, there is a method of forming the structure of the storage electrode into a stack, cylinder, fin, or trench. In particular, examples of the method for forming the cylindrical storage electrode are disclosed in Korean Patent Publication No. 2001-83402, Korean Patent Publication No. 2001-73561, Korean Patent Publication No. 2001-4189, and US Patent 2001-4189. .

In addition, another example of the method of expanding the surface area may be a method of forming the height of the capacitor high. However, when the capacitor is formed through the above method, the capacitor collapses frequently because the bottom line width of the storage node hole is not easily secured. Accordingly, the fall phenomenon is minimized by forming the capacitor in the double mode.

However, each of the above methods has limitations in forming a capacitor which requires a recent higher storage capacity.

It is an object of the present invention to provide a method of forming a capacitor comprising a storage electrode having a cylinder type and a double mode.

1A to 1F are cross-sectional views illustrating a method of forming a capacitor according to an embodiment of the present invention.

2A to 2F are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device using the method of the present invention.

The present invention for achieving the above object, the step of repeatedly stacking a BPSG film having a different concentration on the substrate at least twice, the step of laminating a TEOS film on the BPSG film, the TEOS film and the BPSG film sequentially Etching to form a storage node hole exposing the substrate surface, etching a substrate having the storage node hole to remove a portion of the high concentration BPSG film from the BPSG film, and by the storage node hole Forming a storage electrode being designed; And forming a dielectric film and a plate electrode on the storage electrode.

In this manner, a capacitor including a cylinder type and a storage electrode having a double mode can be formed by the above method. Therefore, a fall does not occur and a capacitor which requires a higher storage capacity can be easily formed.

Hereinafter, the present invention will be described in detail.

Referring to FIG. 1A, BPSG films 12 having different concentrations are repeatedly stacked on the substrate 10. That is, the first BBPSG film 12a at low concentration, the second BBPSG film 12b at high concentration, the first BBPSG film 12a at low concentration, the second BBPSG film 12b at high concentration, the first BBPSG film 12a at low concentration, and the first agent at high concentration The 2BPSG films 12b are sequentially stacked. Here, it is preferable that the repetitive lamination is at least twice. The concentration of the BPSG film 12 is preferably adjusted by boron B contained in the BPSG film 12. Subsequently, a TEOS film 14 is laminated on the BPSG film 12.

Referring to FIG. 1B, the TEOS film 14 and the BPSG film 12 are sequentially etched. As a result, the TEOS film pattern 18 and the first BPSG film pattern 16 are formed. The storage node hole 20 exposing the surface of the substrate 10 is formed by the TEOS film pattern 18 and the BPSG film pattern 16. The storage node hole 20 is formed by dry etching using gas. At this time, the bottom line width of the storage node hole 20 can be easily secured because the BPSG film 12 is located below.

Referring to FIG. 1C, the substrate 10 including the resultant storage node hole 20 is etched. As a result, a second BPSG film pattern 22 in which a part of the high concentration BPSG film 16b is removed from the BPSG film pattern 16 is formed. The high concentration of BPSG film 16b is removed by wet etching using a chemical such as hydrofluoric acid (HF). In addition, when the concentration of boron contained in the BPSG film 12 is high, the etching is more easily performed. Therefore, the concentration of boron contained in the BPSG film 12 is adjusted.

1D and 1E, a storage electrode 26 designed by the storage node hole 20 is formed. Specifically, the storage electrode film 24 is stacked on the substrate 10 including the storage node hole 20 in which the high concentration BPSG film 22b is partially removed. That is, the storage electrode film 24 is formed in the storage node hole 20 and on the TEOS film pattern 18. Then, the storage electrode film 24 is polished. At this time, the polishing is accomplished by chemical mechanical polishing (CMP), and the polishing endpoint is the surface of the TEOS film pattern 18. Subsequently, the TEOS film pattern 18 and the second BPGS film pattern 22 are removed. As a result, the storage electrode 26 is formed.

Referring to FIG. 1F, a dielectric film 28 is stacked on a surface of the storage electrode 26, and then a plate electrode 30 including a plate electrode film is formed on the dielectric film 28. Accordingly, the capacitor C including the storage electrode 26, the dielectric layer 28, and the plate electrode 30 may be formed.

The present invention provides a method for forming the storage electrode, the method of forming a storage electrode having a double mode achieved by a double molding structure. In addition, a method of forming a portion of the cylinder in the double mode is provided. In this way, by forming in the double mode to minimize the collapse of the capacitor, by forming in a cylinder type it is possible to expand the surface area. Thus, the method can be actively applied to the formation of capacitors that require a higher accumulation capacity in recent years.

Hereinafter, a method of forming a capacitor of a semiconductor device to which the method of the present invention is applied will be described.

Referring to FIG. 2A, the trench structure 202 is formed on the substrate 200 by performing a conventional device isolation process. Thus, the substrate 200 is separated into an active region and an inactive region. In addition, impurities are partially implanted into the substrate 200 to form p-wells and n-wells. Subsequently, gate patterns 204 formed of polysilicon 204a, tungsten silicide 204b, and silicon nitride 204c are formed on the active region of the substrate 200, and serve as word lines of the DRAM device. The gate pattern 204 has a polyside structure in which polysilicon 204a and tungsten silicide 204b doped with a high concentration of impurities are stacked. In addition, a spacer 206 made of silicon nitride may be further formed on sidewalls of the gate pattern 204.

Subsequently, an impurity is implanted using the gate patterns 204 as a mask to form a source 205a / drain 205b on a surface portion of the substrate 200 that is connected to the gate patterns 204. As a result, a transistor structure including the gate pattern 204 and the source 205a / drain 205b is formed. Here, one of the source 205a / drain 205b of the transistor structure is a capacitor contact region connected to the lower electrode layer of the capacitor, and the other is a bit line contact region connected to the bit line structure. In the present embodiment, the source 205a of the transistor structure corresponds to the capacitor contact region, and the drain 205b of the transistor structure corresponds to the bit line contact region.

The capacitor contact pad 210a may be in contact with the lower electrode layer of the capacitor by filling polysilicon between the gate patterns 204 of the transistor structure, and the bit line contact pad may be in electrical contact with the bit line structure. 210b). Here, the polysilicon 210 filled in the capacitor contact region corresponds to the capacitor contact pad 210a, and the polysilicon 210 filled in the bit line contact region corresponds to the bit line contact pad 210b.

Referring to FIG. 2B, a bit line structure 220 is formed in electrical contact with the bit line contact pad 210b. Specifically, the first interlayer insulating layer 222 is sequentially stacked on the polysilicon 210 filled between the gate pattern 204 and the gate pattern 204 of the transistor structure. The first interlayer insulating layer 222 is partially etched through a conventional photolithography process to form a bit line contact hole 223 exposing the surface of the bit line contact pad 210b. Subsequently, tungsten 220a is sequentially stacked on the bit line contact hole 223 and the first interlayer insulating layer 222. As a result, tungsten 220a is completely filled in the bit line contact hole 223. Subsequently, silicon nitride 220b is laminated on tungsten 220a. The bit line structure 220 made of tungsten 220a and silicon nitride 220b is formed by partially etching the silicon nitride 220b and tungsten 220a through a conventional photolithography process.

Subsequently, silicon nitride is deposited on the bit line structure 220 and the first interlayer insulating layer 222. The silicon nitride is etched to form a spacer structure 224 formed of the silicon nitride on sidewalls of the bit line structure 220. Accordingly, the tungsten 220a of the bit line structure 220 is covered by the silicon nitride 220b of the mask layer and surrounded by the silicon nitride of the spacer structure 224.

Subsequently, the second interlayer insulating layer 230 is successively stacked on the bit line structure 220, the spacer structure 224, and the first interlayer insulating layer 222. The second interlayer insulating layer 230 is made of silicon oxide, and is deposited by high density plasma deposition.

Referring to FIG. 2C, the second interlayer insulating layer 230 and the first interlayer insulating layer 222 are sequentially etched to form a self-aligned contact hole 232 exposing the surface of the contact pad of the capacitor. The etching is achieved by a difference in etching rates of silicon nitride of the bit line structure 220 and the space structure 224 and silicon oxide of the second interlayer insulating layer 230 and the first interlayer insulating layer 222.

Referring to FIG. 2D, the lower electrode layer 234 of the capacitor is filled into the self-aligned contact hole 232. That is, the lower contact electrode layer 234 is stacked and then the lower contact electrode layer 234 is filled only in the self-aligned contact hole through polishing.

Referring to FIG. 2E, a storage electrode connected to the lower contact electrode layer is formed through the aforementioned method of FIGS. 1A to 1E. That is, a storage electrode having a cylinder type at the bottom and having a double mode as a whole is formed.

Referring to FIG. 2F, a dielectric layer is formed on a surface of the storage electrode, and a plate electrode, which is an upper electrode, is formed on the dielectric layer. Accordingly, a capacitor including the storage electrode, the dielectric layer, and the plate electrode is formed.

As described above, in the case of applying the method of the present invention, even if the capacitor is formed higher, sufficient line width is secured in the lower portion so that the capacitor does not collapse, and the surface area can be expanded by forming the structure in the lower portion. have.

According to the present invention, it is possible to easily form a capacitor including a storage electrode having a cylinder type and a double mode. Thus, no fall occurs, and a capacitor having a sufficient power storage capacity is provided. Therefore, the above method can be actively applied to the manufacture of semiconductor devices requiring high integration in recent years.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (4)

a) repeatedly depositing BPSG films having different concentrations on the substrate at least twice; b) stacking a TEOS film on the BPSG film; c) sequentially etching the TEOS film and the BPSG film to form a storage node hole exposing a substrate surface; d) etching the substrate having the storage node holes to remove a portion of the high concentration BPSG film from the BPSG film; e) forming a storage electrode designed by the storage node hole; And f) forming a dielectric film and a plate electrode on the storage electrode. The method of claim 1, wherein c) is achieved by dry etching. The method of claim 1, wherein d) is achieved by wet etching. The method of claim 1, wherein the BPSG film has different concentrations due to concentration differences of boron (B).